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/linux/drivers/net/can/ctucanfd/
H A DKconfig2 tristate "CTU CAN-FD IP core" if COMPILE_TEST
4 This driver adds support for the CTU CAN FD open-source IP core.
8 is available (https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top).
9 Implementation on Intel FPGA-based PCI Express board is available
10 from project (https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd) and
11 on Intel SoC from project (https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd).
15 tristate "CTU CAN-FD IP core PCI/PCIe driver"
19 This driver adds PCI/PCIe support for CTU CAN-FD IP core.
20 The project providing FPGA design for Intel EP4CGX15 based DB4CGX15
22 at https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd .
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/linux/drivers/watchdog/
H A Dpika_wdt.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PIKA FPGA based Watchdog Timer
29 #define DRV_NAME "PIKA-WDT"
50 void __iomem *fpga; member
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
76 * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in in pikawdt_reset()
80 unsigned reset = in_be32(pikawdt_private.fpga + 0x14); in pikawdt_reset()
81 /* enable with max timeout - 15 seconds */ in pikawdt_reset()
83 out_be32(pikawdt_private.fpga + 0x14, reset); in pikawdt_reset()
118 return -EBUSY; in pikawdt_open()
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/linux/Documentation/driver-api/
H A Dxillybus.rst2 Xillybus driver for generic FPGA interface
10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
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H A Dmen-chameleon-bus.rst31 ----------------------
35 based devices.
38 -----------------------------------------
40 The current implementation is limited to PCI and PCIe based carrier devices
44 - Multi-resource MCB devices like the VME Controller or M-Module carrier.
45 - MCB devices that need another MCB device, like SRAM for a DMA Controller's
47 - A per-carrier IRQ domain for carrier devices that have one (or more) IRQs
48 per MCB device like PCIe based carriers with MSI or MSI-X support.
55 - The MEN Chameleon Bus itself,
56 - drivers for MCB Carrier Devices and
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/linux/arch/powerpc/boot/
H A Debony.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Based on earlier code:
9 * Copyright 2002-2005 MontaVista Software Inc.
30 #define EBONY_FPGA_PATH "/plb/opb/ebc/fpga"
32 #define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash"
38 u8 *fpga; in ebony_flashsel_fixup() local
43 fatal("Couldn't locate FPGA node %s\n\r", EBONY_FPGA_PATH); in ebony_flashsel_fixup()
45 if (getprop(devp, "virtual-reg", &fpga, sizeof(fpga)) != sizeof(fpga)) in ebony_flashsel_fixup()
46 fatal("%s has missing or invalid virtual-reg property\n\r", in ebony_flashsel_fixup()
49 fpga_reg0 = in_8(fpga); in ebony_flashsel_fixup()
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/linux/Documentation/fpga/
H A Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <enno.luebbers@intel.com>
8 - Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 - Wu Hao <hao.wu@intel.com>
10 - Xu Yilun <yilun.xu@intel.com>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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/linux/include/uapi/linux/
H A Dfpga-dfl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Header File for FPGA DFL User API
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
23 * The IOCTL interface for DFL based FPGA is designed for extensibility by
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
60 * Reset the FPGA Port and its AFU. No parameters are supported.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
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/linux/drivers/mcb/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 FPGA based devices. It is used to identify MCB based IP-Cores within
14 an FPGA and provide the necessary framework for instantiating drivers
21 tristate "PCI based MCB carrier"
26 This is a MCB carrier on a PCI device. Both PCI attached on-board
30 If build as a module, the module is called mcb-pci.ko
33 tristate "LPC (non PCI) based MCB carrier"
39 If build as a module, the module is called mcb-lpc.ko
/linux/drivers/fpga/
H A Dts73xx-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Technologic Systems TS-73xx SBC FPGA loader
7 * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
8 * TS-7300, heavily based on load_fpga.c in their vendor tree.
17 #include <linux/fpga/fpga-mgr.h>
39 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write_init()
41 /* Reset the FPGA */ in ts73xx_fpga_write_init()
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
44 writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
53 struct ts73xx_fpga_priv *priv = mgr->priv; in ts73xx_fpga_write()
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/linux/arch/powerpc/boot/dts/fsl/
H A Dgef_ppc9a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
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H A Dgef_sbc310.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00010000>; // FPGA
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
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H A Dgef_sbc610.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Based on: SBS CM6 Device Tree Source
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
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H A Dge_imp3a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
7 * Based on: P2020 DS Device Tree Source
11 /include/ "p2020si-pre.dtsi"
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
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/linux/drivers/media/pci/cx23885/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
48 This is a video4linux driver for Conexant 23885 based
55 tristate "Altera FPGA based CI module"
59 An Altera FPGA CI module for NetUP Dual DVB-T/C RF CI card.
62 module will be called altera-ci
/linux/arch/powerpc/platforms/86xx/
H A Dgef_sbc310.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
26 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_sbc310_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); in gef_sbc310_init_irq()
61 printk(KERN_WARNING "SBC310: No FPGA PIC\n"); in gef_sbc310_init_irq()
81 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); in gef_sbc310_setup_arch()
121 /* Return the FPGA revision */
138 ('A' + gef_sbc310_get_board_rev() - 1)); in gef_sbc310_show_cpuinfo()
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H A Dgef_sbc610.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
26 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_sbc610_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic"); in gef_sbc610_init_irq()
61 printk(KERN_WARNING "SBC610: No FPGA PIC\n"); in gef_sbc610_init_irq()
82 regs = of_find_compatible_node(NULL, NULL, "gef,fpga-regs"); in gef_sbc610_setup_arch()
113 /* Return the FPGA revision */
129 ('A' + gef_sbc610_get_board_rev() - 1)); in gef_sbc610_show_cpuinfo()
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H A Dgef_ppc9a.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
12 * NEC fixup adapted from arch/mips/pci/fixup-lm2e.c
26 #include <asm/pci-bridge.h>
56 * There is a simple interrupt handler in the main FPGA, this needs in gef_ppc9a_init_irq()
59 cascade_node = of_find_compatible_node(NULL, NULL, "gef,fpga-pic-1.00"); in gef_ppc9a_init_irq()
61 printk(KERN_WARNING "PPC9A: No FPGA PIC\n"); in gef_ppc9a_init_irq()
82 regs = of_find_compatible_node(NULL, NULL, "gef,ppc9a-fpga-regs"); in gef_ppc9a_setup_arch()
113 /* Return the FPGA revision */
148 seq_printf(m, "FPGA Revision\t: %u\n", gef_ppc9a_get_fpga_rev()); in gef_ppc9a_show_cpuinfo()
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/linux/arch/powerpc/platforms/52xx/
H A Dmedia5200.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for 'media5200-platform' compatible boards.
11 * Notable characteristic of the Media5200 is the presence of an FPGA
30 { .compatible = "fsl,mpc5200-gpio", },
31 { .compatible = "mpc5200-gpio", },
35 /* FPGA register set */
39 #define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
73 .name = "Media5200 FPGA",
86 raw_spin_lock(&desc->lock); in media5200_irq_cascade()
87 chip->irq_mask(&desc->irq_data); in media5200_irq_cascade()
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/linux/arch/powerpc/platforms/85xx/
H A Dge_imp3a.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
25 #include <asm/pci-bridge.h>
47 if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) { in ge_imp3a_pic_init()
63 * There is a simple interrupt handler in the main FPGA, this needs in ge_imp3a_pic_init()
66 for_each_node_by_type(np, "interrupt-controller") in ge_imp3a_pic_init()
67 if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) { in ge_imp3a_pic_init()
73 printk(KERN_WARNING "IMP3A: No FPGA PIC\n"); in ge_imp3a_pic_init()
88 if (of_device_is_compatible(np, "fsl,mpc8540-pci") || in ge_imp3a_pci_assign_primary()
89 of_device_is_compatible(np, "fsl,mpc8548-pcie") || in ge_imp3a_pci_assign_primary()
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H A Dsocrates.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Based on MPC8560 ADS and arch/ppc tqm85xx ports
12 * Copyright (c) 2005-2006 DENX Software Engineering
15 * Based on original work by
30 #include <asm/pci-bridge.h>
50 np = of_find_compatible_node(NULL, NULL, "abb,socrates-fpga-pic"); in socrates_pic_init()
52 printk(KERN_ERR "Could not find socrates-fpga-pic node\n"); in socrates_pic_init()
/linux/Documentation/devicetree/bindings/bus/
H A Dxlnx,versal-net-cdx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 The CDX bus manages multiple FPGA based hardware devices, which
14 devices. These FPGA based devices can be added/modified dynamically
15 on run-time.
20 are used to configure SMMU and GIC-ITS respectively.
22 iommu-map property is used to define the set of stream ids
26 The msi-map property is used to associate the devices with the
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/linux/drivers/memory/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
96 SoCs. EMIF is an SDRAM controller that, based on its revision,
99 functions of the driver includes re-configuring AC timing
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/linux/drivers/gpio/
H A Dgpio-ge.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for GE FPGA based GPIO
13 * Configuration of output modes (totem-pole/open-drain).
14 * Interrupt configuration - interrupts are always generated, the FPGA relies
39 .compatible = "gef,sbc610-gpio",
42 .compatible = "gef,sbc310-gpio",
45 .compatible = "ge,imp3a-gpio",
54 struct device *dev = &pdev->dev; in gef_gpio_probe()
61 return -ENOMEM; in gef_gpio_probe()
74 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", dev_fwnode(dev)); in gef_gpio_probe()
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/linux/arch/sh/boards/mach-se/7343/
H A Dirq.c1 // SPDX-License-Identifier: GPL-2.0
3 * Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
8 * Based on linux/arch/sh/boards/se/7343/irq.c
11 #define DRV_NAME "SE7343-FPGA"
20 #include <mach-se/mach/se7343.h>
36 chip->irq_mask_ack(data); in se7343_irq_demux()
43 chip->irq_unmask(data); in se7343_irq_demux()
80 ct = gc->chip_types; in se7343_gc_init()
81 ct->chip.irq_mask = irq_gc_mask_set_bit; in se7343_gc_init()
82 ct->chip.irq_unmask = irq_gc_mask_clr_bit; in se7343_gc_init()
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/linux/arch/powerpc/platforms/44x/
H A Dppc476.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Based on earlier code:
10 * Copyright 2002-2005 MontaVista Software Inc.
13 * Copyright (c) 2003-2005 Zultys Technologies
98 { "akebono-avr" },
104 .name = "akebono-avr",
125 for_each_node_with_property(np, "interrupt-controller") { in ppc47x_init_irq()
133 if (of_device_is_compatible(np, "chrp,open-pic")) { in ppc47x_init_irq()
135 * device-tree, just pass 0 to all arguments in ppc47x_init_irq()
163 /* Assume spin table. We could test for the enable-method in in smp_ppc47x_kick_cpu()
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