Lines Matching +full:fpga +full:- +full:based

1 // SPDX-License-Identifier: GPL-2.0-or-later
7  * Based on: SBS CM6 Device Tree Source
14  * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
35 			  4 0 0xfc000000 0x00008000	// FPGA
36 			  5 0 0xfc008000 0x00008000	// AFIX FPGA
37 			  6 0 0xfd000000 0x00800000	// IO FPGA (8-bit)
38 			  7 0 0xfd800000 0x00800000>;	// IO FPGA (32-bit)
42 			compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 			bank-width = <4>;
45 			device-width = <2>;
46 			#address-cells = <1>;
47 			#size-cells = <1>;
51 				read-only;
57 			compatible = "gef,ppc9a-paged-flash", "cfi-flash";
59 			bank-width = <4>;
60 			device-width = <2>;
61 			#address-cells = <1>;
62 			#size-cells = <1>;
70 				read-only;
80 		fpga@4,0 {
81 			compatible = "gef,ppc9a-fpga-regs";
86 			compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
87 				"gef,fpga-wdt";
90 			interrupt-parent = <&gef_pic>;
94 			compatible = "gef,ppc9a-fpga-wdt", "gef,fpga-wdt-1.00",
95 				"gef,fpga-wdt";
98 			interrupt-parent = <&gef_pic>;
102 			#interrupt-cells = <1>;
103 			interrupt-controller;
104 			compatible = "gef,ppc9a-fpga-pic", "gef,fpga-pic-1.00";
110 			#gpio-cells = <2>;
111 			compatible = "gef,ppc9a-gpio", "gef,sbc610-gpio";
113 			gpio-controller;
143 			tbi-handle = <&tbi0>;
144 			phy-handle = <&phy0>;
145 			phy-connection-type = "gmii";
149 			phy0: ethernet-phy@0 {
150 				interrupt-parent = <&gef_pic>;
154 			phy2: ethernet-phy@2 {
155 				interrupt-parent = <&gef_pic>;
159 			tbi0: tbi-phy@11 {
161 				device_type = "tbi-phy";
166 			tbi-handle = <&tbi2>;
167 			phy-handle = <&phy2>;
168 			phy-connection-type = "gmii";
172 			tbi2: tbi-phy@11 {
174 				device_type = "tbi-phy";
216 /include/ "mpc8641si-post.dtsi"