| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | altera-a10sr.txt | 1 * Altera Arria10 Development Kit System Resource Chip
6 - reg : The SPI Chip Select address for the Arria10
22 Arria10 GPIO
30 Arria10 Peripheral PHY Reset
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | altera.yaml | 27 - altr,socfpga-arria10-socdk
28 - const: altr,socfpga-arria10
37 - const: altr,socfpga-arria10
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| /linux/arch/arm/boot/dts/intel/socfpga/ |
| H A D | socfpga_arria10_mercury_aa1.dtsi | 11 compatible = "enclustra,mercury-aa1", "altr,socfpga-arria10", "altr,socfpga";
71 /* Following mappings are taken from arria10 socdk dts */
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| H A D | socfpga_arria10_socdk.dtsi | 9 compatible = "altr,socfpga-arria10-socdk", "altr,socfpga-arria10", "altr,socfpga";
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| H A D | socfpga_arria10_mercury_pe1.dts | 11 "altr,socfpga-arria10", "altr,socfpga";
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| H A D | socfpga_arria10_chameleonv3.dts | 11 "altr,socfpga-arria10", "altr,socfpga";
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| /linux/include/linux/mfd/ |
| H A D | altera-a10sr.h | 5 * Declarations for Altera Arria10 MAX5 System Resource Chip
35 /* Arria10 System Controller Register Defines */
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| /linux/arch/arm/mach-socfpga/ |
| H A D | socfpga.c | 108 "altr,socfpga-arria10",
112 DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
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| H A D | ocram.c | 41 /* Arria10 OCRAM Section */
89 * This function uses the memory initialization block in the Arria10 ECC
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| /linux/drivers/gpio/ |
| H A D | gpio-altera-a10sr.c | 5 * GPIO driver for Altera Arria10 MAX5 System Resource Chip
115 MODULE_DESCRIPTION("Altera Arria10 System Resource Chip GPIO");
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| H A D | Kconfig | 1287 tristate "Altera Arria10 System Resource GPIO"
1290 Driver for Arria10 Development Kit GPIO expansion which
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| /linux/drivers/reset/ |
| H A D | reset-a10sr.c | 5 * Reset driver for Altera Arria10 MAX5 System Resource Chip
127 MODULE_DESCRIPTION("Altera Arria10 System Resource Reset Controller Driver");
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| H A D | Kconfig | 19 tristate "Altera Arria10 System Resource Reset"
23 peripheral PHYs on the Altera Arria10 System Resource Chip.
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| /linux/drivers/mfd/ |
| H A D | altera-a10sr.c | 3 * Altera Arria10 DevKit System Resource MFD Driver
9 * SPI access for Altera Arria10 MAX5 System Resource Chip
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| /linux/Documentation/devicetree/bindings/fpga/ |
| H A D | altera-pr-ip.txt | 1 Altera Arria10 Partial Reconfiguration IP
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| H A D | altera-socfpga-a10-fpga-mgr.txt | 1 Altera SOCFPGA Arria10 FPGA Manager
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| /linux/include/dt-bindings/reset/ |
| H A D | altr,rst-mgr-a10sr.h | 5 * Reset binding definitions for Altera Arria10 MAX5 System Resource Chip
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| /linux/drivers/edac/ |
| H A D | altera_edac.c | 350 /* Arria10 has a 2nd IRQ */ in altr_sdram_probe()
396 /* Only the Arria10 has separate IRQs */ in altr_sdram_probe()
397 if (of_machine_is_compatible("altr,socfpga-arria10")) { in altr_sdram_probe()
398 /* Arria10 specific initialization */ in altr_sdram_probe()
826 /******************* Arria10 Device ECC Shared Functions *****************/
875 /******************* Arria10 Memory Buffer Functions *********************/
912 * This function uses the memory initialization block in the Arria10 ECC
1690 /********************* Arria10 EDAC Device Functions *************************/
1726 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1760 * The Stratix10 EDAC Error Injection Functions differ from Arria10
[all …]
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| H A D | altera_edac.h | 214 /* Arria10 General ECC Block Module Defines */
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| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | altr,rst-mgr.yaml | 15 - description: Cyclone5/Arria5/Arria10
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| /linux/Documentation/devicetree/bindings/arm/altera/ |
| H A D | socfpga-clk-manager.yaml | 14 tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
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