1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright 2022 Google LLC 4*724ba675SRob Herring */ 5*724ba675SRob Herring/dts-v1/; 6*724ba675SRob Herring#include "socfpga_arria10_mercury_aa1.dtsi" 7*724ba675SRob Herring 8*724ba675SRob Herring/ { 9*724ba675SRob Herring model = "Google Chameleon V3"; 10*724ba675SRob Herring compatible = "google,chameleon-v3", "enclustra,mercury-aa1", 11*724ba675SRob Herring "altr,socfpga-arria10", "altr,socfpga"; 12*724ba675SRob Herring 13*724ba675SRob Herring aliases { 14*724ba675SRob Herring serial0 = &uart0; 15*724ba675SRob Herring i2c0 = &i2c0; 16*724ba675SRob Herring i2c1 = &i2c1; 17*724ba675SRob Herring }; 18*724ba675SRob Herring}; 19*724ba675SRob Herring 20*724ba675SRob Herring&gmac0 { 21*724ba675SRob Herring status = "okay"; 22*724ba675SRob Herring}; 23*724ba675SRob Herring 24*724ba675SRob Herring&gpio0 { 25*724ba675SRob Herring status = "okay"; 26*724ba675SRob Herring}; 27*724ba675SRob Herring 28*724ba675SRob Herring&gpio1 { 29*724ba675SRob Herring status = "okay"; 30*724ba675SRob Herring}; 31*724ba675SRob Herring 32*724ba675SRob Herring&gpio2 { 33*724ba675SRob Herring status = "okay"; 34*724ba675SRob Herring}; 35*724ba675SRob Herring 36*724ba675SRob Herring&i2c0 { 37*724ba675SRob Herring status = "okay"; 38*724ba675SRob Herring 39*724ba675SRob Herring ssm2603: audio-codec@1a { 40*724ba675SRob Herring compatible = "adi,ssm2603"; 41*724ba675SRob Herring reg = <0x1a>; 42*724ba675SRob Herring }; 43*724ba675SRob Herring}; 44*724ba675SRob Herring 45*724ba675SRob Herring&i2c1 { 46*724ba675SRob Herring status = "okay"; 47*724ba675SRob Herring 48*724ba675SRob Herring u80: gpio@21 { 49*724ba675SRob Herring compatible = "nxp,pca9535"; 50*724ba675SRob Herring reg = <0x21>; 51*724ba675SRob Herring gpio-controller; 52*724ba675SRob Herring #gpio-cells = <2>; 53*724ba675SRob Herring 54*724ba675SRob Herring gpio-line-names = 55*724ba675SRob Herring "SOM_AUD_MUTE", 56*724ba675SRob Herring "DP1_OUT_CEC_EN", 57*724ba675SRob Herring "DP2_OUT_CEC_EN", 58*724ba675SRob Herring "DP1_SOM_PS8469_CAD", 59*724ba675SRob Herring "DPD_SOM_PS8469_CAD", 60*724ba675SRob Herring "DP_OUT_PWR_EN", 61*724ba675SRob Herring "STM32_RST_L", 62*724ba675SRob Herring "STM32_BOOT0", 63*724ba675SRob Herring 64*724ba675SRob Herring "FPGA_PROT", 65*724ba675SRob Herring "STM32_FPGA_COMM0", 66*724ba675SRob Herring "TP119", 67*724ba675SRob Herring "TP120", 68*724ba675SRob Herring "TP121", 69*724ba675SRob Herring "TP122", 70*724ba675SRob Herring "TP123", 71*724ba675SRob Herring "TP124"; 72*724ba675SRob Herring }; 73*724ba675SRob Herring}; 74*724ba675SRob Herring 75*724ba675SRob Herring&mmc { 76*724ba675SRob Herring status = "okay"; 77*724ba675SRob Herring}; 78*724ba675SRob Herring 79*724ba675SRob Herring&uart0 { 80*724ba675SRob Herring status = "okay"; 81*724ba675SRob Herring}; 82*724ba675SRob Herring 83*724ba675SRob Herring&uart1 { 84*724ba675SRob Herring status = "okay"; 85*724ba675SRob Herring}; 86*724ba675SRob Herring 87*724ba675SRob Herring&usb0 { 88*724ba675SRob Herring status = "okay"; 89*724ba675SRob Herring dr_mode = "host"; 90*724ba675SRob Herring}; 91