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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Davxvnniint8intrin.h1 /*===-------- avxvnniint8intrin.h - AVXVNNIINT8 intrinsics -----------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
25 /// Multiply groups of 4 adjacent pairs of signed 8-bit integers in \a __A with
26 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate
27 /// signed 16-bit results. Sum these 4 results with the corresponding
28 /// 32-bit integer in \a __W, and store the packed 32-bit results in \a dst.
39 /// A 128-bit vector of [16 x char].
41 /// A 128-bit vector of [16 x char].
43 /// A 128-bit vector of [4 x int].
[all …]
H A Dxmmintrin.h1 /*===---- xmmintrin.h - SSE intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
36 __attribute__((__always_inline__, __nodebug__, __target__("sse,no-evex512"), \
40 __target__("mmx,sse,no-evex512"), __min_vector_width__(64)))
42 /// Adds the 32-bit float values in the low-order bits of the operands.
49 /// A 128-bit vector of [4 x float] containing one of the source operands.
52 /// A 128-bit vector of [4 x float] containing one of the source operands.
54 /// \returns A 128-bit vector of [4 x float] whose lower 32 bits contain the sum
64 /// Adds two 128-bit vectors of [4 x float], and returns the results of
[all …]
H A Dmmintrin.h1 /*===---- mmintrin.h - MMX intrinsics --------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
26 __attribute__((__always_inline__, __nodebug__, __target__("mmx,no-evex512"), \
37 __target__("mmx,no-evex512")))
42 /// Constructs a 64-bit integer vector, setting the lower 32 bits to the
43 /// value of the 32-bit integer parameter and setting the upper 32 bits to 0.
50 /// A 32-bit integer value.
51 /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the
59 /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit
[all …]
H A Dfmaintrin.h1 /*===---- fmaintrin.h - FMA intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
21 /// Computes a multiply-add of 128-bit vectors of [4 x float].
29 /// A 128-bit vector of [4 x float] containing the multiplicand.
31 /// A 128-bit vector of [4 x float] containing the multiplier.
33 /// A 128-bit vector of [4 x float] containing the addend.
34 /// \returns A 128-bit vector of [4 x float] containing the result.
41 /// Computes a multiply-add of 128-bit vectors of [2 x double].
49 /// A 128-bit vector of [2 x double] containing the multiplicand.
[all …]
H A Dshaintrin.h1 /*===---- shaintrin.h - SHA intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
20 /// Performs four iterations of the inner loop of the SHA-1 message digest
21 /// algorithm using the starting SHA-1 state (A, B, C, D) from the 128-bit
22 /// vector of [4 x i32] in \a V1 and the next four 32-bit elements of the
23 /// message from the 128-bit vector of [4 x i32] in \a V2. Note that the
24 /// SHA-1 state variable E must have already been added to \a V2
26 /// SHA-1 state (A, B, C, D) as a 128-bit vector of [4 x i32].
28 /// The SHA-1 algorithm has an inner loop of 80 iterations, twenty each
[all …]
H A Davxvnniintrin.h1 /*===--------------- avxvnniintrin.h - VNNI intrinsics --------------------===
22 *===-----------------------------------------------------------------------===
46 /// Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in \a __A with
47 /// corresponding signed 8-bit integers in \a __B, producing 4 intermediate signed
48 /// 16-bit results. Sum these 4 results with the corresponding 32-bit integer
49 /// in \a __S, and store the packed 32-bit results in DST.
55 /// tmp1.word := Signed(ZeroExtend16(__A.byte[4*j]) * SignExtend16(__B.byte[4*j]))
56 /// tmp2.word := Signed(ZeroExtend16(__A.byte[4*j+1]) * SignExtend16(__B.byte[4*j+1]))
57 /// tmp3.word := Signed(ZeroExtend16(__A.byte[4*j+2]) * SignExtend16(__B.byte[4*j+2]))
58 /// tmp4.word := Signed(ZeroExtend16(__A.byte[4*j+3]) * SignExtend16(__B.byte[4*j+3]))
[all …]
H A Davxintrin.h1 /*===---- avxintrin.h - AVX intrinsics -------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
54 __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \
57 __attribute__((__always_inline__, __nodebug__, __target__("avx,no-evex512"), \
61 /// Adds two 256-bit vectors of [4 x double].
68 /// A 256-bit vector of [4 x double] containing one of the source operands.
70 /// A 256-bit vector of [4 x double] containing one of the source operands.
71 /// \returns A 256-bit vector of [4 x double] containing the sums of both
79 /// Adds two 256-bit vectors of [8 x float].
[all …]
H A Dsmmintrin.h1 /*===---- smmintrin.h - SSE4 intrinsics ------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
22 __target__("sse4.1,no-evex512"), __min_vector_width__(128)))
41 /// Rounds up each element of the 128-bit vector of [4 x float] to an
42 /// integer and returns the rounded values in a 128-bit vector of
43 /// [4 x float].
54 /// A 128-bit vector of [4 x float] values to be rounded up.
55 /// \returns A 128-bit vector of [4 x float] containing the rounded values.
58 /// Rounds up each element of the 128-bit vector of [2 x double] to an
[all …]
H A Dtmmintrin.h1 /*===---- tmmintrin.h - SSSE3 intrinsics -----------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
22 __target__("ssse3,no-evex512"), __min_vector_width__(64)))
25 __target__("mmx,ssse3,no-evex512"), \
28 /// Computes the absolute value of each of the packed 8-bit signed
29 /// integers in the source operand and stores the 8-bit unsigned integer
37 /// A 64-bit vector of [8 x i8].
38 /// \returns A 64-bit integer vector containing the absolute values of the
46 /// Computes the absolute value of each of the packed 8-bit signed
[all …]
/freebsd/secure/lib/libcrypto/man/man3/
H A DOPENSSL_ia32cap.318 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
98 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dmach2 #------------------------------------------------------------
8 #------------------------------------------------------------
9 # if set, it's for the 64-bit version of the architecture
10 # yes, this is separate from the low-order magic number bit
11 # it's also separate from the "64-bit libraries" bit in the
14 # Reference: https://opensource.apple.com/source/cctools/cctools-949.0.1/
15 # include/mach-o/loader.h
17 0 name mach-o-cpu
20 # 32-bit ABIs.
24 >>>4 belong&0x00ffffff 0 vax
[all …]
/freebsd/contrib/wpa/src/common/
H A Dieee802_11_defs.h3 * Copyright (c) 2002-2019, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008 Intel Corporation
35 #define WLAN_FC_GET_STYPE(fc) (((fc) & 0x00f0) >> 4)
39 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
41 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
53 #define WLAN_FC_STYPE_PROBE_REQ 4
76 #define WLAN_FC_STYPE_NULLFUNC 4
97 #define WLAN_AUTH_FILS_SK 4
105 #define WLAN_CAPABILITY_ESS BIT(0)
106 #define WLAN_CAPABILITY_IBSS BIT(1)
[all …]
H A Ddefs.h2 * WPA Supplicant - Common definitions
3 * Copyright (c) 2004-2018, Jouni Malinen <j@w1.fi>
12 #define WPA_CIPHER_NONE BIT(0)
13 #define WPA_CIPHER_WEP40 BIT(1)
14 #define WPA_CIPHER_WEP104 BIT(2)
15 #define WPA_CIPHER_TKIP BIT(3)
16 #define WPA_CIPHER_CCMP BIT(4)
17 #define WPA_CIPHER_AES_128_CMAC BIT(5)
18 #define WPA_CIPHER_GCMP BIT(6)
19 #define WPA_CIPHER_SMS4 BIT(7)
[all …]
/freebsd/sys/dev/dpaa2/
H A Ddpaa2_ni_dpkg.h1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause AND BSD-2-Clause
4 * Copyright © 2013-2015 Freescale Semiconductor, Inc.
36 * Commit: 4c86114194e644b6da9107d75910635c9e87179e
41 * Copyright © 2021-2022 Dmitry Salychev
68 #define BIT(x) (1ul << (x)) macro
71 * DPKG_NUM_OF_MASKS - Number of masks per key extraction
73 #define DPKG_NUM_OF_MASKS 4
76 * DPKG_MAX_NUM_OF_EXTRACTS - Number of extractions per key profile
81 * enum dpkg_extract_from_hdr_type - Selecting extraction by header types
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
30 #define MT_INT_TX_DONE_ALL GENMASK(19, 4)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
[all …]
/freebsd/sys/contrib/dev/iwlwifi/fw/api/
H A Drs.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation
12 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags
27 IWL_TLC_MNG_CFG_FLAGS_STBC_MSK = BIT(0),
28 IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK = BIT(
[all...]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE])
40 #define MT_TOP_3NSS BIT(24)
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
59 #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2])
62 #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2])
69 #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs))
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
14 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0)
15 #define DATA_RATE_HT_IDX_MASK_V1 GENMASK(4, 0)
17 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4)
20 #define DATA_RATE_MCS_MASK_V1 GENMASK(4, 0)
27 if (rtwdev->chi in rtw89_get_data_rate_mode()
[all...]
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
18 #define BAC_OOBS_SEL BIT(4)
20 #define B_BAC_EQ_SEL BIT(5)
22 #define B_PCIE_BIT_PSAVE BIT(15)
24 #define BAC_RX_TEST_EN BIT(
[all...]
/freebsd/sys/amd64/vmm/amd/
H A Damdvi_priv.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
37 #define BIT(n) (1ULL << (n)) macro
38 /* Return value of bits[n:m] where n and (n >= ) m are bit positions. */
40 ((1 << (((n) - (m)) + 1)) - 1))
45 #define AMDVI_PCI_CAP_IOTLB BIT(0) /* IOTLB is supported. */
46 #define AMDVI_PCI_CAP_HT BIT(1) /* HyperTransport tunnel support. */
47 #define AMDVI_PCI_CAP_NPCACHE BIT(2) /* Not present page cached. */
48 #define AMDVI_PCI_CAP_EFR BIT(3) /* Extended features. */
49 #define AMDVI_PCI_CAP_EXT BIT(4) /* Miscellaneous information reg. */
[all …]
/freebsd/secure/usr.bin/openssl/man/
H A Dopenssl-enc.118 .\" Set up some character translations and predefined strings. \*(-- will
24 .tr \(*W-
27 . ds -- \(*W-
29 . if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
30 . if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
37 . ds -- \|\(em\|
71 .\" Fear. Run. Save yourself. No user-serviceable parts.
81 . ds #H ((1u-(\\\\n(.fu%2u))*.13m)
97 . ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
98 . ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_regs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -4
[all...]
/freebsd/sys/dev/ice/
H A Dice_adminq_cmd.h1 /* SPDX-License-Identifier: BSD-3-Clause */
79 u8 reserved[4];
87 #define ICE_AQC_DRIVER_UNLOADING BIT(0)
107 #define ICE_AQC_RES_ID_GLBL_LOCK 4
203 /* Manage MAC address, read command - indirect (0x0107)
208 #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
[all...]

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