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/linux/drivers/gpu/drm/i915/display/
H A Dintel_qp_tables.c1 // SPDX-License-Identifier: MIT
43 { 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
45 { 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
47 { 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
49 { 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1,
51 { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1,
53 { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
55 { 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
57 { 6, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
58 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
[all …]
/linux/lib/crypto/powerpc/
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
13 # 3. a += b; d ^= a; d <<<= 8;
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
78 stdu 1,-752(1)
99 addi 9, 1, 256
100 SAVE_VRS 20, 0, 9
101 SAVE_VRS 21, 16, 9
102 SAVE_VRS 22, 32, 9
[all …]
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
26 # to 9 vectors for multiplications.
28 # setup r^4, r^3, r^2, r vectors
29 # vs [r^1, r^3, r^2, r^4]
[all …]
H A Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
89 ld 9,16(4)
104 mulld 26,9,6
105 mulhdu 27,9,6
[all …]
/linux/tools/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
96 #define PSTATE_UAO pstate_field(0, 3)
[all …]
/linux/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
17 #include <asm/gpr-num.h>
23 * [20-19] : Op0
24 * [18-16] : Op1
25 * [15-12] : CRn
26 * [11-8] : CRm
27 * [7-5] : Op2
84 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
97 #define PSTATE_UAO pstate_field(0, 3)
[all …]
/linux/drivers/clk/renesas/
H A Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
76 {3, 8},
90 {3, 16},
98 {3, 16},
125 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
126 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
127 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
[all …]
H A Dr9a09g047-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
73 {3, 8},
87 {3, 16},
95 {3, 16},
122 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
123 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
124 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
[all …]
H A Dr9a09g056-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
68 {3, 8},
76 {3, 16},
84 {3, 16},
111 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
112 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
113 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
[all …]
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Drate.c29 /* 0 1 2 3 4 5 6 7 8 9 */
46 {6500, 13500, CEIL(6500 * 10, 9), CEIL(13500 * 10, 9), 0x00,
49 {13000, 27000, CEIL(13000 * 10, 9), CEIL(27000 * 10, 9), 0x08,
51 /* MCS 2: SS 1, MOD: QPSK, CR 3/4 */
52 {19500, 40500, CEIL(19500 * 10, 9), CEIL(40500 * 10, 9), 0x0A,
54 /* MCS 3: SS 1, MOD: 16QAM, CR 1/2 */
55 {26000, 54000, CEIL(26000 * 10, 9), CEIL(54000 * 10, 9), 0x10,
57 /* MCS 4: SS 1, MOD: 16QAM, CR 3/4 */
58 {39000, 81000, CEIL(39000 * 10, 9), CEIL(81000 * 10, 9), 0x12,
60 /* MCS 5: SS 1, MOD: 64QAM, CR 2/3 */
[all …]
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7,8,9",
8 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
15 "Counter": "0,1,2,3,4,5,6,7,8,9",
26 "Counter": "0,1,2,3,4,5,6,7,8,9",
36 "Counter": "0,1,2,3,4,5,6,7,8,9",
45 "Counter": "0,1,2,3,4,5,6,7",
54 "Counter": "0,1,2,3,4,5,6,7,8,9",
63 "Counter": "0,1,2,3,4,5,6,7,8,9",
73 "Counter": "0,1,2,3,4,5,6,7",
83 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
H A Dfrontend.json4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
17 …"PublicDescription": "Number of times the front-end is resteered when it finds a branch instructio…
24 "Counter": "0,1,2,3,4,5,6,7",
33 "Counter": "0,1,2,3,4,5,6,7",
42 "Counter": "0,1,2,3,4,5,6,7",
51 "Counter": "0,1,2,3,4,5,6,7",
60 "Counter": "0,1,2,3,4,5,6,7,8,9",
63 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length …
70 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
/linux/include/dt-bindings/memory/
H A Dmt8195-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
20 * modules dma-address-region larbs-ports
21 * disp 0 ~ 4G larb0/1/2/3
26 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
38 #define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3)
46 #define M4U_PORT_L1_DISP_OVL0_RDMA1 MTK_M4U_ID(1, 3)
54 #define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(2, 3)
[all …]
H A Dmediatek,mt6893-memory-port.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
10 #include <dt-bindings/memory/mtk-memory-port.h>
17 * modules dma-address-region larbs-ports
21 * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
31 #define M4U_PORT_L0_OVL_2L_RDMA1_HDR MTK_M4U_DOM_ID(0, 3)
37 #define M4U_PORT_L0_OVL_2L_RDMA0_SYSRAM MTK_M4U_DOM_ID(0, 9)
48 #define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_DOM_ID(1, 3)
54 #define M4U_PORT_L1_OVL_2L_RDMA1_SYSRAM MTK_M4U_DOM_ID(1, 9)
65 #define M4U_PORT_L2_MDP_WROT2 MTK_M4U_DOM_ID(2, 3)
75 #define M4U_PORT_L4_VDEC_PRED_RD_EXT_MDP MTK_M4U_DOM_ID(4, 3)
[all …]
H A Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
22 * modules dma-address-region larbs-ports
27 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb13: port 9/10
32 /* LARB 0 -- MMSYS */
36 #define IOMMU_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 3)
38 /* LARB 1 -- MMSYS */
42 #define IOMMU_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 3)
45 /* LARB 2 -- MMSYS */
49 #define IOMMU_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3)
[all …]
H A Dmt8192-larb-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
18 * modules dma-address-region larbs-ports
21 * cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20
22 * CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10
32 #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 3)
40 #define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_ID(1, 3)
50 #define M4U_PORT_L2_MDP_WROT1 MTK_M4U_ID(2, 3)
59 #define M4U_PORT_L4_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3)
65 #define M4U_PORT_L4_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9)
[all …]
/linux/drivers/staging/media/ipu3/
H A Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
24 .even = { { 0, 3, 122, 7, 3, 0, 0 },
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
31 { 0, -12, 113, 7, 32, -5, 0 },
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8196.c1 // SPDX-License-Identifier: GPL-2.0
10 #include "pinctrl-mtk-mt8196.h"
11 #include "pinctrl-paris.h"
41 PIN_FIELD_BASE(3, 3, 11, 0x00a0, 0x10, 1, 1),
46 PIN_FIELD_BASE(8, 8, 11, 0x00a0, 0x10, 3, 1),
47 PIN_FIELD_BASE(9, 9, 9, 0x0120, 0x10, 13, 1),
48 PIN_FIELD_BASE(10, 10, 9, 0x0120, 0x10, 12, 1),
50 PIN_FIELD_BASE(12, 12, 9, 0x0120, 0x10, 15, 1),
51 PIN_FIELD_BASE(13, 13, 6, 0x0120, 0x10, 3, 1),
52 PIN_FIELD_BASE(14, 14, 3, 0x00c0, 0x10, 0, 1),
[all …]
H A Dpinctrl-mt8189.c1 // SPDX-License-Identifier: GPL-2.0
8 #include "pinctrl-mtk-mt8189.h"
9 #include "pinctrl-paris.h"
37 PIN_FIELD_BASE(1, 1, 8, 0x00c0, 0x10, 3, 1),
39 PIN_FIELD_BASE(3, 3, 8, 0x00c0, 0x10, 5, 1),
45 PIN_FIELD_BASE(9, 9, 7, 0x00e0, 0x10, 9, 1),
50 PIN_FIELD_BASE(14, 14, 3, 0x00f0, 0x10, 0, 1),
51 PIN_FIELD_BASE(15, 15, 3, 0x00f0, 0x10, 1, 1),
57 PIN_FIELD_BASE(21, 21, 7, 0x00e0, 0x10, 3, 1),
58 PIN_FIELD_BASE(22, 22, 9, 0x00f0, 0x10, 0, 1),
[all …]
/linux/arch/arm64/tools/
H A Dsysreg1 # SPDX-License-Identifier: GPL-2.0-only
52 # NI - Not implemented
53 # IMP - Implemented
99 Sysreg OSDTRTX_EL1 2 0 0 3 2
107 Res0 3:0
125 Sysreg SPMACCESSR_EL1 2 0 9 13 3
261 UnsignedEnum 9:8 P4
276 UnsignedEnum 3:2 P1
288 Sysreg SPMACCESSR_EL12 2 5 9 13 3
292 Sysreg SPMIIDR_EL1 2 0 9 13 4
[all …]
/linux/arch/arm/mach-omap1/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
7 * Copyright (C) 2003 - 2008 Nokia Corporation
15 #include <linux/soc/ti/omap1-io.h>
30 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
31 MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
34 MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
35 MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
36 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
37 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
[all …]
/linux/drivers/clk/rockchip/
H A Drst-rk3576.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
26 RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
41 RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3),
47 RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9),
65 RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0),
66 RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2),
67 RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3),
68 RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4),
69 RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5),
[all …]
/linux/arch/csky/lib/
H A Dusercopy.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
15 " mov %3, %1 \n" in raw_copy_from_user()
16 " or %3, %2 \n" in raw_copy_from_user()
17 " andi %3, 3 \n" in raw_copy_from_user()
18 " cmpnei %3, 0 \n" in raw_copy_from_user()
22 " bt 3f \n" in raw_copy_from_user()
23 "2: ldw %3, (%2, 0) \n" in raw_copy_from_user()
25 " stw %3, (%1, 0) \n" in raw_copy_from_user()
27 "11: ldw %3, (%2, 8) \n" in raw_copy_from_user()
[all …]
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A Dpipeline.json4 "Counter": "0,1,2,3,4,5,6,7",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
18 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
25 "Counter": "0,1,2,3,4,5,6,7",
34 "Counter": "0,1,2,3,4,5,6,7",
43 "Counter": "0,1,2,3,4,5,6,7",
53 "Counter": "0,1,2,3,4,5,6,7,8,9",
64 "Counter": "0,1,2,3,4,5,6,7",
73 "Counter": "0,1,2,3,4,5,6,7",
82 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32mp257.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 #include "pinctrl-stm32.h"
19 STM32_FUNCTION(3, "SPI5_RDY"),
25 STM32_FUNCTION(9, "TIM5_CH2"),
36 STM32_FUNCTION(3, "SPI6_MISO"),
41 STM32_FUNCTION(9, "I2C4_SDA"),
54 STM32_FUNCTION(3, "SPI7_MISO"),
57 STM32_FUNCTION(9, "I3C1_SDA"),
66 PINCTRL_PIN(3, "PA3"),
[all …]

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