Lines Matching +full:3 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
73 {3, 8},
87 {3, 16},
95 {3, 16},
122 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
123 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
124 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
126 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
130 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
190 BUS_MSTOP(5, BIT(9))),
192 BUS_MSTOP(3, BIT(2))),
194 BUS_MSTOP(3, BIT(3))),
195 DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3,
201 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
202 BUS_MSTOP(3, BIT(5))),
203 DEF_MOD("gpt_0_pclk_sfr", CLK_PLLCLN_DIV8, 3, 1, 1, 17,
205 DEF_MOD("gpt_1_pclk_sfr", CLK_PLLCLN_DIV8, 3, 2, 1, 18,
220 BUS_MSTOP(3, BIT(14))),
221 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
223 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
225 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
227 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
228 BUS_MSTOP(3, BIT(13))),
229 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
231 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
233 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
234 BUS_MSTOP(1, BIT(3))),
235 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
237 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
239 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
241 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
243 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
245 DEF_MOD("canfd_0_pclk", CLK_PLLCLN_DIV16, 9, 12, 4, 28,
247 DEF_MOD("canfd_0_clk_ram", CLK_PLLCLN_DIV8, 9, 13, 4, 29,
249 DEF_MOD("canfd_0_clkc", CLK_PLLCLN_DIV20, 9, 14, 4, 30,
251 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
257 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
266 BUS_MSTOP(8, BIT(3))),
268 BUS_MSTOP(8, BIT(3))),
269 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
270 BUS_MSTOP(8, BIT(3))),
272 BUS_MSTOP(8, BIT(3))),
287 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
307 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
310 BUS_MSTOP(9, BIT(4))),
311 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
312 BUS_MSTOP(9, BIT(4))),
314 BUS_MSTOP(9, BIT(4))),
316 BUS_MSTOP(3, BIT(4))),
318 BUS_MSTOP(3, BIT(4))),
320 BUS_MSTOP(3, BIT(4))),
326 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
327 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */
328 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */
329 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */
330 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */
331 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */
332 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */
333 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
334 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
335 DEF_RST(5, 9, 2, 10), /* GPT_0_RST_P_REG */
339 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
340 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
341 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
342 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
343 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
344 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
345 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
346 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
347 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
348 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
349 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
350 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
351 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
352 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
356 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
360 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */
370 DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */