Lines Matching +full:3 +full:- +full:9
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
68 {3, 8},
76 {3, 16},
84 {3, 16},
111 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
112 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3),
113 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
115 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
119 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
172 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
173 BUS_MSTOP(3, BIT(5))),
174 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3,
186 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9,
191 BUS_MSTOP(3, BIT(10))),
193 BUS_MSTOP(3, BIT(10))),
207 BUS_MSTOP(3, BIT(14))),
208 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16,
210 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17,
212 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18,
214 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
215 BUS_MSTOP(3, BIT(13))),
216 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20,
218 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21,
220 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22,
221 BUS_MSTOP(1, BIT(3))),
222 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23,
224 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24,
226 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25,
228 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26,
230 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
232 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31,
238 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3,
247 BUS_MSTOP(8, BIT(3))),
249 BUS_MSTOP(8, BIT(3))),
250 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9,
251 BUS_MSTOP(8, BIT(3))),
253 BUS_MSTOP(8, BIT(3))),
262 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
265 BUS_MSTOP(7, BIT(9))),
270 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
290 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
293 BUS_MSTOP(3, BIT(4))),
295 BUS_MSTOP(3, BIT(4))),
297 BUS_MSTOP(3, BIT(4))),
301 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
302 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
303 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
306 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */
307 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */
308 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */
309 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */
310 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */
311 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */
312 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */
313 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
314 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
315 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
316 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
317 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */
318 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */
319 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
320 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
321 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
322 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
323 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */
324 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */
325 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */
326 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */
328 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */
332 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */