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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
31 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
40 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
42 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
43 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
44 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
[all …]
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
41 #define MT_TX_FREE_PAIR BIT(31)
46 #define MT_TXD0_PKT_FMT GENMASK(24, 23)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
52 #define MT_TXD1_OWN_MAC GENMASK(29, 24)
53 #define MT_TXD1_AMSDU BIT(23)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
62 #define MT_TXD2_FIX_RATE BIT(31)
[all …]
H A Dmt76x02_regs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
43 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
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/freebsd/contrib/file/magic/Magdir/
H A Dmach2 #------------------------------------------------------------
8 #------------------------------------------------------------
9 # if set, it's for the 64-bit version of the architecture
10 # yes, this is separate from the low-order magic number bit
11 # it's also separate from the "64-bit libraries" bit in the
14 # Reference: https://opensource.apple.com/source/cctools/cctools-949.0.1/
15 # include/mach-o/loader.h
17 0 name mach-o-cpu
20 # 32-bit ABIs.
153 # 64-bit ABIs.
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
23 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
[all …]
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
35 #define MT_HW_INFO_BASE ((dev)->reg_map[MT_HW_BASE])
40 #define MT_TOP_3NSS BIT(24)
45 #define MT_TOP_MISC2 ((dev)->reg_map[MT_TOP_CFG_BASE] + 0x134)
49 #define MT_TOP_MISC2_FW_PWR_ON BIT(1)
59 #define MT_MCU_PCIE_REMAP_2 ((dev)->reg_map[MT_PCIE_REMAP_2])
62 #define MT_PCIE_REMAP_BASE_2 ((dev)->reg_map[MT_PCIE_REMAP_BASE2])
69 #define MT_HIF(ofs) ((dev)->reg_map[MT_HIF_BASE] + (ofs))
71 #define MT_HIF_LOGIC_RST_N BIT(4)
74 #define MT_PDMA_AXI_SLPPROT_ENABLE BIT(0)
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/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
27 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
40 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
48 if (rtwdev->chi in rtw89_get_data_mcs()
[all...]
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(
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H A Dfw.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
26 #define RTW89_C2HREG_HDR_ACK BIT(7)
38 #define RTW89_C2HREG_PHYCAP_W0_ACK BIT(7)
42 #define RTW89_C2HREG_PHYCAP_W0_BW GENMASK(31, 24)
46 #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC GENMASK(31, 24)
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/freebsd/lib/libc/arm/string/
H A Dmemcpy.S48 /* Word-align the destination buffer */
64 ands ip, r1, #0x03 /* Is src also word-aligned? */
67 /* Quad-align the destination buffer */
70 stmfd sp!, {r4-r9} /* Free up some registers */
80 ldr r4, [r1], #0x04 /* LD:00-03 */
81 ldr r5, [r1], #0x04 /* LD:04-07 */
83 ldr r6, [r1], #0x04 /* LD:08-0b */
84 ldr r7, [r1], #0x04 /* LD:0c-0f */
85 ldr r8, [r1], #0x04 /* LD:10-13 */
86 ldr r9, [r1], #0x04 /* LD:14-17 */
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
[all …]
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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/freebsd/lib/libvgl/
H A Dtext.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991-1997 Søren Schmidt
46 if (VGLTextFont->BitmapArray != VGLFont) in VGLTextSetFontFile()
47 free (VGLTextFont->BitmapArray); in VGLTextSetFontFile()
55 VGLTextFont->Width = 8; in VGLTextSetFontFile()
56 VGLTextFont->Height = 8; in VGLTextSetFontFile()
57 VGLTextFont->BitmapArray = VGLFont; in VGLTextSetFontFile()
62 fread(&VGLTextFont->Width, 1 , 1, fd); in VGLTextSetFontFile()
63 fread(&VGLTextFont->Height, 1 , 1, fd); in VGLTextSetFontFile()
[all …]
/freebsd/sys/arm/arm/
H A Dsupport.S1 /*-
98 * r0 - dest address
99 * r1 - byte to write
100 * r2 - number of bytes to write
103 * r0 - dest address
120 orr r3, r3, r3, lsl #8 /* Extend value to 16-bits */
121 tst ip, #0x04 /* Quad-align for armv5e */
122 orr r3, r3, r3, lsl #16 /* Extend value to 32-bits */
123 subne r1, r1, #0x04 /* Quad-align if necessary */
181 /* Compensate for 64-bit alignment check */
[all …]
/freebsd/sys/dev/etherswitch/arswitch/
H A Darswitchreg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
34 * Register manipulation macros that expect bit field defines
42 #define BIT(_m) (1UL << (_m)) macro
43 #define BITM(_count) ((1UL << (_count)) - 1)
59 /* DIR-615 E4 U-Boot */
80 #define AR8X16_MODE_LED_OPEN_EN (1u << 24)
95 #define AR8X16_REG_SW_MAC_ADDR1_BYTE0 BITS(24, 8)
96 #define AR8X16_REG_SW_MAC_ADDR1_BYTE0_S 24
147 #define AR8216_ATU_ACTIVE BIT(3)
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/freebsd/sys/dev/cxgbe/cudbg/
H A Dcudbg_wtp.c1 /*-
258 struct adapter *padap = pdbg_init->adap; in read_sge_debug_data()
277 struct adapter *padap = pdbg_init->adap; in read_tp_mib_data()
293 struct adapter *padap = pdbg_init->adap; in t5_wtp_data()
325 wtp->sge_pcie_cmd_req.sop[0] = sge_dbg_reg->debug_PC_Req_SOP0_cnt; in t5_wtp_data()
326 wtp->sge_pcie_cmd_req.sop[1] = sge_dbg_reg->debug_PC_Req_SOP1_cnt; in t5_wtp_data()
328 wtp->sge_pcie_cmd_req.eop[0] = sge_dbg_reg->debug_PC_Req_EOP0_cnt; in t5_wtp_data()
329 wtp->sge_pcie_cmd_req.eop[1] = sge_dbg_reg->debug_PC_Req_EOP1_cnt; in t5_wtp_data()
334 wtp->pcie_core_cmd_req.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/ in t5_wtp_data()
335 wtp->pcie_core_cmd_req.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/ in t5_wtp_data()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRFixupKinds.h1 //===-- AVRFixupKinds.h - AVR Specific Fixup Entries -------
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
27 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
31 // e.g. s3 field may encode the signed integers values -1 .. 6
34 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
64 class ExtMode<bit mode, string instSfx, string asmSfx> {
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/freebsd/sys/dev/ocs_fc/
H A Docs_fcp.h1 /*-
72 * Generic Services FC Type Bit mask macros:
111 uint32_t :24,
128 * @brief FC header in big-endian order
133 d_id:24;
135 s_id:24;
137 f_ctl:24;
147 * @brief FC header in little-endian order
151 uint32_t d_id:24,
154 uint32_t s_id:24,
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/freebsd/sys/dev/etherswitch/ar40xx/
H A Dar40xx_reg.h20 * Register manipulation macros that expect bit field defines
27 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
28 #define BIT(_n) (1UL << (_n)) macro
51 #define AR40XX_PSGMII_ATHR_CSCO_MODE_25M BIT(0)
101 #define AR40XX_MODULE_EN_MIB BIT(0)
104 #define AR40XX_MIB_BUSY BIT(17)
105 #define AR40XX_MIB_CPU_KEEP BIT(20)
106 #define AR40XX_MIB_FUNC BITS(24, 3)
107 #define AR40XX_MIB_FUNC_S 24
112 #define AR40XX_ESS_SERVICE_TAG_STAG BIT(17)
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/freebsd/sys/contrib/dev/rtw88/
H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
9 #define BIT_FEN_EN_25_1 BIT(13)
10 #define BIT_FEN_ELDR BIT(12)
11 #define BIT_FEN_CPUEN BIT(2)
12 #define BIT_FEN_BB_GLB_RST BIT(
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/freebsd/contrib/netbsd-tests/include/
H A Dd_bitstring_27.out29 24 3 1 3
34 be: 0 -1 000000000000000000000000000
35 is: 0 -1 000000000000000000000000000
71 24 0
76 be: 0 -1 000000000000000000000000000
77 is: 0 -1 000000000000000000000000000
84 be: 0 -1 000000000000000000000000000
85 is: 0 -1 000000000000000000000000000
88 be: 0 -1 000000000000000000000000000
89 is: 0 -1 000000000000000000000000000
[all …]
H A Dd_bitstring_32.out29 24 3 1 3
39 be: 0 -1 00000000000000000000000000000000
40 is: 0 -1 00000000000000000000000000000000
76 24 0
86 be: 0 -1 00000000000000000000000000000000
87 is: 0 -1 00000000000000000000000000000000
94 be: 0 -1 00000000000000000000000000000000
95 is: 0 -1 00000000000000000000000000000000
98 be: 0 -1 00000000000000000000000000000000
99 is: 0 -1 00000000000000000000000000000000
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td1 //===-- RISCVInstrFormatsV.td - RISC-V V Instruction Formats -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file describes the RISC-V V extension instruction formats.
11 //===----------------------------------------------------------------------===//
65 let Inst{29-20} = vtypei{9-0};
66 let Inst{19-15} = uimm;
67 let Inst{14-12} = OPCFG.Value;
68 let Inst{11-7} = rd;
69 let Inst{6-0} = OPC_OP_V.Value;
[all …]
/freebsd/sys/dev/sound/pcm/
H A Dpcm.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2006-2009 Ariff Abdullah <ariff@FreeBSD.org>
6 * Copyright (c) 2024-2025 The FreeBSD Foundation
45 * Automatically turn on 64bit arithmetic on suitable archs
46 * (amd64 64bit, etc..) for wider 32bit samples / integer processing.
76 /* 32bit fixed point shift */
80 #define PCM_S8_MIN -0x80
82 #define PCM_S16_MIN -0x8000
84 #define PCM_S24_MIN -0x800000
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