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/linux/arch/powerpc/crypto/
H A Dcurve25519-ppc64le_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9 # [1] https://github.com/dot-asm/cryptogams/
11 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org>
58 # - Added x25519_fe51_sqr_times, x25519_fe51_frombytes, x25519_fe51_tobytes
61 # Copyright 2024- IBM Corp.
63 # X25519 lower-level primitives for PPC64.
73 stdu 1,-144(1)
74 std 21,56(1)
77 std 24,80(1)
90 ld 10,24(4)
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-samsung-dcphy.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Guochun Huang <hero.huang@rock-chips.com>
8 #include <dt-bindings/phy/phy.h>
73 * The selection between the 400-based or 200-based values for REG_400M
337 {6500, 32, 117, 31, 28, 30, 56, 27, 24, 44, 37},
338 {6490, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
339 {6480, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
340 {6470, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
341 {6460, 32, 116, 31, 28, 30, 56, 27, 24, 44, 37},
342 {6450, 32, 115, 31, 28, 30, 56, 27, 24, 44, 37},
[all …]
/linux/arch/alpha/include/asm/
H A Dxor.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/asm-alpha/xor.h
5 * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
62 ldq $6,24($17) \n\
63 ldq $7,24($18) \n\
67 ldq $21,40($17) \n\
71 ldq $24,48($18) \n\
85 stq $6,24($17) \n\
86 xor $21,$22,$21 \n\
88 xor $23,$24,$23 \n\
[all …]
/linux/lib/crypto/powerpc/
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
78 stdu 1,-752(1)
87 SAVE_GPR 21, 168, 1
90 SAVE_GPR 24, 192, 1
101 SAVE_VRS 21, 16, 9
104 SAVE_VRS 24, 64, 9
120 SAVE_VSX 21, 304, 9
[all …]
H A Dpoly1305-p10le_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
10 # Poly1305 - this version mainly using vector/VSX/Scalar
11 # - 26 bits limbs
12 # - Handle multiple 64 byte blcok.
17 # p = 2^130 - 5
25 # 07/22/21 - this revison based on the above sum of products. Setup r^4, r^3, r^2, r and s3, s2, …
56 #include <asm/asm-offsets.h>
57 #include <asm/asm-compat.h>
95 stdu 1,-752(1)
[all …]
/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
[all …]
/linux/include/dt-bindings/memory/
H A Dmt8195-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
20 * modules dma-address-region larbs-ports
22 * vcodec 4G ~ 8G larb19/20/21/22/23/24
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
143 #define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21)
257 #define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21)
260 #define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24)
286 #define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(20, 21)
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt6735-apmixedsys.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "clk-mtk.h"
10 #include "clk-pll.h"
12 #include <dt-bindings/clock/mediatek,mt6735-apmixedsys.h>
45 #define CON0_RST_BAR BIT(24)
69 …l", ARMPLL_CON0, ARMPLL_PWR_CON0, 0x00000001, 0, ARMPLL_CON1, 24, 0, 0, 0, ARMPLL_CON1, 21, PLL_AO…
70 …N0, MAINPLL_PWR_CON0, 0xf0000101, CON0_RST_BAR, MAINPLL_CON1, 24, 0, 0, 0, MAINPLL_CON1, 21, HAVE_…
71 …N0, UNIVPLL_PWR_CON0, 0xfc000001, CON0_RST_BAR, UNIVPLL_CON1, 24, 0, 0, 0, UNIVPLL_CON1, 21, HAVE_…
72 …L, "mmpll", MMPLL_CON0, MMPLL_PWR_CON0, 0x00000001, 0, MMPLL_CON1, 24, 0, 0, 0, MMPLL_CON1, 21, 0),
[all …]
H A Dclk-mt8167-apmixedsys.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
13 #include "clk-pll.h"
14 #include "clk-mtk.h"
60 21, 0x0104, 24, 0, 0x0104, 0),
62 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
64 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
66 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
72 21, 0x01C4, 24, 0, 0x01C4, 0),
74 21, 0x01E4, 24, 0, 0x01E4, 0),
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8365.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-mtk-common.h"
15 #include "pinctrl-mtk-mt8365.h"
48 MTK_PIN_DRV_GRP(20, 0x710, 24, 2),
49 MTK_PIN_DRV_GRP(21, 0x710, 24, 2),
52 MTK_PIN_DRV_GRP(24, 0x720, 0, 2),
77 MTK_PIN_DRV_GRP(49, 0x720, 24, 2),
78 MTK_PIN_DRV_GRP(50, 0x720, 24, 2),
79 MTK_PIN_DRV_GRP(51, 0x720, 24, 2),
[all …]
/linux/arch/arm/mach-omap1/
H A Dmux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-omap1/mux.c
7 * Copyright (C) 2003 - 2008 Nokia Corporation
15 #include <linux/soc/ti/omap1-io.h>
30 MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
36 MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
37 MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
42 MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
66 MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
79 MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
[all …]
/linux/arch/arm/kernel/
H A Dphys2virt.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1994-2002 Russell King
22 * __fixup_pv_table - patch the stub instructions with the delta between
36 subs r3, r8, #PAGE_OFFSET @ PHYS_OFFSET - PAGE_OFFSET
41 mov r0, r3, lsr #21 @ constant for add/sub instructions
42 teq r3, r0, lsl #21 @ must be 2 MiB aligned
61 @ The Thumb-2 versions of the patchable sequences are
63 @ phys-to-virt: movw <reg>, #offset<31:21>
64 @ lsl <reg>, #21
67 @ virt-to-phys (non-LPAE): movw <reg>, #offset<31:21>
[all …]
/linux/drivers/net/ethernet/amazon/ena/
H A Dena_eth_io_defs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
12 ENA_ETH_IO_L3_PROTO_FCOE = 21,
24 /* 15:0 : length - Buffer length in bytes, must
26 * to update like End-to-End CRC, Authentication GMAC
29 * the 4-byte added in the end for 802.3 Ethernet FCS
30 * 21:16 : req_id_hi - Request ID[15:10]
31 * 22 : reserved22 - MBZ
32 * 23 : meta_desc - MBZ
33 * 24 : phase
[all …]
/linux/arch/alpha/kernel/
H A Dentry.S1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Kernel entry-points.
8 #include <asm/asm-offsets.h>
28 .cfi_rel_offset $16, 24
35 .size \func, . - \func
39 * This defines the normal kernel pt-regs layout.
41 * regs 9-15 preserved by C code
42 * regs 16-18 saved by PAL-code
43 * regs 29-30 saved and set up by PAL-code
44 * JRP - Save regs 16-18 in a special area of the stack, so that
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
23 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
29 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
51 #define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21)
81 #define MT_RXV1_VHTA2_B8_B3 GENMASK(29, 24)
83 #define MT_RXV1_HT_NO_SOUND BIT(21)
98 #define MT_RXV2_GROUP_ID GENMASK(26, 21)
101 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
[all …]
/linux/drivers/mtd/maps/
H A Dphysmap-gemini.c1 // SPDX-License-Identifier: GPL-2.0
3 * Cortina Systems Gemini OF physmap add-on
18 #include "physmap-gemini.h"
21 * The Flash-relevant parts of the global status register
25 #define FLASH_TYPE_MASK (0x3 << 24)
26 #define FLASH_TYPE_NAND_2K (0x3 << 24)
27 #define FLASH_TYPE_NAND_512 (0x2 << 24)
28 #define FLASH_TYPE_PARALLEL (0x1 << 24)
29 #define FLASH_TYPE_SERIAL (0x0 << 24)
35 #define FLASH_SIZE_MASK (0x3 << 21)
[all …]
/linux/drivers/gpu/drm/mxsfb/
H A Dlcdif_regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
60 #define CTRL1_RECOVER_ON_UNDERFLOW BIT(24)
61 #define CTRL1_FIFO_CLEAR BIT(21)
68 #define CTRL2_SET_OUTSTANDING_REQS_2 (0x1 << 21)
69 #define CTRL2_SET_OUTSTANDING_REQS_4 (0x2 << 21)
70 #define CTRL2_SET_OUTSTANDING_REQS_8 (0x3 << 21)
71 #define CTRL2_SET_OUTSTANDING_REQS_16 (0x4 << 21)
72 #define CTRL2_SET_OUTSTANDING_REQS_MASK (0x7 << 21)
83 #define VDCTRL0_ENABLE_ACT_HIGH BIT(24)
84 #define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21)
[all …]
/linux/arch/arm64/tools/
H A Dsysreg1 # SPDX-License-Identifier: GPL-2.0-only
52 # NI - Not implemented
53 # IMP - Implemented
83 Res0 25:24
85 Field 21 TDA
221 UnsignedEnum 25:24 P12
231 UnsignedEnum 21:20 P10
302 Field 31:21 ARCHITECT
315 Field 24 MT
325 Field 24 HDBG
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
69 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24)
70 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24)
89 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24)
100 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24)
104 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24)
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gpu_commands.h1 /* SPDX-License-Identifier: MIT*/
3 * Copyright © 2003-2018 Intel Corporation
30 #define INSTR_26_TO_24_SHIFT 24
68 #define MI_OVERLAY_CONTINUE (0x0<<21)
69 #define MI_OVERLAY_ON (0x1<<21)
70 #define MI_OVERLAY_OFF (0x2<<21)
94 #define MI_SEMAPHORE_UPDATE (1<<21)
137 #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
150 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
152 * - One can actually load arbitrary many arbitrary registers: Simply issue x
[all …]
/linux/include/linux/netfilter/
H A Dnf_conntrack_h323_types.h1 /* SPDX-License-Identifier: GPL-2.0-only */
148 eH2250LogicalChannelParameters_destination = (1 << 24),
153 (1 << 21),
260 eSetup_UUIE_sourceCallSignalAddress = (1 << 24),
263 eSetup_UUIE_h245SecurityCapability = (1 << 21),
306 eCallProceeding_UUIE_maintainConnection = (1 << 24),
328 eConnect_UUIE_maintainConnection = (1 << 24),
331 eConnect_UUIE_presentationIndicator = (1 << 21),
356 eAlerting_UUIE_maintainConnection = (1 << 24),
359 eAlerting_UUIE_screeningIndicator = (1 << 21),
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
25 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21)
52 #define MISC_CTRL_INT_OUTPUT_INVERT BIT(24)
86 #define GPIO_MUX_24 BIT(24)
89 #define GPIO_MUX_21 BIT(21)
114 #define LOCALMEM_ARBITRATION_VGA_MASK (0x7 << 24)
115 #define LOCALMEM_ARBITRATION_VGA_OFF (0x0 << 24)
116 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_1 (0x1 << 24)
117 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_2 (0x2 << 24)
[all …]
/linux/drivers/net/ipa/reg/
H A Dipa_reg-v5.5.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
16 [PROD_LOWEST] = GENMASK(31, 24),
39 /* Bits 17-18 reserved */
42 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
44 /* Bits 28-29 reserved */
73 [CLKON_FNR] = BIT(21),
76 [RAM_SLAVEWAY] = BIT(24),
95 /* Bits 29-31 reserved */
110 /* Bits 8-31 reserved */
[all …]
H A Dipa_reg-v5.0.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023-2024 Linaro Ltd. */
16 [PROD_LOWEST] = GENMASK(31, 24),
43 [IF_OUT_OF_BUF_STOP_RESET_MASK_EN] = BIT(21),
45 /* Bits 28-29 reserved */
74 [CLKON_FNR] = BIT(21),
77 [RAM_SLAVEWAY] = BIT(24),
96 /* Bits 29-31 reserved */
111 /* Bits 8-31 reserved */
119 /* Bits 8-15 reserved */
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
28 #define MT_RXD1_NORMAL_PAYLOAD_FORMAT GENMASK(25, 24)
31 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
51 #define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21)
74 #define MT_RXV1_HT_NO_SOUND BIT(21)
86 #define MT_RXV2_VHTA1_B16_B6 GENMASK(31, 21)
116 #define MT_RXV6_RX_VALID BIT(24)
134 #define MT_TXD0_UDP_TCP_SUM BIT(24)
[all …]

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