Lines Matching +full:24 +full:- +full:21
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
13 #include "clk-pll.h"
14 #include "clk-mtk.h"
60 21, 0x0104, 24, 0, 0x0104, 0),
62 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
64 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
66 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
72 21, 0x01C4, 24, 0, 0x01C4, 0),
74 21, 0x01E4, 24, 0, 0x01E4, 0),
89 0x1c4, 24, 3, CLK_DIVIDER_POWER_OF_TWO),
96 struct device_node *node = pdev->dev.of_node; in clk_mt8167_apmixed_probe()
97 struct device *dev = &pdev->dev; in clk_mt8167_apmixed_probe()
106 return -ENOMEM; in clk_mt8167_apmixed_probe()
132 { .compatible = "mediatek,mt8167-apmixedsys" },
140 .name = "clk-mt8167-apmixed",