Lines Matching +full:24 +full:- +full:21
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
60 #define CTRL1_RECOVER_ON_UNDERFLOW BIT(24)
61 #define CTRL1_FIFO_CLEAR BIT(21)
68 #define CTRL2_SET_OUTSTANDING_REQS_2 (0x1 << 21)
69 #define CTRL2_SET_OUTSTANDING_REQS_4 (0x2 << 21)
70 #define CTRL2_SET_OUTSTANDING_REQS_8 (0x3 << 21)
71 #define CTRL2_SET_OUTSTANDING_REQS_16 (0x4 << 21)
72 #define CTRL2_SET_OUTSTANDING_REQS_MASK (0x7 << 21)
83 #define VDCTRL0_ENABLE_ACT_HIGH BIT(24)
84 #define VDCTRL0_VSYNC_PERIOD_UNIT BIT(21)
145 #define DISP_PARA_DISP_MODE_MASK GENMASK(25, 24)
170 #define INT_STATUS_D0_FIFO_EMPTY BIT(24)
177 #define INT_ENABLE_D0_FIFO_EMPTY_EN BIT(24)
205 #define CTRLDESCL0_5_BPP_16_RGB565 (0x4 << 24)
206 #define CTRLDESCL0_5_BPP_16_ARGB1555 (0x5 << 24)
207 #define CTRLDESCL0_5_BPP_16_ARGB4444 (0x6 << 24)
208 #define CTRLDESCL0_5_BPP_YCbCr422 (0x7 << 24)
209 #define CTRLDESCL0_5_BPP_24_RGB888 (0x8 << 24)
210 #define CTRLDESCL0_5_BPP_32_ARGB8888 (0x9 << 24)
211 #define CTRLDESCL0_5_BPP_32_ABGR8888 (0xa << 24)
212 #define CTRLDESCL0_5_BPP_MASK GENMASK(27, 24)
247 #define CSC0_COEF4_D1_MASK GENMASK(24, 16)
252 #define CSC0_COEF5_D3_MASK GENMASK(24, 16)
256 #define PANIC0_THRES_LOW_MASK GENMASK(24, 16)