Lines Matching +full:24 +full:- +full:21
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 1994-2002 Russell King
22 * __fixup_pv_table - patch the stub instructions with the delta between
36 subs r3, r8, #PAGE_OFFSET @ PHYS_OFFSET - PAGE_OFFSET
41 mov r0, r3, lsr #21 @ constant for add/sub instructions
42 teq r3, r0, lsl #21 @ must be 2 MiB aligned
61 @ The Thumb-2 versions of the patchable sequences are
63 @ phys-to-virt: movw <reg>, #offset<31:21>
64 @ lsl <reg>, #21
67 @ virt-to-phys (non-LPAE): movw <reg>, #offset<31:21>
68 @ lsl <reg>, #21
71 @ virt-to-phys (LPAE): movw <reg>, #offset<31:21>
72 @ lsl <reg>, #21
77 @ In the non-LPAE case, all patchable instructions are MOVW
79 @ second halfword of the opcode (the 16-bit immediate is encoded
83 @ +-----------+---+-------------+------++---+------+----+------+
85 @ +-----------+---+-------------+------++---+------+----+------+
98 @ +-----------+---+---------------------++---+------+----+------+
101 @ +-----------+---+---------------------++---+------+----+------+
103 moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
105 ubfx r6, r6, #21, #8 @ put bits 28:21 into the MOVW imm8 field
115 bic ip, #0x20 @ clear bit 5 (MVN -> MOV)
116 orr ip, ip, r0, lsr #16 @ MOV -> MVN if offset < 0
125 orreq ip, r0 @ Z flag set -> MOV/MVN -> patch in high bits
126 orrne ip, r6 @ Z flag clear -> MOVW -> patch in low bits
144 @ phys-to-virt: sub <VA>, <PA>, #offset<31:24>, lsl #24
147 @ virt-to-phys (non-LPAE): add <PA>, <VA>, #offset<31:24>, lsl #24
150 @ virt-to-phys (LPAE): movw <reg>, #offset<31:20>
155 @ In the non-LPAE case, all patchable instructions are ADD or SUB
162 @ +------+-----------------+------+------+-------+
167 @ +------+-----------------+------+------+-------+
175 @ bit 24.
178 @ +------+-----------------+------+------+-------+
180 @ +------+-----------------+------+------+-------+
183 mov r3, r6, lsr #16 @ put offset bits 31-16 into r3
184 mov r6, r6, lsr #24 @ put offset bits 31-24 into r6
185 and r3, r3, #0xf0 @ only keep offset bits 23-20 in r3
189 tst ip, #PV_BIT24 @ ADD/SUB have bit 24 clear
195 orreq ip, ip, r6, lsl #4 @ MOVW -> mask in offset bits 31-24
196 orreq ip, ip, r3, lsr #4 @ MOVW -> mask in offset bits 23-20
197 orrne ip, ip, r0 @ MOV -> mask in offset bits 7-0 (or bit 22)
204 orreq ip, ip, r6 ARM_BE8(, lsl #24) @ mask in offset bits 31-24
205 orrne ip, ip, r3 ARM_BE8(, lsl #24) @ mask in offset bits 23-20
219 stmfd sp!, {r4 - r7, lr}
223 ldmfd sp!, {r4 - r7, pc}
232 .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset
238 .size __pv_offset, . -__pv_offset