1af1a8899SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2024b246eSLinus Torvalds /* 3024b246eSLinus Torvalds * include/asm-alpha/xor.h 4024b246eSLinus Torvalds * 5024b246eSLinus Torvalds * Optimized RAID-5 checksumming functions for alpha EV5 and EV6 6024b246eSLinus Torvalds */ 7024b246eSLinus Torvalds 8*297565aaSArd Biesheuvel extern void 9*297565aaSArd Biesheuvel xor_alpha_2(unsigned long bytes, unsigned long * __restrict p1, 10*297565aaSArd Biesheuvel const unsigned long * __restrict p2); 11*297565aaSArd Biesheuvel extern void 12*297565aaSArd Biesheuvel xor_alpha_3(unsigned long bytes, unsigned long * __restrict p1, 13*297565aaSArd Biesheuvel const unsigned long * __restrict p2, 14*297565aaSArd Biesheuvel const unsigned long * __restrict p3); 15*297565aaSArd Biesheuvel extern void 16*297565aaSArd Biesheuvel xor_alpha_4(unsigned long bytes, unsigned long * __restrict p1, 17*297565aaSArd Biesheuvel const unsigned long * __restrict p2, 18*297565aaSArd Biesheuvel const unsigned long * __restrict p3, 19*297565aaSArd Biesheuvel const unsigned long * __restrict p4); 20*297565aaSArd Biesheuvel extern void 21*297565aaSArd Biesheuvel xor_alpha_5(unsigned long bytes, unsigned long * __restrict p1, 22*297565aaSArd Biesheuvel const unsigned long * __restrict p2, 23*297565aaSArd Biesheuvel const unsigned long * __restrict p3, 24*297565aaSArd Biesheuvel const unsigned long * __restrict p4, 25*297565aaSArd Biesheuvel const unsigned long * __restrict p5); 26024b246eSLinus Torvalds 27*297565aaSArd Biesheuvel extern void 28*297565aaSArd Biesheuvel xor_alpha_prefetch_2(unsigned long bytes, unsigned long * __restrict p1, 29*297565aaSArd Biesheuvel const unsigned long * __restrict p2); 30*297565aaSArd Biesheuvel extern void 31*297565aaSArd Biesheuvel xor_alpha_prefetch_3(unsigned long bytes, unsigned long * __restrict p1, 32*297565aaSArd Biesheuvel const unsigned long * __restrict p2, 33*297565aaSArd Biesheuvel const unsigned long * __restrict p3); 34*297565aaSArd Biesheuvel extern void 35*297565aaSArd Biesheuvel xor_alpha_prefetch_4(unsigned long bytes, unsigned long * __restrict p1, 36*297565aaSArd Biesheuvel const unsigned long * __restrict p2, 37*297565aaSArd Biesheuvel const unsigned long * __restrict p3, 38*297565aaSArd Biesheuvel const unsigned long * __restrict p4); 39*297565aaSArd Biesheuvel extern void 40*297565aaSArd Biesheuvel xor_alpha_prefetch_5(unsigned long bytes, unsigned long * __restrict p1, 41*297565aaSArd Biesheuvel const unsigned long * __restrict p2, 42*297565aaSArd Biesheuvel const unsigned long * __restrict p3, 43*297565aaSArd Biesheuvel const unsigned long * __restrict p4, 44*297565aaSArd Biesheuvel const unsigned long * __restrict p5); 45024b246eSLinus Torvalds 46024b246eSLinus Torvalds asm(" \n\ 47024b246eSLinus Torvalds .text \n\ 48024b246eSLinus Torvalds .align 3 \n\ 49024b246eSLinus Torvalds .ent xor_alpha_2 \n\ 50024b246eSLinus Torvalds xor_alpha_2: \n\ 51024b246eSLinus Torvalds .prologue 0 \n\ 52024b246eSLinus Torvalds srl $16, 6, $16 \n\ 53024b246eSLinus Torvalds .align 4 \n\ 54024b246eSLinus Torvalds 2: \n\ 55024b246eSLinus Torvalds ldq $0,0($17) \n\ 56024b246eSLinus Torvalds ldq $1,0($18) \n\ 57024b246eSLinus Torvalds ldq $2,8($17) \n\ 58024b246eSLinus Torvalds ldq $3,8($18) \n\ 59024b246eSLinus Torvalds \n\ 60024b246eSLinus Torvalds ldq $4,16($17) \n\ 61024b246eSLinus Torvalds ldq $5,16($18) \n\ 62024b246eSLinus Torvalds ldq $6,24($17) \n\ 63024b246eSLinus Torvalds ldq $7,24($18) \n\ 64024b246eSLinus Torvalds \n\ 65024b246eSLinus Torvalds ldq $19,32($17) \n\ 66024b246eSLinus Torvalds ldq $20,32($18) \n\ 67024b246eSLinus Torvalds ldq $21,40($17) \n\ 68024b246eSLinus Torvalds ldq $22,40($18) \n\ 69024b246eSLinus Torvalds \n\ 70024b246eSLinus Torvalds ldq $23,48($17) \n\ 71024b246eSLinus Torvalds ldq $24,48($18) \n\ 72024b246eSLinus Torvalds ldq $25,56($17) \n\ 73024b246eSLinus Torvalds xor $0,$1,$0 # 7 cycles from $1 load \n\ 74024b246eSLinus Torvalds \n\ 75024b246eSLinus Torvalds ldq $27,56($18) \n\ 76024b246eSLinus Torvalds xor $2,$3,$2 \n\ 77024b246eSLinus Torvalds stq $0,0($17) \n\ 78024b246eSLinus Torvalds xor $4,$5,$4 \n\ 79024b246eSLinus Torvalds \n\ 80024b246eSLinus Torvalds stq $2,8($17) \n\ 81024b246eSLinus Torvalds xor $6,$7,$6 \n\ 82024b246eSLinus Torvalds stq $4,16($17) \n\ 83024b246eSLinus Torvalds xor $19,$20,$19 \n\ 84024b246eSLinus Torvalds \n\ 85024b246eSLinus Torvalds stq $6,24($17) \n\ 86024b246eSLinus Torvalds xor $21,$22,$21 \n\ 87024b246eSLinus Torvalds stq $19,32($17) \n\ 88024b246eSLinus Torvalds xor $23,$24,$23 \n\ 89024b246eSLinus Torvalds \n\ 90024b246eSLinus Torvalds stq $21,40($17) \n\ 91024b246eSLinus Torvalds xor $25,$27,$25 \n\ 92024b246eSLinus Torvalds stq $23,48($17) \n\ 93024b246eSLinus Torvalds subq $16,1,$16 \n\ 94024b246eSLinus Torvalds \n\ 95024b246eSLinus Torvalds stq $25,56($17) \n\ 96024b246eSLinus Torvalds addq $17,64,$17 \n\ 97024b246eSLinus Torvalds addq $18,64,$18 \n\ 98024b246eSLinus Torvalds bgt $16,2b \n\ 99024b246eSLinus Torvalds \n\ 100024b246eSLinus Torvalds ret \n\ 101024b246eSLinus Torvalds .end xor_alpha_2 \n\ 102024b246eSLinus Torvalds \n\ 103024b246eSLinus Torvalds .align 3 \n\ 104024b246eSLinus Torvalds .ent xor_alpha_3 \n\ 105024b246eSLinus Torvalds xor_alpha_3: \n\ 106024b246eSLinus Torvalds .prologue 0 \n\ 107024b246eSLinus Torvalds srl $16, 6, $16 \n\ 108024b246eSLinus Torvalds .align 4 \n\ 109024b246eSLinus Torvalds 3: \n\ 110024b246eSLinus Torvalds ldq $0,0($17) \n\ 111024b246eSLinus Torvalds ldq $1,0($18) \n\ 112024b246eSLinus Torvalds ldq $2,0($19) \n\ 113024b246eSLinus Torvalds ldq $3,8($17) \n\ 114024b246eSLinus Torvalds \n\ 115024b246eSLinus Torvalds ldq $4,8($18) \n\ 116024b246eSLinus Torvalds ldq $6,16($17) \n\ 117024b246eSLinus Torvalds ldq $7,16($18) \n\ 118024b246eSLinus Torvalds ldq $21,24($17) \n\ 119024b246eSLinus Torvalds \n\ 120024b246eSLinus Torvalds ldq $22,24($18) \n\ 121024b246eSLinus Torvalds ldq $24,32($17) \n\ 122024b246eSLinus Torvalds ldq $25,32($18) \n\ 123024b246eSLinus Torvalds ldq $5,8($19) \n\ 124024b246eSLinus Torvalds \n\ 125024b246eSLinus Torvalds ldq $20,16($19) \n\ 126024b246eSLinus Torvalds ldq $23,24($19) \n\ 127024b246eSLinus Torvalds ldq $27,32($19) \n\ 128024b246eSLinus Torvalds nop \n\ 129024b246eSLinus Torvalds \n\ 130024b246eSLinus Torvalds xor $0,$1,$1 # 8 cycles from $0 load \n\ 131024b246eSLinus Torvalds xor $3,$4,$4 # 6 cycles from $4 load \n\ 132024b246eSLinus Torvalds xor $6,$7,$7 # 6 cycles from $7 load \n\ 133024b246eSLinus Torvalds xor $21,$22,$22 # 5 cycles from $22 load \n\ 134024b246eSLinus Torvalds \n\ 135024b246eSLinus Torvalds xor $1,$2,$2 # 9 cycles from $2 load \n\ 136024b246eSLinus Torvalds xor $24,$25,$25 # 5 cycles from $25 load \n\ 137024b246eSLinus Torvalds stq $2,0($17) \n\ 138024b246eSLinus Torvalds xor $4,$5,$5 # 6 cycles from $5 load \n\ 139024b246eSLinus Torvalds \n\ 140024b246eSLinus Torvalds stq $5,8($17) \n\ 141024b246eSLinus Torvalds xor $7,$20,$20 # 7 cycles from $20 load \n\ 142024b246eSLinus Torvalds stq $20,16($17) \n\ 143024b246eSLinus Torvalds xor $22,$23,$23 # 7 cycles from $23 load \n\ 144024b246eSLinus Torvalds \n\ 145024b246eSLinus Torvalds stq $23,24($17) \n\ 146024b246eSLinus Torvalds xor $25,$27,$27 # 7 cycles from $27 load \n\ 147024b246eSLinus Torvalds stq $27,32($17) \n\ 148024b246eSLinus Torvalds nop \n\ 149024b246eSLinus Torvalds \n\ 150024b246eSLinus Torvalds ldq $0,40($17) \n\ 151024b246eSLinus Torvalds ldq $1,40($18) \n\ 152024b246eSLinus Torvalds ldq $3,48($17) \n\ 153024b246eSLinus Torvalds ldq $4,48($18) \n\ 154024b246eSLinus Torvalds \n\ 155024b246eSLinus Torvalds ldq $6,56($17) \n\ 156024b246eSLinus Torvalds ldq $7,56($18) \n\ 157024b246eSLinus Torvalds ldq $2,40($19) \n\ 158024b246eSLinus Torvalds ldq $5,48($19) \n\ 159024b246eSLinus Torvalds \n\ 160024b246eSLinus Torvalds ldq $20,56($19) \n\ 161024b246eSLinus Torvalds xor $0,$1,$1 # 4 cycles from $1 load \n\ 162024b246eSLinus Torvalds xor $3,$4,$4 # 5 cycles from $4 load \n\ 163024b246eSLinus Torvalds xor $6,$7,$7 # 5 cycles from $7 load \n\ 164024b246eSLinus Torvalds \n\ 165024b246eSLinus Torvalds xor $1,$2,$2 # 4 cycles from $2 load \n\ 166024b246eSLinus Torvalds xor $4,$5,$5 # 5 cycles from $5 load \n\ 167024b246eSLinus Torvalds stq $2,40($17) \n\ 168024b246eSLinus Torvalds xor $7,$20,$20 # 4 cycles from $20 load \n\ 169024b246eSLinus Torvalds \n\ 170024b246eSLinus Torvalds stq $5,48($17) \n\ 171024b246eSLinus Torvalds subq $16,1,$16 \n\ 172024b246eSLinus Torvalds stq $20,56($17) \n\ 173024b246eSLinus Torvalds addq $19,64,$19 \n\ 174024b246eSLinus Torvalds \n\ 175024b246eSLinus Torvalds addq $18,64,$18 \n\ 176024b246eSLinus Torvalds addq $17,64,$17 \n\ 177024b246eSLinus Torvalds bgt $16,3b \n\ 178024b246eSLinus Torvalds ret \n\ 179024b246eSLinus Torvalds .end xor_alpha_3 \n\ 180024b246eSLinus Torvalds \n\ 181024b246eSLinus Torvalds .align 3 \n\ 182024b246eSLinus Torvalds .ent xor_alpha_4 \n\ 183024b246eSLinus Torvalds xor_alpha_4: \n\ 184024b246eSLinus Torvalds .prologue 0 \n\ 185024b246eSLinus Torvalds srl $16, 6, $16 \n\ 186024b246eSLinus Torvalds .align 4 \n\ 187024b246eSLinus Torvalds 4: \n\ 188024b246eSLinus Torvalds ldq $0,0($17) \n\ 189024b246eSLinus Torvalds ldq $1,0($18) \n\ 190024b246eSLinus Torvalds ldq $2,0($19) \n\ 191024b246eSLinus Torvalds ldq $3,0($20) \n\ 192024b246eSLinus Torvalds \n\ 193024b246eSLinus Torvalds ldq $4,8($17) \n\ 194024b246eSLinus Torvalds ldq $5,8($18) \n\ 195024b246eSLinus Torvalds ldq $6,8($19) \n\ 196024b246eSLinus Torvalds ldq $7,8($20) \n\ 197024b246eSLinus Torvalds \n\ 198024b246eSLinus Torvalds ldq $21,16($17) \n\ 199024b246eSLinus Torvalds ldq $22,16($18) \n\ 200024b246eSLinus Torvalds ldq $23,16($19) \n\ 201024b246eSLinus Torvalds ldq $24,16($20) \n\ 202024b246eSLinus Torvalds \n\ 203024b246eSLinus Torvalds ldq $25,24($17) \n\ 204024b246eSLinus Torvalds xor $0,$1,$1 # 6 cycles from $1 load \n\ 205024b246eSLinus Torvalds ldq $27,24($18) \n\ 206024b246eSLinus Torvalds xor $2,$3,$3 # 6 cycles from $3 load \n\ 207024b246eSLinus Torvalds \n\ 208024b246eSLinus Torvalds ldq $0,24($19) \n\ 209024b246eSLinus Torvalds xor $1,$3,$3 \n\ 210024b246eSLinus Torvalds ldq $1,24($20) \n\ 211024b246eSLinus Torvalds xor $4,$5,$5 # 7 cycles from $5 load \n\ 212024b246eSLinus Torvalds \n\ 213024b246eSLinus Torvalds stq $3,0($17) \n\ 214024b246eSLinus Torvalds xor $6,$7,$7 \n\ 215024b246eSLinus Torvalds xor $21,$22,$22 # 7 cycles from $22 load \n\ 216024b246eSLinus Torvalds xor $5,$7,$7 \n\ 217024b246eSLinus Torvalds \n\ 218024b246eSLinus Torvalds stq $7,8($17) \n\ 219024b246eSLinus Torvalds xor $23,$24,$24 # 7 cycles from $24 load \n\ 220024b246eSLinus Torvalds ldq $2,32($17) \n\ 221024b246eSLinus Torvalds xor $22,$24,$24 \n\ 222024b246eSLinus Torvalds \n\ 223024b246eSLinus Torvalds ldq $3,32($18) \n\ 224024b246eSLinus Torvalds ldq $4,32($19) \n\ 225024b246eSLinus Torvalds ldq $5,32($20) \n\ 226024b246eSLinus Torvalds xor $25,$27,$27 # 8 cycles from $27 load \n\ 227024b246eSLinus Torvalds \n\ 228024b246eSLinus Torvalds ldq $6,40($17) \n\ 229024b246eSLinus Torvalds ldq $7,40($18) \n\ 230024b246eSLinus Torvalds ldq $21,40($19) \n\ 231024b246eSLinus Torvalds ldq $22,40($20) \n\ 232024b246eSLinus Torvalds \n\ 233024b246eSLinus Torvalds stq $24,16($17) \n\ 234024b246eSLinus Torvalds xor $0,$1,$1 # 9 cycles from $1 load \n\ 235024b246eSLinus Torvalds xor $2,$3,$3 # 5 cycles from $3 load \n\ 236024b246eSLinus Torvalds xor $27,$1,$1 \n\ 237024b246eSLinus Torvalds \n\ 238024b246eSLinus Torvalds stq $1,24($17) \n\ 239024b246eSLinus Torvalds xor $4,$5,$5 # 5 cycles from $5 load \n\ 240024b246eSLinus Torvalds ldq $23,48($17) \n\ 241024b246eSLinus Torvalds ldq $24,48($18) \n\ 242024b246eSLinus Torvalds \n\ 243024b246eSLinus Torvalds ldq $25,48($19) \n\ 244024b246eSLinus Torvalds xor $3,$5,$5 \n\ 245024b246eSLinus Torvalds ldq $27,48($20) \n\ 246024b246eSLinus Torvalds ldq $0,56($17) \n\ 247024b246eSLinus Torvalds \n\ 248024b246eSLinus Torvalds ldq $1,56($18) \n\ 249024b246eSLinus Torvalds ldq $2,56($19) \n\ 250024b246eSLinus Torvalds xor $6,$7,$7 # 8 cycles from $6 load \n\ 251024b246eSLinus Torvalds ldq $3,56($20) \n\ 252024b246eSLinus Torvalds \n\ 253024b246eSLinus Torvalds stq $5,32($17) \n\ 254024b246eSLinus Torvalds xor $21,$22,$22 # 8 cycles from $22 load \n\ 255024b246eSLinus Torvalds xor $7,$22,$22 \n\ 256024b246eSLinus Torvalds xor $23,$24,$24 # 5 cycles from $24 load \n\ 257024b246eSLinus Torvalds \n\ 258024b246eSLinus Torvalds stq $22,40($17) \n\ 259024b246eSLinus Torvalds xor $25,$27,$27 # 5 cycles from $27 load \n\ 260024b246eSLinus Torvalds xor $24,$27,$27 \n\ 261024b246eSLinus Torvalds xor $0,$1,$1 # 5 cycles from $1 load \n\ 262024b246eSLinus Torvalds \n\ 263024b246eSLinus Torvalds stq $27,48($17) \n\ 264024b246eSLinus Torvalds xor $2,$3,$3 # 4 cycles from $3 load \n\ 265024b246eSLinus Torvalds xor $1,$3,$3 \n\ 266024b246eSLinus Torvalds subq $16,1,$16 \n\ 267024b246eSLinus Torvalds \n\ 268024b246eSLinus Torvalds stq $3,56($17) \n\ 269024b246eSLinus Torvalds addq $20,64,$20 \n\ 270024b246eSLinus Torvalds addq $19,64,$19 \n\ 271024b246eSLinus Torvalds addq $18,64,$18 \n\ 272024b246eSLinus Torvalds \n\ 273024b246eSLinus Torvalds addq $17,64,$17 \n\ 274024b246eSLinus Torvalds bgt $16,4b \n\ 275024b246eSLinus Torvalds ret \n\ 276024b246eSLinus Torvalds .end xor_alpha_4 \n\ 277024b246eSLinus Torvalds \n\ 278024b246eSLinus Torvalds .align 3 \n\ 279024b246eSLinus Torvalds .ent xor_alpha_5 \n\ 280024b246eSLinus Torvalds xor_alpha_5: \n\ 281024b246eSLinus Torvalds .prologue 0 \n\ 282024b246eSLinus Torvalds srl $16, 6, $16 \n\ 283024b246eSLinus Torvalds .align 4 \n\ 284024b246eSLinus Torvalds 5: \n\ 285024b246eSLinus Torvalds ldq $0,0($17) \n\ 286024b246eSLinus Torvalds ldq $1,0($18) \n\ 287024b246eSLinus Torvalds ldq $2,0($19) \n\ 288024b246eSLinus Torvalds ldq $3,0($20) \n\ 289024b246eSLinus Torvalds \n\ 290024b246eSLinus Torvalds ldq $4,0($21) \n\ 291024b246eSLinus Torvalds ldq $5,8($17) \n\ 292024b246eSLinus Torvalds ldq $6,8($18) \n\ 293024b246eSLinus Torvalds ldq $7,8($19) \n\ 294024b246eSLinus Torvalds \n\ 295024b246eSLinus Torvalds ldq $22,8($20) \n\ 296024b246eSLinus Torvalds ldq $23,8($21) \n\ 297024b246eSLinus Torvalds ldq $24,16($17) \n\ 298024b246eSLinus Torvalds ldq $25,16($18) \n\ 299024b246eSLinus Torvalds \n\ 300024b246eSLinus Torvalds ldq $27,16($19) \n\ 301024b246eSLinus Torvalds xor $0,$1,$1 # 6 cycles from $1 load \n\ 302024b246eSLinus Torvalds ldq $28,16($20) \n\ 303024b246eSLinus Torvalds xor $2,$3,$3 # 6 cycles from $3 load \n\ 304024b246eSLinus Torvalds \n\ 305024b246eSLinus Torvalds ldq $0,16($21) \n\ 306024b246eSLinus Torvalds xor $1,$3,$3 \n\ 307024b246eSLinus Torvalds ldq $1,24($17) \n\ 308024b246eSLinus Torvalds xor $3,$4,$4 # 7 cycles from $4 load \n\ 309024b246eSLinus Torvalds \n\ 310024b246eSLinus Torvalds stq $4,0($17) \n\ 311024b246eSLinus Torvalds xor $5,$6,$6 # 7 cycles from $6 load \n\ 312024b246eSLinus Torvalds xor $7,$22,$22 # 7 cycles from $22 load \n\ 313024b246eSLinus Torvalds xor $6,$23,$23 # 7 cycles from $23 load \n\ 314024b246eSLinus Torvalds \n\ 315024b246eSLinus Torvalds ldq $2,24($18) \n\ 316024b246eSLinus Torvalds xor $22,$23,$23 \n\ 317024b246eSLinus Torvalds ldq $3,24($19) \n\ 318024b246eSLinus Torvalds xor $24,$25,$25 # 8 cycles from $25 load \n\ 319024b246eSLinus Torvalds \n\ 320024b246eSLinus Torvalds stq $23,8($17) \n\ 321024b246eSLinus Torvalds xor $25,$27,$27 # 8 cycles from $27 load \n\ 322024b246eSLinus Torvalds ldq $4,24($20) \n\ 323024b246eSLinus Torvalds xor $28,$0,$0 # 7 cycles from $0 load \n\ 324024b246eSLinus Torvalds \n\ 325024b246eSLinus Torvalds ldq $5,24($21) \n\ 326024b246eSLinus Torvalds xor $27,$0,$0 \n\ 327024b246eSLinus Torvalds ldq $6,32($17) \n\ 328024b246eSLinus Torvalds ldq $7,32($18) \n\ 329024b246eSLinus Torvalds \n\ 330024b246eSLinus Torvalds stq $0,16($17) \n\ 331024b246eSLinus Torvalds xor $1,$2,$2 # 6 cycles from $2 load \n\ 332024b246eSLinus Torvalds ldq $22,32($19) \n\ 333024b246eSLinus Torvalds xor $3,$4,$4 # 4 cycles from $4 load \n\ 334024b246eSLinus Torvalds \n\ 335024b246eSLinus Torvalds ldq $23,32($20) \n\ 336024b246eSLinus Torvalds xor $2,$4,$4 \n\ 337024b246eSLinus Torvalds ldq $24,32($21) \n\ 338024b246eSLinus Torvalds ldq $25,40($17) \n\ 339024b246eSLinus Torvalds \n\ 340024b246eSLinus Torvalds ldq $27,40($18) \n\ 341024b246eSLinus Torvalds ldq $28,40($19) \n\ 342024b246eSLinus Torvalds ldq $0,40($20) \n\ 343024b246eSLinus Torvalds xor $4,$5,$5 # 7 cycles from $5 load \n\ 344024b246eSLinus Torvalds \n\ 345024b246eSLinus Torvalds stq $5,24($17) \n\ 346024b246eSLinus Torvalds xor $6,$7,$7 # 7 cycles from $7 load \n\ 347024b246eSLinus Torvalds ldq $1,40($21) \n\ 348024b246eSLinus Torvalds ldq $2,48($17) \n\ 349024b246eSLinus Torvalds \n\ 350024b246eSLinus Torvalds ldq $3,48($18) \n\ 351024b246eSLinus Torvalds xor $7,$22,$22 # 7 cycles from $22 load \n\ 352024b246eSLinus Torvalds ldq $4,48($19) \n\ 353024b246eSLinus Torvalds xor $23,$24,$24 # 6 cycles from $24 load \n\ 354024b246eSLinus Torvalds \n\ 355024b246eSLinus Torvalds ldq $5,48($20) \n\ 356024b246eSLinus Torvalds xor $22,$24,$24 \n\ 357024b246eSLinus Torvalds ldq $6,48($21) \n\ 358024b246eSLinus Torvalds xor $25,$27,$27 # 7 cycles from $27 load \n\ 359024b246eSLinus Torvalds \n\ 360024b246eSLinus Torvalds stq $24,32($17) \n\ 361024b246eSLinus Torvalds xor $27,$28,$28 # 8 cycles from $28 load \n\ 362024b246eSLinus Torvalds ldq $7,56($17) \n\ 363024b246eSLinus Torvalds xor $0,$1,$1 # 6 cycles from $1 load \n\ 364024b246eSLinus Torvalds \n\ 365024b246eSLinus Torvalds ldq $22,56($18) \n\ 366024b246eSLinus Torvalds ldq $23,56($19) \n\ 367024b246eSLinus Torvalds ldq $24,56($20) \n\ 368024b246eSLinus Torvalds ldq $25,56($21) \n\ 369024b246eSLinus Torvalds \n\ 370024b246eSLinus Torvalds xor $28,$1,$1 \n\ 371024b246eSLinus Torvalds xor $2,$3,$3 # 9 cycles from $3 load \n\ 372024b246eSLinus Torvalds xor $3,$4,$4 # 9 cycles from $4 load \n\ 373024b246eSLinus Torvalds xor $5,$6,$6 # 8 cycles from $6 load \n\ 374024b246eSLinus Torvalds \n\ 375024b246eSLinus Torvalds stq $1,40($17) \n\ 376024b246eSLinus Torvalds xor $4,$6,$6 \n\ 377024b246eSLinus Torvalds xor $7,$22,$22 # 7 cycles from $22 load \n\ 378024b246eSLinus Torvalds xor $23,$24,$24 # 6 cycles from $24 load \n\ 379024b246eSLinus Torvalds \n\ 380024b246eSLinus Torvalds stq $6,48($17) \n\ 381024b246eSLinus Torvalds xor $22,$24,$24 \n\ 382024b246eSLinus Torvalds subq $16,1,$16 \n\ 383024b246eSLinus Torvalds xor $24,$25,$25 # 8 cycles from $25 load \n\ 384024b246eSLinus Torvalds \n\ 385024b246eSLinus Torvalds stq $25,56($17) \n\ 386024b246eSLinus Torvalds addq $21,64,$21 \n\ 387024b246eSLinus Torvalds addq $20,64,$20 \n\ 388024b246eSLinus Torvalds addq $19,64,$19 \n\ 389024b246eSLinus Torvalds \n\ 390024b246eSLinus Torvalds addq $18,64,$18 \n\ 391024b246eSLinus Torvalds addq $17,64,$17 \n\ 392024b246eSLinus Torvalds bgt $16,5b \n\ 393024b246eSLinus Torvalds ret \n\ 394024b246eSLinus Torvalds .end xor_alpha_5 \n\ 395024b246eSLinus Torvalds \n\ 396024b246eSLinus Torvalds .align 3 \n\ 397024b246eSLinus Torvalds .ent xor_alpha_prefetch_2 \n\ 398024b246eSLinus Torvalds xor_alpha_prefetch_2: \n\ 399024b246eSLinus Torvalds .prologue 0 \n\ 400024b246eSLinus Torvalds srl $16, 6, $16 \n\ 401024b246eSLinus Torvalds \n\ 402024b246eSLinus Torvalds ldq $31, 0($17) \n\ 403024b246eSLinus Torvalds ldq $31, 0($18) \n\ 404024b246eSLinus Torvalds \n\ 405024b246eSLinus Torvalds ldq $31, 64($17) \n\ 406024b246eSLinus Torvalds ldq $31, 64($18) \n\ 407024b246eSLinus Torvalds \n\ 408024b246eSLinus Torvalds ldq $31, 128($17) \n\ 409024b246eSLinus Torvalds ldq $31, 128($18) \n\ 410024b246eSLinus Torvalds \n\ 411024b246eSLinus Torvalds ldq $31, 192($17) \n\ 412024b246eSLinus Torvalds ldq $31, 192($18) \n\ 413024b246eSLinus Torvalds .align 4 \n\ 414024b246eSLinus Torvalds 2: \n\ 415024b246eSLinus Torvalds ldq $0,0($17) \n\ 416024b246eSLinus Torvalds ldq $1,0($18) \n\ 417024b246eSLinus Torvalds ldq $2,8($17) \n\ 418024b246eSLinus Torvalds ldq $3,8($18) \n\ 419024b246eSLinus Torvalds \n\ 420024b246eSLinus Torvalds ldq $4,16($17) \n\ 421024b246eSLinus Torvalds ldq $5,16($18) \n\ 422024b246eSLinus Torvalds ldq $6,24($17) \n\ 423024b246eSLinus Torvalds ldq $7,24($18) \n\ 424024b246eSLinus Torvalds \n\ 425024b246eSLinus Torvalds ldq $19,32($17) \n\ 426024b246eSLinus Torvalds ldq $20,32($18) \n\ 427024b246eSLinus Torvalds ldq $21,40($17) \n\ 428024b246eSLinus Torvalds ldq $22,40($18) \n\ 429024b246eSLinus Torvalds \n\ 430024b246eSLinus Torvalds ldq $23,48($17) \n\ 431024b246eSLinus Torvalds ldq $24,48($18) \n\ 432024b246eSLinus Torvalds ldq $25,56($17) \n\ 433024b246eSLinus Torvalds ldq $27,56($18) \n\ 434024b246eSLinus Torvalds \n\ 435024b246eSLinus Torvalds ldq $31,256($17) \n\ 436024b246eSLinus Torvalds xor $0,$1,$0 # 8 cycles from $1 load \n\ 437024b246eSLinus Torvalds ldq $31,256($18) \n\ 438024b246eSLinus Torvalds xor $2,$3,$2 \n\ 439024b246eSLinus Torvalds \n\ 440024b246eSLinus Torvalds stq $0,0($17) \n\ 441024b246eSLinus Torvalds xor $4,$5,$4 \n\ 442024b246eSLinus Torvalds stq $2,8($17) \n\ 443024b246eSLinus Torvalds xor $6,$7,$6 \n\ 444024b246eSLinus Torvalds \n\ 445024b246eSLinus Torvalds stq $4,16($17) \n\ 446024b246eSLinus Torvalds xor $19,$20,$19 \n\ 447024b246eSLinus Torvalds stq $6,24($17) \n\ 448024b246eSLinus Torvalds xor $21,$22,$21 \n\ 449024b246eSLinus Torvalds \n\ 450024b246eSLinus Torvalds stq $19,32($17) \n\ 451024b246eSLinus Torvalds xor $23,$24,$23 \n\ 452024b246eSLinus Torvalds stq $21,40($17) \n\ 453024b246eSLinus Torvalds xor $25,$27,$25 \n\ 454024b246eSLinus Torvalds \n\ 455024b246eSLinus Torvalds stq $23,48($17) \n\ 456024b246eSLinus Torvalds subq $16,1,$16 \n\ 457024b246eSLinus Torvalds stq $25,56($17) \n\ 458024b246eSLinus Torvalds addq $17,64,$17 \n\ 459024b246eSLinus Torvalds \n\ 460024b246eSLinus Torvalds addq $18,64,$18 \n\ 461024b246eSLinus Torvalds bgt $16,2b \n\ 462024b246eSLinus Torvalds ret \n\ 463024b246eSLinus Torvalds .end xor_alpha_prefetch_2 \n\ 464024b246eSLinus Torvalds \n\ 465024b246eSLinus Torvalds .align 3 \n\ 466024b246eSLinus Torvalds .ent xor_alpha_prefetch_3 \n\ 467024b246eSLinus Torvalds xor_alpha_prefetch_3: \n\ 468024b246eSLinus Torvalds .prologue 0 \n\ 469024b246eSLinus Torvalds srl $16, 6, $16 \n\ 470024b246eSLinus Torvalds \n\ 471024b246eSLinus Torvalds ldq $31, 0($17) \n\ 472024b246eSLinus Torvalds ldq $31, 0($18) \n\ 473024b246eSLinus Torvalds ldq $31, 0($19) \n\ 474024b246eSLinus Torvalds \n\ 475024b246eSLinus Torvalds ldq $31, 64($17) \n\ 476024b246eSLinus Torvalds ldq $31, 64($18) \n\ 477024b246eSLinus Torvalds ldq $31, 64($19) \n\ 478024b246eSLinus Torvalds \n\ 479024b246eSLinus Torvalds ldq $31, 128($17) \n\ 480024b246eSLinus Torvalds ldq $31, 128($18) \n\ 481024b246eSLinus Torvalds ldq $31, 128($19) \n\ 482024b246eSLinus Torvalds \n\ 483024b246eSLinus Torvalds ldq $31, 192($17) \n\ 484024b246eSLinus Torvalds ldq $31, 192($18) \n\ 485024b246eSLinus Torvalds ldq $31, 192($19) \n\ 486024b246eSLinus Torvalds .align 4 \n\ 487024b246eSLinus Torvalds 3: \n\ 488024b246eSLinus Torvalds ldq $0,0($17) \n\ 489024b246eSLinus Torvalds ldq $1,0($18) \n\ 490024b246eSLinus Torvalds ldq $2,0($19) \n\ 491024b246eSLinus Torvalds ldq $3,8($17) \n\ 492024b246eSLinus Torvalds \n\ 493024b246eSLinus Torvalds ldq $4,8($18) \n\ 494024b246eSLinus Torvalds ldq $6,16($17) \n\ 495024b246eSLinus Torvalds ldq $7,16($18) \n\ 496024b246eSLinus Torvalds ldq $21,24($17) \n\ 497024b246eSLinus Torvalds \n\ 498024b246eSLinus Torvalds ldq $22,24($18) \n\ 499024b246eSLinus Torvalds ldq $24,32($17) \n\ 500024b246eSLinus Torvalds ldq $25,32($18) \n\ 501024b246eSLinus Torvalds ldq $5,8($19) \n\ 502024b246eSLinus Torvalds \n\ 503024b246eSLinus Torvalds ldq $20,16($19) \n\ 504024b246eSLinus Torvalds ldq $23,24($19) \n\ 505024b246eSLinus Torvalds ldq $27,32($19) \n\ 506024b246eSLinus Torvalds nop \n\ 507024b246eSLinus Torvalds \n\ 508024b246eSLinus Torvalds xor $0,$1,$1 # 8 cycles from $0 load \n\ 509024b246eSLinus Torvalds xor $3,$4,$4 # 7 cycles from $4 load \n\ 510024b246eSLinus Torvalds xor $6,$7,$7 # 6 cycles from $7 load \n\ 511024b246eSLinus Torvalds xor $21,$22,$22 # 5 cycles from $22 load \n\ 512024b246eSLinus Torvalds \n\ 513024b246eSLinus Torvalds xor $1,$2,$2 # 9 cycles from $2 load \n\ 514024b246eSLinus Torvalds xor $24,$25,$25 # 5 cycles from $25 load \n\ 515024b246eSLinus Torvalds stq $2,0($17) \n\ 516024b246eSLinus Torvalds xor $4,$5,$5 # 6 cycles from $5 load \n\ 517024b246eSLinus Torvalds \n\ 518024b246eSLinus Torvalds stq $5,8($17) \n\ 519024b246eSLinus Torvalds xor $7,$20,$20 # 7 cycles from $20 load \n\ 520024b246eSLinus Torvalds stq $20,16($17) \n\ 521024b246eSLinus Torvalds xor $22,$23,$23 # 7 cycles from $23 load \n\ 522024b246eSLinus Torvalds \n\ 523024b246eSLinus Torvalds stq $23,24($17) \n\ 524024b246eSLinus Torvalds xor $25,$27,$27 # 7 cycles from $27 load \n\ 525024b246eSLinus Torvalds stq $27,32($17) \n\ 526024b246eSLinus Torvalds nop \n\ 527024b246eSLinus Torvalds \n\ 528024b246eSLinus Torvalds ldq $0,40($17) \n\ 529024b246eSLinus Torvalds ldq $1,40($18) \n\ 530024b246eSLinus Torvalds ldq $3,48($17) \n\ 531024b246eSLinus Torvalds ldq $4,48($18) \n\ 532024b246eSLinus Torvalds \n\ 533024b246eSLinus Torvalds ldq $6,56($17) \n\ 534024b246eSLinus Torvalds ldq $7,56($18) \n\ 535024b246eSLinus Torvalds ldq $2,40($19) \n\ 536024b246eSLinus Torvalds ldq $5,48($19) \n\ 537024b246eSLinus Torvalds \n\ 538024b246eSLinus Torvalds ldq $20,56($19) \n\ 539024b246eSLinus Torvalds ldq $31,256($17) \n\ 540024b246eSLinus Torvalds ldq $31,256($18) \n\ 541024b246eSLinus Torvalds ldq $31,256($19) \n\ 542024b246eSLinus Torvalds \n\ 543024b246eSLinus Torvalds xor $0,$1,$1 # 6 cycles from $1 load \n\ 544024b246eSLinus Torvalds xor $3,$4,$4 # 5 cycles from $4 load \n\ 545024b246eSLinus Torvalds xor $6,$7,$7 # 5 cycles from $7 load \n\ 546024b246eSLinus Torvalds xor $1,$2,$2 # 4 cycles from $2 load \n\ 547024b246eSLinus Torvalds \n\ 548024b246eSLinus Torvalds xor $4,$5,$5 # 5 cycles from $5 load \n\ 549024b246eSLinus Torvalds xor $7,$20,$20 # 4 cycles from $20 load \n\ 550024b246eSLinus Torvalds stq $2,40($17) \n\ 551024b246eSLinus Torvalds subq $16,1,$16 \n\ 552024b246eSLinus Torvalds \n\ 553024b246eSLinus Torvalds stq $5,48($17) \n\ 554024b246eSLinus Torvalds addq $19,64,$19 \n\ 555024b246eSLinus Torvalds stq $20,56($17) \n\ 556024b246eSLinus Torvalds addq $18,64,$18 \n\ 557024b246eSLinus Torvalds \n\ 558024b246eSLinus Torvalds addq $17,64,$17 \n\ 559024b246eSLinus Torvalds bgt $16,3b \n\ 560024b246eSLinus Torvalds ret \n\ 561024b246eSLinus Torvalds .end xor_alpha_prefetch_3 \n\ 562024b246eSLinus Torvalds \n\ 563024b246eSLinus Torvalds .align 3 \n\ 564024b246eSLinus Torvalds .ent xor_alpha_prefetch_4 \n\ 565024b246eSLinus Torvalds xor_alpha_prefetch_4: \n\ 566024b246eSLinus Torvalds .prologue 0 \n\ 567024b246eSLinus Torvalds srl $16, 6, $16 \n\ 568024b246eSLinus Torvalds \n\ 569024b246eSLinus Torvalds ldq $31, 0($17) \n\ 570024b246eSLinus Torvalds ldq $31, 0($18) \n\ 571024b246eSLinus Torvalds ldq $31, 0($19) \n\ 572024b246eSLinus Torvalds ldq $31, 0($20) \n\ 573024b246eSLinus Torvalds \n\ 574024b246eSLinus Torvalds ldq $31, 64($17) \n\ 575024b246eSLinus Torvalds ldq $31, 64($18) \n\ 576024b246eSLinus Torvalds ldq $31, 64($19) \n\ 577024b246eSLinus Torvalds ldq $31, 64($20) \n\ 578024b246eSLinus Torvalds \n\ 579024b246eSLinus Torvalds ldq $31, 128($17) \n\ 580024b246eSLinus Torvalds ldq $31, 128($18) \n\ 581024b246eSLinus Torvalds ldq $31, 128($19) \n\ 582024b246eSLinus Torvalds ldq $31, 128($20) \n\ 583024b246eSLinus Torvalds \n\ 584024b246eSLinus Torvalds ldq $31, 192($17) \n\ 585024b246eSLinus Torvalds ldq $31, 192($18) \n\ 586024b246eSLinus Torvalds ldq $31, 192($19) \n\ 587024b246eSLinus Torvalds ldq $31, 192($20) \n\ 588024b246eSLinus Torvalds .align 4 \n\ 589024b246eSLinus Torvalds 4: \n\ 590024b246eSLinus Torvalds ldq $0,0($17) \n\ 591024b246eSLinus Torvalds ldq $1,0($18) \n\ 592024b246eSLinus Torvalds ldq $2,0($19) \n\ 593024b246eSLinus Torvalds ldq $3,0($20) \n\ 594024b246eSLinus Torvalds \n\ 595024b246eSLinus Torvalds ldq $4,8($17) \n\ 596024b246eSLinus Torvalds ldq $5,8($18) \n\ 597024b246eSLinus Torvalds ldq $6,8($19) \n\ 598024b246eSLinus Torvalds ldq $7,8($20) \n\ 599024b246eSLinus Torvalds \n\ 600024b246eSLinus Torvalds ldq $21,16($17) \n\ 601024b246eSLinus Torvalds ldq $22,16($18) \n\ 602024b246eSLinus Torvalds ldq $23,16($19) \n\ 603024b246eSLinus Torvalds ldq $24,16($20) \n\ 604024b246eSLinus Torvalds \n\ 605024b246eSLinus Torvalds ldq $25,24($17) \n\ 606024b246eSLinus Torvalds xor $0,$1,$1 # 6 cycles from $1 load \n\ 607024b246eSLinus Torvalds ldq $27,24($18) \n\ 608024b246eSLinus Torvalds xor $2,$3,$3 # 6 cycles from $3 load \n\ 609024b246eSLinus Torvalds \n\ 610024b246eSLinus Torvalds ldq $0,24($19) \n\ 611024b246eSLinus Torvalds xor $1,$3,$3 \n\ 612024b246eSLinus Torvalds ldq $1,24($20) \n\ 613024b246eSLinus Torvalds xor $4,$5,$5 # 7 cycles from $5 load \n\ 614024b246eSLinus Torvalds \n\ 615024b246eSLinus Torvalds stq $3,0($17) \n\ 616024b246eSLinus Torvalds xor $6,$7,$7 \n\ 617024b246eSLinus Torvalds xor $21,$22,$22 # 7 cycles from $22 load \n\ 618024b246eSLinus Torvalds xor $5,$7,$7 \n\ 619024b246eSLinus Torvalds \n\ 620024b246eSLinus Torvalds stq $7,8($17) \n\ 621024b246eSLinus Torvalds xor $23,$24,$24 # 7 cycles from $24 load \n\ 622024b246eSLinus Torvalds ldq $2,32($17) \n\ 623024b246eSLinus Torvalds xor $22,$24,$24 \n\ 624024b246eSLinus Torvalds \n\ 625024b246eSLinus Torvalds ldq $3,32($18) \n\ 626024b246eSLinus Torvalds ldq $4,32($19) \n\ 627024b246eSLinus Torvalds ldq $5,32($20) \n\ 628024b246eSLinus Torvalds xor $25,$27,$27 # 8 cycles from $27 load \n\ 629024b246eSLinus Torvalds \n\ 630024b246eSLinus Torvalds ldq $6,40($17) \n\ 631024b246eSLinus Torvalds ldq $7,40($18) \n\ 632024b246eSLinus Torvalds ldq $21,40($19) \n\ 633024b246eSLinus Torvalds ldq $22,40($20) \n\ 634024b246eSLinus Torvalds \n\ 635024b246eSLinus Torvalds stq $24,16($17) \n\ 636024b246eSLinus Torvalds xor $0,$1,$1 # 9 cycles from $1 load \n\ 637024b246eSLinus Torvalds xor $2,$3,$3 # 5 cycles from $3 load \n\ 638024b246eSLinus Torvalds xor $27,$1,$1 \n\ 639024b246eSLinus Torvalds \n\ 640024b246eSLinus Torvalds stq $1,24($17) \n\ 641024b246eSLinus Torvalds xor $4,$5,$5 # 5 cycles from $5 load \n\ 642024b246eSLinus Torvalds ldq $23,48($17) \n\ 643024b246eSLinus Torvalds xor $3,$5,$5 \n\ 644024b246eSLinus Torvalds \n\ 645024b246eSLinus Torvalds ldq $24,48($18) \n\ 646024b246eSLinus Torvalds ldq $25,48($19) \n\ 647024b246eSLinus Torvalds ldq $27,48($20) \n\ 648024b246eSLinus Torvalds ldq $0,56($17) \n\ 649024b246eSLinus Torvalds \n\ 650024b246eSLinus Torvalds ldq $1,56($18) \n\ 651024b246eSLinus Torvalds ldq $2,56($19) \n\ 652024b246eSLinus Torvalds ldq $3,56($20) \n\ 653024b246eSLinus Torvalds xor $6,$7,$7 # 8 cycles from $6 load \n\ 654024b246eSLinus Torvalds \n\ 655024b246eSLinus Torvalds ldq $31,256($17) \n\ 656024b246eSLinus Torvalds xor $21,$22,$22 # 8 cycles from $22 load \n\ 657024b246eSLinus Torvalds ldq $31,256($18) \n\ 658024b246eSLinus Torvalds xor $7,$22,$22 \n\ 659024b246eSLinus Torvalds \n\ 660024b246eSLinus Torvalds ldq $31,256($19) \n\ 661024b246eSLinus Torvalds xor $23,$24,$24 # 6 cycles from $24 load \n\ 662024b246eSLinus Torvalds ldq $31,256($20) \n\ 663024b246eSLinus Torvalds xor $25,$27,$27 # 6 cycles from $27 load \n\ 664024b246eSLinus Torvalds \n\ 665024b246eSLinus Torvalds stq $5,32($17) \n\ 666024b246eSLinus Torvalds xor $24,$27,$27 \n\ 667024b246eSLinus Torvalds xor $0,$1,$1 # 7 cycles from $1 load \n\ 668024b246eSLinus Torvalds xor $2,$3,$3 # 6 cycles from $3 load \n\ 669024b246eSLinus Torvalds \n\ 670024b246eSLinus Torvalds stq $22,40($17) \n\ 671024b246eSLinus Torvalds xor $1,$3,$3 \n\ 672024b246eSLinus Torvalds stq $27,48($17) \n\ 673024b246eSLinus Torvalds subq $16,1,$16 \n\ 674024b246eSLinus Torvalds \n\ 675024b246eSLinus Torvalds stq $3,56($17) \n\ 676024b246eSLinus Torvalds addq $20,64,$20 \n\ 677024b246eSLinus Torvalds addq $19,64,$19 \n\ 678024b246eSLinus Torvalds addq $18,64,$18 \n\ 679024b246eSLinus Torvalds \n\ 680024b246eSLinus Torvalds addq $17,64,$17 \n\ 681024b246eSLinus Torvalds bgt $16,4b \n\ 682024b246eSLinus Torvalds ret \n\ 683024b246eSLinus Torvalds .end xor_alpha_prefetch_4 \n\ 684024b246eSLinus Torvalds \n\ 685024b246eSLinus Torvalds .align 3 \n\ 686024b246eSLinus Torvalds .ent xor_alpha_prefetch_5 \n\ 687024b246eSLinus Torvalds xor_alpha_prefetch_5: \n\ 688024b246eSLinus Torvalds .prologue 0 \n\ 689024b246eSLinus Torvalds srl $16, 6, $16 \n\ 690024b246eSLinus Torvalds \n\ 691024b246eSLinus Torvalds ldq $31, 0($17) \n\ 692024b246eSLinus Torvalds ldq $31, 0($18) \n\ 693024b246eSLinus Torvalds ldq $31, 0($19) \n\ 694024b246eSLinus Torvalds ldq $31, 0($20) \n\ 695024b246eSLinus Torvalds ldq $31, 0($21) \n\ 696024b246eSLinus Torvalds \n\ 697024b246eSLinus Torvalds ldq $31, 64($17) \n\ 698024b246eSLinus Torvalds ldq $31, 64($18) \n\ 699024b246eSLinus Torvalds ldq $31, 64($19) \n\ 700024b246eSLinus Torvalds ldq $31, 64($20) \n\ 701024b246eSLinus Torvalds ldq $31, 64($21) \n\ 702024b246eSLinus Torvalds \n\ 703024b246eSLinus Torvalds ldq $31, 128($17) \n\ 704024b246eSLinus Torvalds ldq $31, 128($18) \n\ 705024b246eSLinus Torvalds ldq $31, 128($19) \n\ 706024b246eSLinus Torvalds ldq $31, 128($20) \n\ 707024b246eSLinus Torvalds ldq $31, 128($21) \n\ 708024b246eSLinus Torvalds \n\ 709024b246eSLinus Torvalds ldq $31, 192($17) \n\ 710024b246eSLinus Torvalds ldq $31, 192($18) \n\ 711024b246eSLinus Torvalds ldq $31, 192($19) \n\ 712024b246eSLinus Torvalds ldq $31, 192($20) \n\ 713024b246eSLinus Torvalds ldq $31, 192($21) \n\ 714024b246eSLinus Torvalds .align 4 \n\ 715024b246eSLinus Torvalds 5: \n\ 716024b246eSLinus Torvalds ldq $0,0($17) \n\ 717024b246eSLinus Torvalds ldq $1,0($18) \n\ 718024b246eSLinus Torvalds ldq $2,0($19) \n\ 719024b246eSLinus Torvalds ldq $3,0($20) \n\ 720024b246eSLinus Torvalds \n\ 721024b246eSLinus Torvalds ldq $4,0($21) \n\ 722024b246eSLinus Torvalds ldq $5,8($17) \n\ 723024b246eSLinus Torvalds ldq $6,8($18) \n\ 724024b246eSLinus Torvalds ldq $7,8($19) \n\ 725024b246eSLinus Torvalds \n\ 726024b246eSLinus Torvalds ldq $22,8($20) \n\ 727024b246eSLinus Torvalds ldq $23,8($21) \n\ 728024b246eSLinus Torvalds ldq $24,16($17) \n\ 729024b246eSLinus Torvalds ldq $25,16($18) \n\ 730024b246eSLinus Torvalds \n\ 731024b246eSLinus Torvalds ldq $27,16($19) \n\ 732024b246eSLinus Torvalds xor $0,$1,$1 # 6 cycles from $1 load \n\ 733024b246eSLinus Torvalds ldq $28,16($20) \n\ 734024b246eSLinus Torvalds xor $2,$3,$3 # 6 cycles from $3 load \n\ 735024b246eSLinus Torvalds \n\ 736024b246eSLinus Torvalds ldq $0,16($21) \n\ 737024b246eSLinus Torvalds xor $1,$3,$3 \n\ 738024b246eSLinus Torvalds ldq $1,24($17) \n\ 739024b246eSLinus Torvalds xor $3,$4,$4 # 7 cycles from $4 load \n\ 740024b246eSLinus Torvalds \n\ 741024b246eSLinus Torvalds stq $4,0($17) \n\ 742024b246eSLinus Torvalds xor $5,$6,$6 # 7 cycles from $6 load \n\ 743024b246eSLinus Torvalds xor $7,$22,$22 # 7 cycles from $22 load \n\ 744024b246eSLinus Torvalds xor $6,$23,$23 # 7 cycles from $23 load \n\ 745024b246eSLinus Torvalds \n\ 746024b246eSLinus Torvalds ldq $2,24($18) \n\ 747024b246eSLinus Torvalds xor $22,$23,$23 \n\ 748024b246eSLinus Torvalds ldq $3,24($19) \n\ 749024b246eSLinus Torvalds xor $24,$25,$25 # 8 cycles from $25 load \n\ 750024b246eSLinus Torvalds \n\ 751024b246eSLinus Torvalds stq $23,8($17) \n\ 752024b246eSLinus Torvalds xor $25,$27,$27 # 8 cycles from $27 load \n\ 753024b246eSLinus Torvalds ldq $4,24($20) \n\ 754024b246eSLinus Torvalds xor $28,$0,$0 # 7 cycles from $0 load \n\ 755024b246eSLinus Torvalds \n\ 756024b246eSLinus Torvalds ldq $5,24($21) \n\ 757024b246eSLinus Torvalds xor $27,$0,$0 \n\ 758024b246eSLinus Torvalds ldq $6,32($17) \n\ 759024b246eSLinus Torvalds ldq $7,32($18) \n\ 760024b246eSLinus Torvalds \n\ 761024b246eSLinus Torvalds stq $0,16($17) \n\ 762024b246eSLinus Torvalds xor $1,$2,$2 # 6 cycles from $2 load \n\ 763024b246eSLinus Torvalds ldq $22,32($19) \n\ 764024b246eSLinus Torvalds xor $3,$4,$4 # 4 cycles from $4 load \n\ 765024b246eSLinus Torvalds \n\ 766024b246eSLinus Torvalds ldq $23,32($20) \n\ 767024b246eSLinus Torvalds xor $2,$4,$4 \n\ 768024b246eSLinus Torvalds ldq $24,32($21) \n\ 769024b246eSLinus Torvalds ldq $25,40($17) \n\ 770024b246eSLinus Torvalds \n\ 771024b246eSLinus Torvalds ldq $27,40($18) \n\ 772024b246eSLinus Torvalds ldq $28,40($19) \n\ 773024b246eSLinus Torvalds ldq $0,40($20) \n\ 774024b246eSLinus Torvalds xor $4,$5,$5 # 7 cycles from $5 load \n\ 775024b246eSLinus Torvalds \n\ 776024b246eSLinus Torvalds stq $5,24($17) \n\ 777024b246eSLinus Torvalds xor $6,$7,$7 # 7 cycles from $7 load \n\ 778024b246eSLinus Torvalds ldq $1,40($21) \n\ 779024b246eSLinus Torvalds ldq $2,48($17) \n\ 780024b246eSLinus Torvalds \n\ 781024b246eSLinus Torvalds ldq $3,48($18) \n\ 782024b246eSLinus Torvalds xor $7,$22,$22 # 7 cycles from $22 load \n\ 783024b246eSLinus Torvalds ldq $4,48($19) \n\ 784024b246eSLinus Torvalds xor $23,$24,$24 # 6 cycles from $24 load \n\ 785024b246eSLinus Torvalds \n\ 786024b246eSLinus Torvalds ldq $5,48($20) \n\ 787024b246eSLinus Torvalds xor $22,$24,$24 \n\ 788024b246eSLinus Torvalds ldq $6,48($21) \n\ 789024b246eSLinus Torvalds xor $25,$27,$27 # 7 cycles from $27 load \n\ 790024b246eSLinus Torvalds \n\ 791024b246eSLinus Torvalds stq $24,32($17) \n\ 792024b246eSLinus Torvalds xor $27,$28,$28 # 8 cycles from $28 load \n\ 793024b246eSLinus Torvalds ldq $7,56($17) \n\ 794024b246eSLinus Torvalds xor $0,$1,$1 # 6 cycles from $1 load \n\ 795024b246eSLinus Torvalds \n\ 796024b246eSLinus Torvalds ldq $22,56($18) \n\ 797024b246eSLinus Torvalds ldq $23,56($19) \n\ 798024b246eSLinus Torvalds ldq $24,56($20) \n\ 799024b246eSLinus Torvalds ldq $25,56($21) \n\ 800024b246eSLinus Torvalds \n\ 801024b246eSLinus Torvalds ldq $31,256($17) \n\ 802024b246eSLinus Torvalds xor $28,$1,$1 \n\ 803024b246eSLinus Torvalds ldq $31,256($18) \n\ 804024b246eSLinus Torvalds xor $2,$3,$3 # 9 cycles from $3 load \n\ 805024b246eSLinus Torvalds \n\ 806024b246eSLinus Torvalds ldq $31,256($19) \n\ 807024b246eSLinus Torvalds xor $3,$4,$4 # 9 cycles from $4 load \n\ 808024b246eSLinus Torvalds ldq $31,256($20) \n\ 809024b246eSLinus Torvalds xor $5,$6,$6 # 8 cycles from $6 load \n\ 810024b246eSLinus Torvalds \n\ 811024b246eSLinus Torvalds stq $1,40($17) \n\ 812024b246eSLinus Torvalds xor $4,$6,$6 \n\ 813024b246eSLinus Torvalds xor $7,$22,$22 # 7 cycles from $22 load \n\ 814024b246eSLinus Torvalds xor $23,$24,$24 # 6 cycles from $24 load \n\ 815024b246eSLinus Torvalds \n\ 816024b246eSLinus Torvalds stq $6,48($17) \n\ 817024b246eSLinus Torvalds xor $22,$24,$24 \n\ 818024b246eSLinus Torvalds ldq $31,256($21) \n\ 819024b246eSLinus Torvalds xor $24,$25,$25 # 8 cycles from $25 load \n\ 820024b246eSLinus Torvalds \n\ 821024b246eSLinus Torvalds stq $25,56($17) \n\ 822024b246eSLinus Torvalds subq $16,1,$16 \n\ 823024b246eSLinus Torvalds addq $21,64,$21 \n\ 824024b246eSLinus Torvalds addq $20,64,$20 \n\ 825024b246eSLinus Torvalds \n\ 826024b246eSLinus Torvalds addq $19,64,$19 \n\ 827024b246eSLinus Torvalds addq $18,64,$18 \n\ 828024b246eSLinus Torvalds addq $17,64,$17 \n\ 829024b246eSLinus Torvalds bgt $16,5b \n\ 830024b246eSLinus Torvalds \n\ 831024b246eSLinus Torvalds ret \n\ 832024b246eSLinus Torvalds .end xor_alpha_prefetch_5 \n\ 833024b246eSLinus Torvalds "); 834024b246eSLinus Torvalds 835024b246eSLinus Torvalds static struct xor_block_template xor_block_alpha = { 836024b246eSLinus Torvalds .name = "alpha", 837024b246eSLinus Torvalds .do_2 = xor_alpha_2, 838024b246eSLinus Torvalds .do_3 = xor_alpha_3, 839024b246eSLinus Torvalds .do_4 = xor_alpha_4, 840024b246eSLinus Torvalds .do_5 = xor_alpha_5, 841024b246eSLinus Torvalds }; 842024b246eSLinus Torvalds 843024b246eSLinus Torvalds static struct xor_block_template xor_block_alpha_prefetch = { 844024b246eSLinus Torvalds .name = "alpha prefetch", 845024b246eSLinus Torvalds .do_2 = xor_alpha_prefetch_2, 846024b246eSLinus Torvalds .do_3 = xor_alpha_prefetch_3, 847024b246eSLinus Torvalds .do_4 = xor_alpha_prefetch_4, 848024b246eSLinus Torvalds .do_5 = xor_alpha_prefetch_5, 849024b246eSLinus Torvalds }; 850024b246eSLinus Torvalds 851024b246eSLinus Torvalds /* For grins, also test the generic routines. */ 852024b246eSLinus Torvalds #include <asm-generic/xor.h> 853024b246eSLinus Torvalds 854024b246eSLinus Torvalds #undef XOR_TRY_TEMPLATES 855024b246eSLinus Torvalds #define XOR_TRY_TEMPLATES \ 856024b246eSLinus Torvalds do { \ 857024b246eSLinus Torvalds xor_speed(&xor_block_8regs); \ 858024b246eSLinus Torvalds xor_speed(&xor_block_32regs); \ 859024b246eSLinus Torvalds xor_speed(&xor_block_alpha); \ 860024b246eSLinus Torvalds xor_speed(&xor_block_alpha_prefetch); \ 861024b246eSLinus Torvalds } while (0) 862024b246eSLinus Torvalds 863024b246eSLinus Torvalds /* Force the use of alpha_prefetch if EV6, as it is significantly 864024b246eSLinus Torvalds faster in the cold cache case. */ 865024b246eSLinus Torvalds #define XOR_SELECT_TEMPLATE(FASTEST) \ 866024b246eSLinus Torvalds (implver() == IMPLVER_EV6 ? &xor_block_alpha_prefetch : FASTEST) 867