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Searched +full:208 +full:mhz (Results 1 – 25 of 63) sorted by relevance

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/linux/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnxp,s32g2-siul2-pinctrl.yaml80 description: Supported slew rate based on Fmax values (MHz)
81 enum: [83, 133, 150, 166, 208]
113 slew-rate = <208>;
119 slew-rate = <208>;
/linux/drivers/clk/renesas/
H A Dr8a7792-cpg-mssr.c92 DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
165 * 14 13 19 (MHz) *1 *2
183 { 1, 208, 106, 200 },
184 { 1, 208, 88, 200 },
189 { 2, 208, 106, 200 },
190 { 2, 208, 88, 200 },
H A Dr8a7791-cpg-mssr.c112 DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
220 * 14 13 19 (MHz) *1 *1
237 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
238 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
H A Dr8a7790-cpg-mssr.c119 DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
222 * 14 13 19 (MHz) *1 *1
239 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
240 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
H A Dr8a7742-cpg-mssr.c108 DEF_MOD("msiof1", 208, R8A7742_CLK_MP),
213 * 14 13 19 (MHz) *1 *1
232 { 1, 208, 106, },
233 { 1, 208, 88, },
238 { 2, 208, 106, },
239 { 2, 208, 88, },
H A Dr8a7743-cpg-mssr.c102 DEF_MOD("msiof1", 208, R8A7743_CLK_MP),
207 * 14 13 19 (MHz) *1 *1
226 { 1, 208, 106, },
227 { 1, 208, 88, },
232 { 2, 208, 106, },
233 { 2, 208, 88, },
H A Dr8a7745-cpg-mssr.c100 DEF_MOD("msiof1", 208, R8A7745_CLK_MP),
191 * 14 13 19 (MHz) *1 *2
206 { 1, 208, 88, 200 },
209 { 2, 208, 88, 200 },
H A Dr8a7794-cpg-mssr.c107 DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
201 * 14 13 19 (MHz) *1 *2
214 { 1, 208, 88, 200 },
217 { 2, 208, 88, 200 },
H A Dr8a77470-cpg-mssr.c90 DEF_MOD("msiof1", 208, R8A77470_CLK_MP),
174 * 14 13 (MHz) *1 *2
H A Dr8a77995-cpg-mssr.c132 DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
211 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
H A Dr8a77980-cpg-mssr.c125 DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
212 * 14 13 (MHz)
H A Dr8a774c0-cpg-mssr.c145 DEF_MOD("msiof3", 208, R8A774C0_CLK_MSO),
261 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
/linux/samples/bpf/
H A Dcpustat_kern.c16 * 208MHz, 432MHz, 729MHz, 960MHz, 1200MHz
H A Dcpustat_user.c149 * To solve this issue, below code forces to set 'scaling_max_freq' to 208MHz
/linux/sound/soc/codecs/
H A Des83xx-dsm-common.h283 #define ADC_ALC_ATKTIME_000208_US 0x01 //time = 208us
376 * 0 - 19.2MHz
377 * 1 - 24MHz
378 * 2 - 12.288MHz
379 * F - Default for 19.2MHz
382 * 0 - 4.8MHz
383 * 1 - 2.4MHz
384 * 2 - 2.304MHz
385 * 3 - 3.072MHz
386 * 4 - 4.096MHz
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller-common.yaml85 - for eMMC, the maximum supported frequency is 200MHz,
87 frequency of 208MHz,
89 384MHz.
/linux/arch/arm/boot/dts/ti/omap/
H A Dam5729-beagleboneai.dts422 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
555 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
556 /* HS: High speed up to 50 MHz (3.3 V signaling). */
557 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
558 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
559 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
560 /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
561 /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
/linux/drivers/comedi/drivers/
H A Dquatech_daqp_cs.c13 * ftp://ftp.quatech.com/Manuals/daqp-208.pdf
15 * This manual is for both the DAQP-208 and the DAQP-308.
38 * Devices: [Quatech] DAQP-208 (daqp), DAQP-308
347 * for programming the device. We always use the DAQP's 5 MHz clock,
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7790.dtsi82 capacity-dmips-mhz = <1024>;
104 capacity-dmips-mhz = <1024>;
126 capacity-dmips-mhz = <1024>;
148 capacity-dmips-mhz = <1024>;
170 capacity-dmips-mhz = <539>;
182 capacity-dmips-mhz = <539>;
194 capacity-dmips-mhz = <539>;
206 capacity-dmips-mhz = <539>;
794 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1071 clocks = <&cpg CPG_MOD 208>;
[all …]
/linux/drivers/net/wireless/ath/wcn36xx/
H A Dhal.h362 WCN36XX_HAL_UPDATE_CHANNEL_LIST_REQ = 208,
408 /* 20MHz IF bandwidth centered on IF carrier */
411 /* 40MHz IF bandwidth with lower 20MHz supporting the primary channel */
414 /* 40MHz IF bandwidth centered on IF carrier */
417 /* 40MHz IF bandwidth with higher 20MHz supporting the primary ch */
420 /* 20/40MHZ offset LOW 40/80MHZ offset CENTERED */
423 /* 20/40MHZ offset CENTERED 40/80MHZ offset CENTERED */
426 /* 20/40MHZ offset HIGH 40/80MHZ offset CENTERED */
429 /* 20/40MHZ offset LOW 40/80MHZ offset LOW */
432 /* 20/40MHZ offset HIGH 40/80MHZ offset LOW */
[all …]
/linux/include/dt-bindings/clock/
H A Dtegra186-clock.h644 #define TEGRA186_CLK_AON_CPU_NIC 208
755 /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
757 /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
791 /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
866 /** Fixed frequency 960MHz PLL for USB and EAVB */
/linux/drivers/pci/hotplug/
H A Dcpqphp_core.c13 * Jan 12, 2003 - Added 66/100/133MHz PCI-X support,
64 #define CPQHPC_MODULE_MINOR 208
852 dbg("bus max supports 133MHz PCI-X\n"); in cpqhpc_probe()
857 dbg("bus max supports 100MHz PCI-X\n"); in cpqhpc_probe()
862 dbg("bus max supports 66MHz PCI-X\n"); in cpqhpc_probe()
867 dbg("bus max supports 66MHz PCI\n"); in cpqhpc_probe()
908 /* First 66 Mhz implementation */ in cpqhpc_probe()
919 /* First PCI-X implementation, 100MHz */ in cpqhpc_probe()
979 /* 133MHz PCI-X if bit 7 is 1 */ in cpqhpc_probe()
982 /* 100MHz PCI-X if bit 7 is 1 and bit 0 is 0, */ in cpqhpc_probe()
[all …]
/linux/drivers/media/dvb-frontends/
H A Dtda10086.c118 /* setup PLL (this assumes SACLK = 96MHz) */ in tda10086_init()
303 } else if (symbol_rate < SACLK / 10000 * 208) { in tda10086_set_symbol_rate()
700 .frequency_min_hz = 950 * MHz,
701 .frequency_max_hz = 2150 * MHz,

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