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Searched +full:208 +full:mhz (Results 1 – 25 of 103) sorted by relevance

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/linux/drivers/cpufreq/
H A Dpxa3xx-cpufreq.c88 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
89 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
90 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
91 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
96 OP(104, 8, 1, 104, 260, 78, 104, 3, 1000, 1100), /* 104MHz */
97 OP(208, 16, 1, 104, 260, 104, 156, 2, 1000, 1100), /* 208MHz */
98 OP(416, 16, 2, 156, 260, 104, 208, 2, 1100, 1200), /* 416MHz */
99 OP(624, 24, 2, 208, 260, 208, 312, 3, 1375, 1400), /* 624MHz */
100 OP(806, 31, 2, 208, 260, 208, 312, 3, 1400, 1400), /* 806MHz */
/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnxp,s32g2-siul2-pinctrl.yaml80 description: Supported slew rate based on Fmax values (MHz)
81 enum: [83, 133, 150, 166, 208]
113 slew-rate = <208>;
119 slew-rate = <208>;
/linux/drivers/clk/renesas/
H A Dr8a7792-cpg-mssr.c92 DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
165 * 14 13 19 (MHz) *1 *2
183 { 1, 208, 106, 200 },
184 { 1, 208, 88, 200 },
189 { 2, 208, 106, 200 },
190 { 2, 208, 88, 200 },
H A Dr8a7791-cpg-mssr.c112 DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
220 * 14 13 19 (MHz) *1 *1
237 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
238 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
H A Dr8a7790-cpg-mssr.c119 DEF_MOD("msiof1", 208, R8A7790_CLK_MP),
222 * 14 13 19 (MHz) *1 *1
239 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
240 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
H A Dr8a7742-cpg-mssr.c108 DEF_MOD("msiof1", 208, R8A7742_CLK_MP),
213 * 14 13 19 (MHz) *1 *1
232 { 1, 208, 106, },
233 { 1, 208, 88, },
238 { 2, 208, 106, },
239 { 2, 208, 88, },
H A Dr8a7743-cpg-mssr.c102 DEF_MOD("msiof1", 208, R8A7743_CLK_MP),
207 * 14 13 19 (MHz) *1 *1
226 { 1, 208, 106, },
227 { 1, 208, 88, },
232 { 2, 208, 106, },
233 { 2, 208, 88, },
H A Dr8a7745-cpg-mssr.c100 DEF_MOD("msiof1", 208, R8A7745_CLK_MP),
191 * 14 13 19 (MHz) *1 *2
206 { 1, 208, 88, 200 },
209 { 2, 208, 88, 200 },
H A Dr8a7794-cpg-mssr.c107 DEF_MOD("msiof1", 208, R8A7794_CLK_MP),
201 * 14 13 19 (MHz) *1 *2
214 { 1, 208, 88, 200 },
217 { 2, 208, 88, 200 },
H A Dr8a77470-cpg-mssr.c90 DEF_MOD("msiof1", 208, R8A77470_CLK_MP),
174 * 14 13 (MHz) *1 *2
H A Dr8a77995-cpg-mssr.c132 DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
211 * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
H A Dr8a77970-cpg-mssr.c120 DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
178 * 14 13 19 (MHz)
H A Dr8a77980-cpg-mssr.c125 DEF_MOD("msiof3", 208, R8A77980_CLK_MSO),
212 * 14 13 (MHz)
/linux/samples/bpf/
H A Dcpustat_kern.c16 * 208MHz, 432MHz, 729MHz, 960MHz, 1200MHz
H A Dcpustat_user.c149 * To solve this issue, below code forces to set 'scaling_max_freq' to 208MHz
/linux/drivers/video/fbdev/
H A Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
68 /* 832x624, 75Hz, Non-Interlaced (57.6 MHz dotclock) */
69 "mac13", 75, 832, 624, 17362, 208, 48, 39, 1, 64, 3,
[all …]
/linux/sound/soc/codecs/
H A Des83xx-dsm-common.h283 #define ADC_ALC_ATKTIME_000208_US 0x01 //time = 208us
376 * 0 - 19.2MHz
377 * 1 - 24MHz
378 * 2 - 12.288MHz
379 * F - Default for 19.2MHz
382 * 0 - 4.8MHz
383 * 1 - 2.4MHz
384 * 2 - 2.304MHz
385 * 3 - 3.072MHz
386 * 4 - 4.096MHz
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml93 - for eMMC, the maximum supported frequency is 200MHz,
95 frequency of 208MHz,
97 384MHz.
/linux/arch/arm/boot/dts/ti/omap/
H A Dam5729-beagleboneai.dts422 st,adc-freq = <1>; /* 3.25 MHz ADC clock speed */
555 /* DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3 V signaling). */
556 /* HS: High speed up to 50 MHz (3.3 V signaling). */
557 /* SDR12: SDR up to 25 MHz (1.8 V signaling). */
558 /* SDR25: SDR up to 50 MHz (1.8 V signaling). */
559 /* SDR50: SDR up to 100 MHz (1.8 V signaling). */
560 /* SDR104: SDR up to 208 MHz (1.8 V signaling) */
561 /* DDR50: DDR up to 50 MHz (1.8 V signaling). */
/linux/arch/mips/boot/dts/ingenic/
H A Dgcw0.dts124 144 160 176 192 208 224 240 255>;
444 * We use a rate of 432 MHz, which is the least common multiple of
445 * 27 MHz (required by TV encoder) and 48 MHz (required by USB host).
478 * 750 kHz for the system timer and clocksource, 12 MHz for the OST,
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx93-mipi-dsi.c73 #define MHZ(x) ((x) * 1000000UL) macro
75 #define REF_CLK_RATE_MAX MHZ(64)
76 #define REF_CLK_RATE_MIN MHZ(2)
77 #define FOUT_MAX MHZ(1250)
78 #define FOUT_MIN MHZ(40)
79 #define FVCO_DIV_FACTOR MHZ(80)
249 /* limitation: 2MHz <= Fin / N <= 8MHz */ in dphy_pll_get_configure_from_opts()
250 min_n = DIV_ROUND_UP_ULL((u64)fin, MHZ(8)); in dphy_pll_get_configure_from_opts()
251 max_n = DIV_ROUND_DOWN_ULL((u64)fin, MHZ(2)); in dphy_pll_get_configure_from_opts()
317 return (clk_get_rate(dsi->clk_cfg) / MHZ(1) - 17) * 4; in dphy_pll_get_cfgclkrange()
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-of-at91.c207 * maximum sd clock value is 120 MHz instead of 208 MHz. For that in sdhci_at91_set_clks_presets()
/linux/Documentation/devicetree/bindings/timer/
H A Drenesas,rz-mtu3.yaml20 - Operating frequency Up to 100 MHz
283 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
/linux/drivers/comedi/drivers/
H A Dquatech_daqp_cs.c13 * ftp://ftp.quatech.com/Manuals/daqp-208.pdf
15 * This manual is for both the DAQP-208 and the DAQP-308.
38 * Devices: [Quatech] DAQP-208 (daqp), DAQP-308
347 * for programming the device. We always use the DAQP's 5 MHz clock,

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