1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/mmc-controller-common.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MMC Controller & Slots Common Properties 8 9maintainers: 10 - Ulf Hansson <ulf.hansson@linaro.org> 11 12description: 13 These properties are common to multiple MMC host controllers and the 14 possible slots or ports for multi-slot controllers. 15 16properties: 17 "#address-cells": 18 const: 1 19 description: 20 The cell is the SDIO function number if a function subnode is used. 21 22 "#size-cells": 23 const: 0 24 25 # Card Detection. 26 # If none of these properties are supplied, the host native card 27 # detect will be used. Only one of them should be provided. 28 29 broken-cd: 30 $ref: /schemas/types.yaml#/definitions/flag 31 description: 32 There is no card detection available; polling must be used. 33 34 cd-gpios: 35 maxItems: 1 36 description: 37 The card detection will be done using the GPIO provided. 38 39 non-removable: 40 $ref: /schemas/types.yaml#/definitions/flag 41 description: 42 Non-removable slot (like eMMC); assume always present. 43 44 # *NOTE* on CD and WP polarity. To use common for all SD/MMC host 45 # controllers line polarity properties, we have to fix the meaning 46 # of the "normal" and "inverted" line levels. We choose to follow 47 # the SDHCI standard, which specifies both those lines as "active 48 # low." Therefore, using the "cd-inverted" property means, that the 49 # CD line is active high, i.e. it is high, when a card is 50 # inserted. Similar logic applies to the "wp-inverted" property. 51 # 52 # CD and WP lines can be implemented on the hardware in one of two 53 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or 54 # as dedicated pins. Polarity of dedicated pins can be specified, 55 # using *-inverted properties. GPIO polarity can also be specified 56 # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the 57 # latter case. We choose to use the XOR logic for GPIO CD and WP 58 # lines. This means, the two properties are "superimposed," for 59 # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the 60 # respective *-inverted property property results in a 61 # double-inversion and actually means the "normal" line polarity is 62 # in effect. 63 wp-inverted: 64 $ref: /schemas/types.yaml#/definitions/flag 65 description: 66 The Write Protect line polarity is inverted. 67 68 cd-inverted: 69 $ref: /schemas/types.yaml#/definitions/flag 70 description: 71 The CD line polarity is inverted. 72 73 # Other properties 74 75 bus-width: 76 description: 77 Number of data lines. 78 $ref: /schemas/types.yaml#/definitions/uint32 79 enum: [1, 4, 8] 80 default: 1 81 82 max-frequency: 83 description: | 84 Maximum operating frequency of the bus: 85 - for eMMC, the maximum supported frequency is 200MHz, 86 - for SD/SDIO cards the SDR104 mode has a max supported 87 frequency of 208MHz, 88 - some mmc host controllers do support a max frequency upto 89 384MHz. 90 So, lets keep the maximum supported value here. 91 92 $ref: /schemas/types.yaml#/definitions/uint32 93 minimum: 400000 94 maximum: 384000000 95 96 disable-wp: 97 $ref: /schemas/types.yaml#/definitions/flag 98 description: 99 When set, no physical write-protect line is present. This 100 property should only be specified when the controller has a 101 dedicated write-protect detection logic. If a GPIO is always used 102 for the write-protect detection logic, it is sufficient to not 103 specify the wp-gpios property in the absence of a write-protect 104 line. Not used in combination with eMMC or SDIO. 105 106 wp-gpios: 107 maxItems: 1 108 description: 109 GPIO to use for the write-protect detection. 110 111 cd-debounce-delay-ms: 112 description: 113 Set delay time before detecting card after card insert 114 interrupt. 115 116 no-1-8-v: 117 $ref: /schemas/types.yaml#/definitions/flag 118 description: 119 When specified, denotes that 1.8V card voltage is not supported 120 on this system, even if the controller claims it. 121 122 cap-sd-highspeed: 123 $ref: /schemas/types.yaml#/definitions/flag 124 description: 125 SD high-speed timing is supported. 126 127 cap-mmc-highspeed: 128 $ref: /schemas/types.yaml#/definitions/flag 129 description: 130 MMC high-speed timing is supported. 131 132 sd-uhs-sdr12: 133 $ref: /schemas/types.yaml#/definitions/flag 134 description: 135 SD UHS SDR12 speed is supported. 136 137 sd-uhs-sdr25: 138 $ref: /schemas/types.yaml#/definitions/flag 139 description: 140 SD UHS SDR25 speed is supported. 141 142 sd-uhs-sdr50: 143 $ref: /schemas/types.yaml#/definitions/flag 144 description: 145 SD UHS SDR50 speed is supported. 146 147 sd-uhs-sdr104: 148 $ref: /schemas/types.yaml#/definitions/flag 149 description: 150 SD UHS SDR104 speed is supported. 151 152 sd-uhs-ddr50: 153 $ref: /schemas/types.yaml#/definitions/flag 154 description: 155 SD UHS DDR50 speed is supported. 156 157 cap-power-off-card: 158 $ref: /schemas/types.yaml#/definitions/flag 159 description: 160 Powering off the card is safe. 161 162 cap-mmc-hw-reset: 163 $ref: /schemas/types.yaml#/definitions/flag 164 description: 165 eMMC hardware reset is supported 166 167 cap-sdio-irq: 168 $ref: /schemas/types.yaml#/definitions/flag 169 description: 170 enable SDIO IRQ signalling on this interface 171 172 full-pwr-cycle: 173 $ref: /schemas/types.yaml#/definitions/flag 174 description: 175 Full power cycle of the card is supported. 176 177 full-pwr-cycle-in-suspend: 178 $ref: /schemas/types.yaml#/definitions/flag 179 description: 180 Full power cycle of the card in suspend is supported. 181 182 mmc-ddr-1_2v: 183 $ref: /schemas/types.yaml#/definitions/flag 184 description: 185 eMMC high-speed DDR mode (1.2V I/O) is supported. 186 187 mmc-ddr-1_8v: 188 $ref: /schemas/types.yaml#/definitions/flag 189 description: 190 eMMC high-speed DDR mode (1.8V I/O) is supported. 191 192 mmc-ddr-3_3v: 193 $ref: /schemas/types.yaml#/definitions/flag 194 description: 195 eMMC high-speed DDR mode (3.3V I/O) is supported. 196 197 mmc-hs200-1_2v: 198 $ref: /schemas/types.yaml#/definitions/flag 199 description: 200 eMMC HS200 mode (1.2V I/O) is supported. 201 202 mmc-hs200-1_8v: 203 $ref: /schemas/types.yaml#/definitions/flag 204 description: 205 eMMC HS200 mode (1.8V I/O) is supported. 206 207 mmc-hs400-1_2v: 208 $ref: /schemas/types.yaml#/definitions/flag 209 description: 210 eMMC HS400 mode (1.2V I/O) is supported. 211 212 mmc-hs400-1_8v: 213 $ref: /schemas/types.yaml#/definitions/flag 214 description: 215 eMMC HS400 mode (1.8V I/O) is supported. 216 217 mmc-hs400-enhanced-strobe: 218 $ref: /schemas/types.yaml#/definitions/flag 219 description: 220 eMMC HS400 enhanced strobe mode is supported 221 222 no-mmc-hs400: 223 $ref: /schemas/types.yaml#/definitions/flag 224 description: 225 All eMMC HS400 modes are not supported. 226 227 dsr: 228 description: 229 Value the card Driver Stage Register (DSR) should be programmed 230 with. 231 $ref: /schemas/types.yaml#/definitions/uint32 232 minimum: 0 233 maximum: 0xffff 234 235 no-sdio: 236 $ref: /schemas/types.yaml#/definitions/flag 237 description: 238 Controller is limited to send SDIO commands during 239 initialization. 240 241 no-sd: 242 $ref: /schemas/types.yaml#/definitions/flag 243 description: 244 Controller is limited to send SD commands during initialization. 245 246 no-mmc: 247 $ref: /schemas/types.yaml#/definitions/flag 248 description: 249 Controller is limited to send MMC commands during 250 initialization. 251 252 fixed-emmc-driver-type: 253 description: 254 For non-removable eMMC, enforce this driver type. The value is 255 the driver type as specified in the eMMC specification (table 256 206 in spec version 5.1) 257 $ref: /schemas/types.yaml#/definitions/uint32 258 minimum: 0 259 maximum: 4 260 261 post-power-on-delay-ms: 262 description: 263 It was invented for MMC pwrseq-simple which could be referred to 264 mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay 265 waiting for I/O signalling and card power supply to be stable, 266 regardless of whether pwrseq-simple is used. Default to 10ms if 267 no available. 268 default: 10 269 270 supports-cqe: 271 $ref: /schemas/types.yaml#/definitions/flag 272 description: 273 The presence of this property indicates that the corresponding 274 MMC host controller supports HW command queue feature. 275 276 disable-cqe-dcmd: 277 $ref: /schemas/types.yaml#/definitions/flag 278 description: 279 The presence of this property indicates that the MMC 280 controller\'s command queue engine (CQE) does not support direct 281 commands (DCMDs). 282 283 keep-power-in-suspend: 284 $ref: /schemas/types.yaml#/definitions/flag 285 description: 286 SDIO only. Preserves card power during a suspend/resume cycle. 287 288 wakeup-source: 289 $ref: /schemas/types.yaml#/definitions/flag 290 description: 291 SDIO only. Enables wake up of host system on SDIO IRQ assertion. 292 293 vmmc-supply: 294 description: 295 Supply for the card power 296 297 vqmmc-supply: 298 description: 299 Supply for the bus IO line power, such as a level shifter. 300 If the level shifter is controlled by a GPIO line, this shall 301 be modeled as a "regulator-fixed" with a GPIO line for 302 switching the level shifter on/off. 303 304 mmc-pwrseq: 305 $ref: /schemas/types.yaml#/definitions/phandle 306 description: 307 System-on-Chip designs may specify a specific MMC power 308 sequence. To successfully detect an (e)MMC/SD/SDIO card, that 309 power sequence must be maintained while initializing the card. 310 311patternProperties: 312 "^.*@[0-9]+$": 313 type: object 314 description: | 315 On embedded systems the cards connected to a host may need 316 additional properties. These can be specified in subnodes to the 317 host controller node. The subnodes are identified by the 318 standard \'reg\' property. Which information exactly can be 319 specified depends on the bindings for the SDIO function driver 320 for the subnode, as specified by the compatible string. 321 322 properties: 323 compatible: 324 description: 325 Name of SDIO function following generic names recommended 326 practice 327 328 reg: 329 items: 330 - minimum: 0 331 maximum: 7 332 description: 333 Must contain the SDIO function number of the function this 334 subnode describes. A value of 0 denotes the memory SD 335 function, values from 1 to 7 denote the SDIO functions. 336 337 required: 338 - reg 339 340 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$": 341 $ref: /schemas/types.yaml#/definitions/uint32-array 342 343 minItems: 2 344 maxItems: 2 345 items: 346 minimum: 0 347 maximum: 359 348 description: 349 Set the clock (phase) delays which are to be configured in the 350 controller while switching to particular speed mode. These values 351 are in pair of degrees. 352 353dependencies: 354 cd-debounce-delay-ms: [ cd-gpios ] 355 fixed-emmc-driver-type: [ non-removable ] 356 357additionalProperties: true 358