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/linux/drivers/net/dsa/
H A Dmv88e6060.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
17 #define PORT_STATUS_PAUSE_EN BIT(15)
18 #define PORT_STATUS_MY_PAUSE BIT(14)
20 #define PORT_STATUS_RESOLVED BIT(13)
21 #define PORT_STATUS_LINK BIT(12)
22 #define PORT_STATUS_PORTMODE BIT(11)
23 #define PORT_STATUS_PHYMODE BIT(10)
24 #define PORT_STATUS_DUPLEX BIT(9)
25 #define PORT_STATUS_SPEED BIT(8)
[all …]
/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dp_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2019-2022 MediaTek Inc.
11 #define MTK_DP_HPD_DISCONNECT BIT(1)
12 #define MTK_DP_HPD_CONNECT BIT(2)
13 #define MTK_DP_HPD_INTERRUPT BIT(3)
21 #define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
22 #define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
23 #define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
24 #define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
25 #define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
[all …]
/linux/drivers/pmdomain/mediatek/
H A Dmt6893-pm-domains.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/power/mediatek,mt6893-power.h>
12 #include "mtk-pm-domains.h"
27 #define MT6893_TOP_AXI_PROT_EN_2_MFG1_STEP4 BIT(7)
29 #define MT6893_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 BIT(24)
30 #define MT6893_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 BIT(25)
31 #define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 BIT(6)
32 #define MT6893_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 BIT(7)
33 #define MT6893_TOP_AXI_PROT_EN_MM_VENC0_STEP1 BIT(26)
34 #define MT6893_TOP_AXI_PROT_EN_MM_2_VENC0_STEP2 BIT(0)
[all …]
H A Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
26 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
27 #define MTK_SCPD_FWAIT_SRAM BIT(1)
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
[all …]
/linux/include/soc/mscc/
H A Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
H A Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
[all …]
/linux/sound/firewire/bebob/
H A Dbebob_command.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bebob_command.c - driver for BeBoB based devices
5 * Copyright (c) 2013-2014 Takashi Sakamoto
16 buf = kzalloc(12, GFP_KERNEL); in avc_audio_set_selector()
18 return -ENOMEM; in avc_audio_set_selector()
30 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_audio_set_selector()
31 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_set_selector()
32 BIT(6) | BIT(7) | BIT(8)); in avc_audio_set_selector()
36 err = -EIO; in avc_audio_set_selector()
38 err = -ENOSYS; in avc_audio_set_selector()
[all …]
/linux/sound/soc/codecs/
H A Dmt6357.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt6357.h -- mt6357 ALSA SoC audio codec driver
14 /* Reg bit defines */
16 #define MT6357_GPIO8_DIR_MASK BIT(8)
18 #define MT6357_GPIO8_DIR_OUTPUT BIT(8)
19 #define MT6357_GPIO9_DIR_MASK BIT(9)
21 #define MT6357_GPIO9_DIR_OUTPUT BIT(9)
22 #define MT6357_GPIO10_DIR_MASK BIT(10)
24 #define MT6357_GPIO10_DIR_OUTPUT BIT(10)
25 #define MT6357_GPIO11_DIR_MASK BIT(11)
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
/linux/drivers/clk/renesas/
H A Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
197 BUS_MSTOP(5, BIT(9))),
199 BUS_MSTOP(3, BIT(2))),
201 BUS_MSTOP(3, BIT(3))),
203 BUS_MSTOP(10, BIT(11))),
205 BUS_MSTOP(10, BIT(12))),
209 BUS_MSTOP(3, BIT(5))),
[all …]
H A Dr9a09g047-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
190 BUS_MSTOP(5, BIT(9))),
192 BUS_MSTOP(3, BIT(2))),
194 BUS_MSTOP(3, BIT(3))),
196 BUS_MSTOP(10, BIT(11))),
198 BUS_MSTOP(10, BIT(12))),
202 BUS_MSTOP(3, BIT(5))),
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8821cu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8821cs_efuse_parsing()
50 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_read_efuse()
51 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
[all …]
/linux/drivers/comedi/drivers/
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/linux/drivers/gpu/drm/tve200/
H A Dtve200_drm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2006-2008 Intel Corporation
28 /* Bits 2-31 are valid physical base addresses */
36 #define TVE200_INT_BUS_ERR BIT(7)
37 #define TVE200_INT_V_STATUS BIT(6) /* vertical blank */
38 #define TVE200_INT_V_NEXT_FRAME BIT(5)
39 #define TVE200_INT_U_NEXT_FRAME BIT(4)
40 #define TVE200_INT_Y_NEXT_FRAME BIT(3)
41 #define TVE200_INT_V_FIFO_UNDERRUN BIT(2)
42 #define TVE200_INT_U_FIFO_UNDERRUN BIT(1)
[all …]
/linux/include/linux/mfd/
H A Dwl1273-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/linux/mfd/wl1273-core.h
17 #define WL1273_FM_DRIVER_NAME "wl1273-fm"
28 #define WL1273_MOST_MODE_SET 12
125 #define WL1273_MODE_RX BIT(0)
126 #define WL1273_MODE_TX BIT(1)
127 #define WL1273_MODE_OFF BIT(2)
128 #define WL1273_MODE_SUSPENDED BIT(3)
130 #define WL1273_RADIO_CHILD BIT(0)
131 #define WL1273_CODEC_CHILD BIT(1)
[all …]
/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
24 WARN_ON(!FIELD_FIT(hvs->vc4->gen == VC4_GEN_6_C ? \
27 FIELD_PREP(hvs->vc4->gen == VC4_GEN_6_C ? \
32 #define VC6_GET_FIELD(word, field) FIELD_GET(hvs->vc4->gen == VC4_GEN_6_C ? \
49 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
50 # define V3D_IDENT1_TUPS_SHIFT 12
61 # define V3D_L2CACTL_L2CCLR BIT(2)
62 # define V3D_L2CACTL_L2CDIS BIT(1)
63 # define V3D_L2CACTL_L2CENA BIT(0)
[all …]
H A Dvc4_packet.h78 /* Not an actual hardware packet -- this is what we use to put
145 #define VC4_LOADSTORE_FULL_RES_EOF BIT(3)
146 #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2)
147 #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1)
148 #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0)
155 #define VC4_LOADSTORE_FULL_RES_EOF BIT(3)
156 #define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2)
157 #define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1)
158 #define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0)
166 #define VC4_LOADSTORE_TILE_BUFFER_EOF BIT(3)
[all …]
/linux/sound/soc/mediatek/mt7986/
H A Dmt7986-reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt7986-reg.h -- MediaTek 7986 audio driver reg definition
75 #define CLK_OUT5_PDN BIT(14)
76 #define CLK_OUT5_PDN_MASK BIT(14)
77 #define CLK_IN5_PDN BIT(7)
78 #define CLK_IN5_PDN_MASK BIT(7)
81 #define PDN_APLL_TUNER2 BIT(12)
82 #define PDN_APLL_TUNER2_MASK BIT(12)
85 #define AUD_APLL2_EN BIT(3)
86 #define AUD_APLL2_EN_MASK BIT(3)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
42 #define MT_TX_FREE_COUNT GENMASK(12, 0)
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
[all …]
/linux/drivers/staging/vme_user/
H A Dvme_tsi148.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
50 * Layout of a DMAC Linked-List Descriptor
53 * correctly laid out - It must also be aligned on 64-bit boundaries.
70 * The descriptor needs to be aligned on a 64-bit boundary, we increase
79 * TSI148 ASIC register structure overlays and bit field definitions.
83 * PCFS - PCI Configuration Space Registers
84 * LCSR - Local Control and Status Registers
85 * GCSR - Global Control and Status Registers
86 * CR/CSR - Subset of Configuration ROM /
489 * offset 0x00 0x600 - DEVI/VENI
[all …]
/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_define.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
12 #define MAC_INT_DAISY_MODE_CHG BIT(31) /* Daisy Mode Change */
13 #define MAC_INT_IP_CHKSUM_ERR BIT(23) /* IP Checksum Append Error */
14 #define MAC_INT_WDOG_TIMER1_EXP BIT(22) /* Watchdog Timer1 Expired */
15 #define MAC_INT_WDOG_TIMER0_EXP BIT(21) /* Watchdog Timer0 Expired */
16 #define MAC_INT_INTRUDER_ALERT BIT(20) /* Atruder Alert */
17 #define MAC_INT_PORT_ST_CHG BIT(19) /* Port Status Change */
18 #define MAC_INT_BC_STORM BIT(18) /* Broad Cast Storm */
19 #define MAC_INT_MUST_DROP_LAN BIT(17) /* Global Queue Exhausted */
[all …]
/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
223 #define RCC_SECCFGR_AXISEC 12
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
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