Lines Matching +full:12 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
19 static const s8 lna_gain_table_0[8] = {22, 8, -6, -22, -31, -40, -46, -52};
20 static const s8 lna_gain_table_1[16] = {10, 6, 2, -2, -6, -10, -14, -17,
21 -20, -24, -28, -31, -34, -37, -40, -44};
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8821cu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8821cs_efuse_parsing()
50 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_read_efuse()
51 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
57 efuse->rfe_option = map->rfe_option & 0x1f; in rtw8821c_read_efuse()
58 efuse->rf_board_option = map->rf_board_option; in rtw8821c_read_efuse()
59 efuse->crystal_cap = map->xtal_k; in rtw8821c_read_efuse()
60 efuse->pa_type_2g = map->pa_type; in rtw8821c_read_efuse()
61 efuse->pa_type_5g = map->pa_type; in rtw8821c_read_efuse()
62 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
63 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
64 efuse->channel_plan = map->channel_plan; in rtw8821c_read_efuse()
65 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
66 efuse->country_code[1] = map->country_code[1]; in rtw8821c_read_efuse()
67 efuse->bt_setting = map->rf_bt_setting; in rtw8821c_read_efuse()
68 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
69 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
70 efuse->thermal_meter_k = map->thermal_meter; in rtw8821c_read_efuse()
71 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; in rtw8821c_read_efuse()
72 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; in rtw8821c_read_efuse()
74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; in rtw8821c_read_efuse()
76 switch (efuse->rfe_option) { in rtw8821c_read_efuse()
83 hal->rfe_btg = true; in rtw8821c_read_efuse()
88 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; in rtw8821c_read_efuse()
90 if (rtwdev->efuse.rfe_option == 2 || rtwdev->efuse.rfe_option == 4) in rtw8821c_read_efuse()
91 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; in rtw8821c_read_efuse()
105 return -ENOTSUPP; in rtw8821c_read_efuse()
135 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_init()
139 dm_info->default_ofdm_index = 24; in rtw8821c_pwrtrack_init()
141 dm_info->default_ofdm_index = swing_idx; in rtw8821c_pwrtrack_init()
143 ewma_thermal_init(&dm_info->avg_thermal[RF_PATH_A]); in rtw8821c_pwrtrack_init()
144 dm_info->delta_power_index[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
145 dm_info->delta_power_index_last[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
146 dm_info->pwr_trk_triggered = false; in rtw8821c_pwrtrack_init()
147 dm_info->pwr_trk_init_trigger = true; in rtw8821c_pwrtrack_init()
148 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; in rtw8821c_pwrtrack_init()
160 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_phy_set_param()
188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8821c_phy_set_param()
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); in rtw8821c_phy_set_param()
196 hal->ch_param[1] = rtw_read32_mask(rtwdev, REG_TXSF6, MASKDWORD); in rtw8821c_phy_set_param()
197 hal->ch_param[2] = rtw_read32_mask(rtwdev, REG_TXFILTER, MASKDWORD); in rtw8821c_phy_set_param()
200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8821c_phy_set_param()
228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); in rtw8821c_mac_init()
241 /* Set beacon cotnrol - enable TSF and other related functions */ in rtw8821c_mac_init()
258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); in rtw8821c_mac_init()
272 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); in rtw8821c_cfg_ldo25()
312 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_channel_rf()
344 if (hal->rfe_btg) in rtw8821c_set_channel_rf()
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8821c_set_channel_rf()
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
386 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_cck_tx_filter_srrc()
424 hal->ch_param[0]); in rtw8821c_cck_tx_filter_srrc()
426 hal->ch_param[1] & MASKLWORD); in rtw8821c_cck_tx_filter_srrc()
428 hal->ch_param[2]); in rtw8821c_cck_tx_filter_srrc()
446 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_channel_bb()
450 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
451 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
452 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
470 hal->ch_param[0]); in rtw8821c_set_channel_bb()
472 hal->ch_param[1] & MASKLWORD); in rtw8821c_set_channel_bb()
474 hal->ch_param[2]); in rtw8821c_set_channel_bb()
477 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
478 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
479 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
508 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
512 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
514 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
522 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
531 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
539 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
540 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
548 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
549 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
556 struct rtw_efuse efuse = rtwdev->efuse; in rtw8821c_get_bb_swing()
588 struct rtw_efuse *efuse = &rtwdev->efuse; in get_cck_rx_pwr()
594 if (efuse->rfe_option == 0) { in get_cck_rx_pwr()
604 return -120; in get_cck_rx_pwr()
608 rx_pwr_all = lna_gain - 2 * vga_idx; in get_cck_rx_pwr()
616 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page0()
626 pkt_stat->rx_power[RF_PATH_A] = rx_power; in query_phy_status_page0()
627 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page0()
628 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page0()
629 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; in query_phy_status_page0()
630 pkt_stat->signal_power = rx_power; in query_phy_status_page0()
636 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page1()
638 s8 min_rx_power = -120; in query_phy_status_page1()
640 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) in query_phy_status_page1()
647 else if (rxsc >= 9 && rxsc <= 12) in query_phy_status_page1()
654 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; in query_phy_status_page1()
655 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page1()
656 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page1()
657 pkt_stat->bw = bw; in query_phy_status_page1()
658 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page1()
686 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index_by_rate()
693 pwr_index = hal->tx_pwr_tbl[path][rate]; in rtw8821c_set_tx_power_index_by_rate()
707 struct rtw_hal *hal = &rtwdev->hal; in rtw8821c_set_tx_power_index()
711 for (path = 0; path < hal->rf_path_num; path++) { in rtw8821c_set_tx_power_index()
724 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_false_alarm_statistics()
731 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); in rtw8821c_false_alarm_statistics()
735 dm_info->cck_fa_cnt = cck_fa_cnt; in rtw8821c_false_alarm_statistics()
736 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
737 dm_info->total_fa_cnt = ofdm_fa_cnt; in rtw8821c_false_alarm_statistics()
739 dm_info->total_fa_cnt += cck_fa_cnt; in rtw8821c_false_alarm_statistics()
742 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
743 dm_info->cck_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
746 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
747 dm_info->ofdm_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
750 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
751 dm_info->ht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
754 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
755 dm_info->vht_err_cnt = FIELD_GET(GENMASK(31, 16), crc32_cnt); in rtw8821c_false_alarm_statistics()
758 dm_info->ofdm_cca_cnt = FIELD_GET(GENMASK(31, 16), cca32_cnt); in rtw8821c_false_alarm_statistics()
759 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; in rtw8821c_false_alarm_statistics()
762 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); in rtw8821c_false_alarm_statistics()
763 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; in rtw8821c_false_alarm_statistics()
766 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
767 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
768 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
769 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
770 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
771 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
795 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); in rtw8821c_do_iqk()
819 /* enable PTA (3-wire function form BT side) */ in rtw8821c_coex_cfg_init()
830 /* beacon queue always hi-pri */ in rtw8821c_coex_cfg_init()
838 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_ant_switch()
839 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_ant_switch()
840 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_ant_switch()
845 if (switch_status == coex_dm->cur_switch_status) in rtw8821c_coex_cfg_ant_switch()
848 if (coex_rfe->wlg_at_btg) { in rtw8821c_coex_cfg_ant_switch()
851 if (coex_rfe->ant_switch_polarity) in rtw8821c_coex_cfg_ant_switch()
857 coex_dm->cur_switch_status = switch_status; in rtw8821c_coex_cfg_ant_switch()
859 if (coex_rfe->ant_switch_diversity && in rtw8821c_coex_cfg_ant_switch()
863 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); in rtw8821c_coex_cfg_ant_switch()
875 if (coex_rfe->rfe_module_type != 0x4 && in rtw8821c_coex_cfg_ant_switch()
876 coex_rfe->rfe_module_type != 0x2) in rtw8821c_coex_cfg_ant_switch()
947 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_rfe_type()
948 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8821c_coex_cfg_rfe_type()
949 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_rfe_type()
951 coex_rfe->rfe_module_type = efuse->rfe_option; in rtw8821c_coex_cfg_rfe_type()
952 coex_rfe->ant_switch_polarity = 0; in rtw8821c_coex_cfg_rfe_type()
953 coex_rfe->ant_switch_exist = true; in rtw8821c_coex_cfg_rfe_type()
954 coex_rfe->wlg_at_btg = false; in rtw8821c_coex_cfg_rfe_type()
956 switch (coex_rfe->rfe_module_type) { in rtw8821c_coex_cfg_rfe_type()
960 case 9: /* 1-Ant, Main, WLG */ in rtw8821c_coex_cfg_rfe_type()
961 default: /* 2-Ant, DPDT, WLG */ in rtw8821c_coex_cfg_rfe_type()
964 case 10: /* 1-Ant, Main, BTG */ in rtw8821c_coex_cfg_rfe_type()
966 case 15: /* 2-Ant, DPDT, BTG */ in rtw8821c_coex_cfg_rfe_type()
967 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
970 case 11: /* 1-Ant, Aux, WLG */ in rtw8821c_coex_cfg_rfe_type()
971 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
974 case 12: /* 1-Ant, Aux, BTG */ in rtw8821c_coex_cfg_rfe_type()
975 coex_rfe->wlg_at_btg = true; in rtw8821c_coex_cfg_rfe_type()
976 coex_rfe->ant_switch_polarity = 1; in rtw8821c_coex_cfg_rfe_type()
979 case 13: /* 2-Ant, no switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
981 case 14: /* 2-Ant, no antenna switch, WLG */ in rtw8821c_coex_cfg_rfe_type()
982 coex_rfe->ant_switch_exist = false; in rtw8821c_coex_cfg_rfe_type()
989 struct rtw_coex *coex = &rtwdev->coex; in rtw8821c_coex_cfg_wl_tx_power()
990 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8821c_coex_cfg_wl_tx_power()
991 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_coex_cfg_wl_tx_power()
992 bool share_ant = efuse->share_ant; in rtw8821c_coex_cfg_wl_tx_power()
997 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) in rtw8821c_coex_cfg_wl_tx_power()
1000 coex_dm->cur_wl_pwr_lvl = wl_pwr; in rtw8821c_coex_cfg_wl_tx_power()
1011 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_txagc_swing_offset()
1012 s8 delta_pwr_idx = dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_txagc_swing_offset()
1013 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; in rtw8821c_txagc_swing_offset()
1017 u8 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
1020 pwr_idx_offset_lower = max_t(s8, pwr_idx_offset_lower, -15); in rtw8821c_txagc_swing_offset()
1025 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
1028 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
1029 delta_pwr_idx - pwr_idx_offset; in rtw8821c_txagc_swing_offset()
1035 swing_index = dm_info->default_ofdm_index; in rtw8821c_txagc_swing_offset()
1037 if (dm_info->default_ofdm_index > in rtw8821c_txagc_swing_offset()
1038 (pwr_idx_offset_lower - delta_pwr_idx)) in rtw8821c_txagc_swing_offset()
1039 swing_index = dm_info->default_ofdm_index + in rtw8821c_txagc_swing_offset()
1040 delta_pwr_idx - pwr_idx_offset_lower; in rtw8821c_txagc_swing_offset()
1050 swing_index = ARRAY_SIZE(rtw8821c_txscale_tbl) - 1; in rtw8821c_txagc_swing_offset()
1072 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwrtrack_set()
1075 u8 channel = rtwdev->hal.current_channel; in rtw8821c_pwrtrack_set()
1076 u8 band_width = rtwdev->hal.current_band_width; in rtw8821c_pwrtrack_set()
1078 u8 tx_rate = dm_info->tx_rate; in rtw8821c_pwrtrack_set()
1079 u8 max_pwr_idx = rtwdev->chip->max_power_index; in rtw8821c_pwrtrack_set()
1086 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1087 pwr_idx_offset_lower = 0 - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1094 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_pwrtrack()
1100 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8821c_phy_pwrtrack()
1107 if (dm_info->pwr_trk_init_trigger) in rtw8821c_phy_pwrtrack()
1108 dm_info->pwr_trk_init_trigger = false; in rtw8821c_phy_pwrtrack()
1115 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); in rtw8821c_phy_pwrtrack()
1117 dm_info->delta_power_index[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
1120 if (dm_info->delta_power_index[RF_PATH_A] == in rtw8821c_phy_pwrtrack()
1121 dm_info->delta_power_index_last[RF_PATH_A]) in rtw8821c_phy_pwrtrack()
1124 dm_info->delta_power_index_last[RF_PATH_A] = in rtw8821c_phy_pwrtrack()
1125 dm_info->delta_power_index[RF_PATH_A]; in rtw8821c_phy_pwrtrack()
1135 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_pwr_track()
1136 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_pwr_track()
1138 if (efuse->power_track_type != 0) in rtw8821c_pwr_track()
1141 if (!dm_info->pwr_trk_triggered) { in rtw8821c_pwr_track()
1144 dm_info->pwr_trk_triggered = true; in rtw8821c_pwr_track()
1149 dm_info->pwr_trk_triggered = false; in rtw8821c_pwr_track()
1175 if (bfee->role == RTW_BFEE_SU) in rtw8821c_bf_config_bfee()
1177 else if (bfee->role == RTW_BFEE_MU) in rtw8821c_bf_config_bfee()
1185 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8821c_phy_cck_pd_set()
1189 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", in rtw8821c_phy_cck_pd_set()
1190 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); in rtw8821c_phy_cck_pd_set()
1192 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) in rtw8821c_phy_cck_pd_set()
1200 dm_info->cck_pd_default + new_lvl * 2, in rtw8821c_phy_cck_pd_set()
1201 pd[new_lvl], dm_info->cck_fa_avg); in rtw8821c_phy_cck_pd_set()
1203 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; in rtw8821c_phy_cck_pd_set()
1205 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; in rtw8821c_phy_cck_pd_set()
1208 dm_info->cck_pd_default + new_lvl * 2); in rtw8821c_phy_cck_pd_set()
1241 RTW_PWR_CMD_WRITE, BIT(0), 0},
1246 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1251 RTW_PWR_CMD_WRITE, BIT(0), 0},
1256 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1279 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1289 RTW_PWR_CMD_WRITE, BIT(5), 0},
1294 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1299 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1304 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1309 RTW_PWR_CMD_WRITE, BIT(0), 0},
1314 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1319 RTW_PWR_CMD_WRITE, BIT(7), 0},
1324 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1329 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1334 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1339 RTW_PWR_CMD_POLLING, BIT(0), 0},
1344 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1349 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1354 RTW_PWR_CMD_WRITE, BIT(1), 0},
1359 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1360 (BIT(7) | BIT(6) | BIT(5))},
1365 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1370 RTW_PWR_CMD_WRITE, BIT(1), 0},
1383 RTW_PWR_CMD_WRITE, BIT(3), 0},
1393 RTW_PWR_CMD_WRITE, BIT(1), 0},
1398 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1403 RTW_PWR_CMD_WRITE, BIT(1), 0},
1408 RTW_PWR_CMD_WRITE, BIT(0), 0},
1413 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1418 RTW_PWR_CMD_POLLING, BIT(1), 0},
1423 RTW_PWR_CMD_WRITE, BIT(3), 0},
1428 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1446 RTW_PWR_CMD_WRITE, BIT(5), 0},
1451 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1456 RTW_PWR_CMD_WRITE, BIT(0), 0},
1461 RTW_PWR_CMD_WRITE, BIT(5), 0},
1466 RTW_PWR_CMD_WRITE, BIT(4), 0},
1471 RTW_PWR_CMD_WRITE, BIT(0), 0},
1476 RTW_PWR_CMD_WRITE, BIT(1), 0},
1481 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1486 RTW_PWR_CMD_WRITE, BIT(2), 0},
1491 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1496 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1501 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1506 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1511 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1516 RTW_PWR_CMD_POLLING, BIT(1), 0},
1521 RTW_PWR_CMD_WRITE, BIT(1), 0},
1692 /* rssi in percentage % (dbm = % - 100) */
1696 /* Shared-Antenna Coex Table */
1698 {0x55555555, 0x55555555}, /* case-0 */
1703 {0xfafafafa, 0xfafafafa}, /* case-5 */
1708 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1713 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1718 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1723 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1728 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1733 /* Non-Shared-Antenna Coex Table */
1735 {0xffffffff, 0xffffffff}, /* case-100 */
1740 {0xffffffff, 0xffffffff}, /* case-105 */
1745 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1750 {0xffff55ff, 0xffff55ff}, /* case-115 */
1755 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1761 /* Shared-Antenna TDMA */
1763 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1764 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1768 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1773 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1778 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1783 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1788 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1793 /* Non-Shared-Antenna TDMA */
1795 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1800 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1805 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1810 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1815 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1824 {0, 20, false, 7}, /* for WL-CPT */
1833 {0, 20, false, 7}, /* for WL-CPT */
1844 11, 11, 12, 12, 12, 12, 12},
1846 11, 12, 12, 12, 12, 12, 12, 12},
1848 11, 12, 12, 12, 12, 12, 12},
1853 12, 12, 12, 12, 12, 12, 12},
1855 12, 12, 12, 12, 12, 12, 12, 12},
1857 11, 12, 12, 12, 12, 12, 12, 12},
1862 11, 11, 12, 12, 12, 12, 12},
1864 11, 12, 12, 12, 12, 12, 12, 12},
1866 11, 12, 12, 12, 12, 12, 12},
1871 12, 12, 12, 12, 12, 12, 12},
1873 12, 12, 12, 12, 12, 12, 12, 12},
1875 11, 12, 12, 12, 12, 12, 12, 12},
1957 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1960 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1961 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1962 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1963 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1968 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2002 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),