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/linux/drivers/clk/renesas/
H A Dr9a09g057-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
15 #include "rzv2h-cpg.h"
197 BUS_MSTOP(5, BIT(9))),
199 BUS_MSTOP(3, BIT(2))),
201 BUS_MSTOP(3, BIT(3))),
203 BUS_MSTOP(10, BIT(11))),
205 BUS_MSTOP(10, BIT(12))),
209 BUS_MSTOP(3, BIT(5))),
[all …]
H A Dr9a09g056-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
173 BUS_MSTOP(3, BIT(5))),
175 BUS_MSTOP(5, BIT(10))),
177 BUS_MSTOP(5, BIT(11))),
179 BUS_MSTOP(2, BIT(13))),
181 BUS_MSTOP(2, BIT(14))),
183 BUS_MSTOP(11, BIT(13))),
[all …]
H A Dr9a09g047-cpg.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
15 #include "rzv2h-cpg.h"
190 BUS_MSTOP(5, BIT(9))),
192 BUS_MSTOP(3, BIT(2))),
194 BUS_MSTOP(3, BIT(3))),
196 BUS_MSTOP(10, BIT(11))),
198 BUS_MSTOP(10, BIT(12))),
202 BUS_MSTOP(3, BIT(5))),
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h1 // SPDX-License-Identifier: GPL-2.0-only
7 #define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)
10 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
11 #define MTK_WDMA_DESC_CTRL_BURST BIT(16)
13 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
14 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
16 #define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE BIT(29)
17 #define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE BIT(31)
29 #define MTK_WED_RESET_TX_BM BIT(0)
30 #define MTK_WED_RESET_RX_BM BIT(1)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
[all …]
/linux/include/soc/mscc/
H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
H A Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
35 #define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
37 #define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
[all …]
H A Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
/linux/drivers/net/can/ctucanfd/
H A Dctucanfd_kregs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2015-2018 Ondrej Ille <ondrej.ille@gmail.com> FEE CTU
7 * Copyright (C) 2018-2022 Ondrej Ille <ondrej.ille@gmail.com> self-funded
8 * Copyright (C) 2018-2019 Martin Jerabek <martin.jerabek01@gmail.com> FEE CTU
9 * Copyright (C) 2018-2022 Pavel Pisa <pisa@cmp.felk.cvut.cz> FEE CTU/self-funded
103 #define REG_MODE_RST BIT(0)
104 #define REG_MODE_BMM BIT(1)
105 #define REG_MODE_STM BIT(2)
106 #define REG_MODE_AFM BIT(3)
107 #define REG_MODE_FDE BIT(4)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
[all …]
/linux/drivers/net/ethernet/asix/
H A Dax88796c_main.h1 /* SPDX-License-Identifier: GPL-2.0-only */
121 #define AX_FC_RX BIT(0)
122 #define AX_FC_TX BIT(1)
123 #define AX_FC_ANEG BIT(2)
126 #define AX_CAP_COMP BIT(0)
153 #define PSR_DEV_READY BIT(7)
155 #define PSR_RESET_CLR BIT(15)
158 #define FER_IPALM BIT(0)
159 #define FER_DCRC BIT(1)
160 #define FER_RH3M BIT(2)
[all …]
/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2021-2022 Bootlin
20 #define SUN6I_ISP_FE_CFG_EN BIT(0)
25 #define SUN6I_ISP_FE_CTRL_SCAP_EN BIT(0)
26 #define SUN6I_ISP_FE_CTRL_VCAP_EN BIT(1)
27 #define SUN6I_ISP_FE_CTRL_PARA_READY BIT(2)
28 #define SUN6I_ISP_FE_CTRL_LUT_UPDATE BIT(3)
29 #define SUN6I_ISP_FE_CTRL_LENS_UPDATE BIT(4)
30 #define SUN6I_ISP_FE_CTRL_GAMMA_UPDATE BIT(5)
31 #define SUN6I_ISP_FE_CTRL_DRC_UPDATE BIT(6)
[all …]
/linux/drivers/comedi/drivers/
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddescs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 #define RDES0_PAYLOAD_CSUM_ERR BIT(0)
19 #define RDES0_CRC_ERROR BIT(1)
20 #define RDES0_DRIBBLING BIT(2)
21 #define RDES0_MII_ERROR BIT(3)
22 #define RDES0_RECEIVE_WATCHDOG BIT(4)
23 #define RDES0_FRAME_TYPE BIT(5)
24 #define RDES0_COLLISION BIT(6)
25 #define RDES0_IPC_CSUM_ERROR BIT(7)
26 #define RDES0_LAST_DESCRIPTOR BIT(8)
[all …]
/linux/drivers/gpu/drm/mcde/
H A Dmcde_display_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #define MCDE_PP_VCMPA BIT(0)
12 #define MCDE_PP_VCMPB BIT(1)
13 #define MCDE_PP_VSCC0 BIT(2)
14 #define MCDE_PP_VSCC1 BIT(3)
15 #define MCDE_PP_VCMPC0 BIT(4)
16 #define MCDE_PP_VCMPC1 BIT(5)
17 #define MCDE_PP_ROTFD_A BIT(6)
18 #define MCDE_PP_ROTFD_B BIT(7)
74 #define MCDE_EXTSRCXCONF_BPP_YCBCR422 11
[all …]
/linux/drivers/power/supply/
H A Dbd99954-charger.h1 /* SPDX-License-Identifier: GPL-2.0-only */
500 [F_PP_BOTH_THRU] = REG_FIELD(VIN_CTRL_SET, 11, 11),
510 [F_VCC_BC_DISEN] = REG_FIELD(CHGOP_SET1, 11, 11),
550 [F_PROCHOT_ICRIT_DG_SET] = REG_FIELD(PROCHOT_CTRL_SET, 10, 11),
565 [F_IOUT_DACIN_VAL] = REG_FIELD(IOUT_DACIN_VAL, 0, 11),
577 [F_VCC_PUPDET] = REG_FIELD(VCC_UCD_STATUS, 11, 11),
621 [F_VBUS_PUPDET] = REG_FIELD(VBUS_UCD_STATUS, 11, 11),
657 [F_ONE_CELL_MODE] = REG_FIELD(IC_SET1, 11, 11),
674 [F_ADCTMOD] = REG_FIELD(VM_CTRL_SET, 10, 11),
704 [F_EXTIADP_TH_SET] = REG_FIELD(EXTIADP_TH_SET, 0, 11),
[all …]
/linux/drivers/mmc/host/
H A Dmeson-mx-sdhc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
15 #define MESON_SDHC_SEND_CMD_HAS_RESP BIT(6)
16 #define MESON_SDHC_SEND_CMD_HAS_DATA BIT(7)
17 #define MESON_SDHC_SEND_RESP_LEN BIT(8)
18 #define MESON_SDHC_SEND_RESP_NO_CRC BIT(9)
19 #define MESON_SDHC_SEND_DATA_DIR BIT(10)
20 #define MESON_SDHC_SEND_DATA_STOP BIT(11)
21 #define MESON_SDHC_SEND_R1B BIT(12)
26 #define MESON_SDHC_CTRL_DDR_MODE BIT(2)
27 #define MESON_SDHC_CTRL_TX_CRC_NOCHECK BIT(3)
[all …]
/linux/drivers/thunderbolt/
H A Dtb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - Port/Switch config area registers
69 * struct tb_cap_extended_short - Switch extended short capability
84 * struct tb_cap_extended_long - Switch extended long capability
102 * struct tb_cap_any - Structure capable of hold every capability
134 u32 unknown3:11;
140 bool fl_sk:1; /* send pulse to transfer one bit */
159 u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */
160 u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */
198 #define ROUTER_CS_3_V BIT(31)
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
222 #define RCC_SECCFGR_MPUSEC 11
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
62 #define MT_TXD1_HDR_INFO GENMASK(15, 11)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
[all …]
/linux/drivers/net/dsa/b53/
H A Db53_serdes.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
11 /* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
18 #define SERDES_ID0_REV_NUM_SHIFT 11
27 #define FIBER_MODE_1000X BIT(0)
28 #define TBI_INTERFACE BIT(1)
29 #define SIGNAL_DETECT_EN BIT(2)
30 #define INVERT_SIGNAL_DETECT BIT(3)
31 #define AUTODET_EN BIT(4)
32 #define SGMII_MASTER_MODE BIT(5)
33 #define DISABLE_DLL_PWRDOWN BIT(6)
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
[all …]
/linux/include/linux/amba/
H A Dpl080.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 * the ability to move more than 2^11 counts of data and some extra
38 #define PL080_CONFIG_M2_BE BIT(2)
39 #define PL080_CONFIG_M1_BE BIT(1)
40 #define PL080_CONFIG_ENABLE BIT(0)
72 #define PL080_LLI_LM_AHB2 BIT(0)
74 #define PL080_CONTROL_TC_IRQ_EN BIT(31)
77 #define PL080_CONTROL_PROT_CACHE BIT(30)
78 #define PL080_CONTROL_PROT_BUFF BIT(29)
79 #define PL080_CONTROL_PROT_SYS BIT(28)
[all …]
/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
14 #define CHNL_CTRL_CHNL_EN BIT(31)
15 #define CHNL_CTRL_CLK_EN BIT(30)
16 #define CHNL_CTRL_CHNL_BYPASS BIT(29)
21 #define CHNL_CTRL_SW_RST BIT(24)
27 #define CHNL_CTRL_SRC_TYPE_MASK BIT(4)
88 #define CHNL_IMG_CTRL_GBL_ALPHA_EN BIT(15)
98 #define CHNL_IMG_CTRL_DEC_X_MASK GENMASK(11, 10)
101 #define CHNL_IMG_CTRL_CROP_EN BIT(7)
[all …]

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