Lines Matching +full:11 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
15 #include "rzv2h-cpg.h"
173 BUS_MSTOP(3, BIT(5))),
175 BUS_MSTOP(5, BIT(10))),
177 BUS_MSTOP(5, BIT(11))),
179 BUS_MSTOP(2, BIT(13))),
181 BUS_MSTOP(2, BIT(14))),
183 BUS_MSTOP(11, BIT(13))),
185 BUS_MSTOP(11, BIT(14))),
187 BUS_MSTOP(11, BIT(15))),
189 BUS_MSTOP(12, BIT(0))),
190 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11,
191 BUS_MSTOP(3, BIT(10))),
193 BUS_MSTOP(3, BIT(10))),
195 BUS_MSTOP(1, BIT(0))),
197 BUS_MSTOP(1, BIT(0))),
199 BUS_MSTOP(5, BIT(12))),
201 BUS_MSTOP(5, BIT(12))),
203 BUS_MSTOP(5, BIT(13))),
205 BUS_MSTOP(5, BIT(13))),
207 BUS_MSTOP(3, BIT(14))),
209 BUS_MSTOP(10, BIT(15))),
211 BUS_MSTOP(10, BIT(15))),
213 BUS_MSTOP(10, BIT(15))),
215 BUS_MSTOP(3, BIT(13))),
217 BUS_MSTOP(1, BIT(1))),
219 BUS_MSTOP(1, BIT(2))),
221 BUS_MSTOP(1, BIT(3))),
223 BUS_MSTOP(1, BIT(4))),
225 BUS_MSTOP(1, BIT(5))),
227 BUS_MSTOP(1, BIT(6))),
229 BUS_MSTOP(1, BIT(7))),
230 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27,
231 BUS_MSTOP(1, BIT(8))),
233 BUS_MSTOP(4, BIT(5))),
235 BUS_MSTOP(4, BIT(5))),
237 BUS_MSTOP(4, BIT(5))),
239 BUS_MSTOP(8, BIT(2))),
241 BUS_MSTOP(8, BIT(2))),
243 BUS_MSTOP(8, BIT(2))),
245 BUS_MSTOP(8, BIT(2))),
247 BUS_MSTOP(8, BIT(3))),
249 BUS_MSTOP(8, BIT(3))),
251 BUS_MSTOP(8, BIT(3))),
253 BUS_MSTOP(8, BIT(3))),
254 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11,
255 BUS_MSTOP(8, BIT(4))),
257 BUS_MSTOP(8, BIT(4))),
259 BUS_MSTOP(8, BIT(4))),
261 BUS_MSTOP(8, BIT(4))),
262 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19,
263 BUS_MSTOP(7, BIT(7))),
264 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
265 BUS_MSTOP(7, BIT(9))),
266 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22,
267 BUS_MSTOP(7, BIT(10))),
268 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
269 BUS_MSTOP(8, BIT(5)), 1),
270 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
271 BUS_MSTOP(8, BIT(5)), 1),
272 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26,
273 BUS_MSTOP(8, BIT(5)), 1),
274 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27,
275 BUS_MSTOP(8, BIT(5)), 1),
276 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28,
277 BUS_MSTOP(8, BIT(5))),
278 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29,
279 BUS_MSTOP(8, BIT(5))),
280 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30,
281 BUS_MSTOP(8, BIT(6)), 1),
282 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31,
283 BUS_MSTOP(8, BIT(6)), 1),
285 BUS_MSTOP(8, BIT(6)), 1),
287 BUS_MSTOP(8, BIT(6)), 1),
289 BUS_MSTOP(8, BIT(6))),
291 BUS_MSTOP(8, BIT(6))),
293 BUS_MSTOP(3, BIT(4))),
295 BUS_MSTOP(3, BIT(4))),
297 BUS_MSTOP(3, BIT(4))),
321 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */
322 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */
336 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
337 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */