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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
46 #define MT_TX_FREE_PAIR BIT(31)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
72 #define MT_TXD2_HTC_VLD BIT(13)
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H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
38 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
39 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
40 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
41 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
42 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
44 #define MT_RXD1_NORMAL_CM BIT(23)
45 #define MT_RXD1_NORMAL_CLM BIT(24)
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/freebsd/contrib/file/magic/Magdir/
H A Dapt2 #------------------------------------------------------------------------------
3 # $File: apt,v 1.1 2016/10/17 19:51:57 christos Exp $
5 # <http://www.fifi.org/doc/libapt-pkg-doc/cache.html/ch2.html>
6 # <https://anonscm.debian.org/cgit/apt/apt.git/tree/apt-pkg/pkgcache.h#n292>
8 # before version 10 ("old format"), data was in arch-specific long/short
10 # old format 64 bit
11 0 name apt-cache-64bit-be
16 # old format 32 bit
17 0 name apt-cache-32bit-be
23 0 name apt-cache-be
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H A Dmach2 #------------------------------------------------------------
8 #------------------------------------------------------------
9 # if set, it's for the 64-bit version of the architecture
10 # yes, this is separate from the low-order magic number bit
11 # it's also separate from the "64-bit libraries" bit in the
14 # Reference: https://opensource.apple.com/source/cctools/cctools-949.0.1/
15 # include/mach-o/loader.h
17 0 name mach-o-cpu
20 # 32-bit ABIs.
34 >>>4 belong&0x00ffffff 10 vax8650
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcFixupKinds.h1 //===-- SparcFixupKinds.h - Sparc Specific Fixup Entries --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
17 // fixup_sparc_call30 - 30-bit PC relative relocation for call
20 /// fixup_sparc_br22 - 22-bit PC relative relocation for
24 /// fixup_sparc_br19 - 19-bit PC relative relocation for
28 /// fixup_sparc_bpr - 16-bit fixup for bpr
31 /// fixup_sparc_13 - 13-bit fixup
34 /// fixup_sparc_hi22 - 22-bit fixup corresponding to %hi(foo)
38 /// fixup_sparc_lo10 - 10-bit fixup corresponding to %lo(foo)
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/freebsd/sys/contrib/dev/rtw89/
H A Dtxrx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
11 #define DATA_RATE_MODE_CTRL_MASK_V1 GENMASK(10, 8)
28 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_rate_mode()
41 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_ht_mcs()
49 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_mcs()
62 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) in rtw89_get_data_nss()
71 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23)
72 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22)
73 #define RTW89_TXWD_BODY0_FW_DL BIT(20)
76 #define RTW89_TXWD_BODY0_STF_MODE BIT(10)
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H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
18 #define BAC_OOBS_SEL BIT(4)
20 #define B_BAC_EQ_SEL BIT(5)
24 #define B_PCIE_BIT_PSAVE BIT(15)
26 #define OFFSET_CAL_MODE BIT(13)
27 #define BAC_RX_TEST_EN BIT(6)
32 #define B_PCIE_BIT_PINOUT_DIS BIT(3)
37 #define B_PCIE_BIT_RD_SEL BIT(2)
54 #define B_AX_CLK_CALIB_EN BIT(12)
55 #define B_AX_CALIB_EN BIT(13)
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H A Dreg.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
9 #define B_AX_AUTOLOAD_SUS BIT(5)
13 #define B_AX_PWC_EV2EF_B15 BIT(15)
14 #define B_AX_PWC_EV2EF_B14 BIT(14)
15 #define B_AX_ISO_EB2CORE BIT(8)
18 #define B_AX_FEN_BB_GLB_RSTN BIT(1)
19 #define B_AX_FEN_BBRSTB BIT(0)
22 #define B_AX_SOP_ASWRM BIT(31)
23 #define B_AX_SOP_PWMM_DSWR BIT(29)
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td1 //===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
21 "\n return isUInt<"#BSz#">(N->getSExtValue());"> {
27 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
31 // e.g. s3 field may encode the signed integers values -1 .. 6
34 "\n return isInt<"#BSz#">(N->getSExtValue());"> {
64 class ExtMode<bit mode, string instSfx, string asmSfx> {
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1 //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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/freebsd/contrib/wpa/src/common/
H A Dieee802_11_defs.h3 * Copyright (c) 2002-2019, Jouni Malinen <j@w1.fi>
4 * Copyright (c) 2007-2008 Intel Corporation
39 #define WLAN_GET_SEQ_FRAG(seq) ((seq) & (BIT(3) | BIT(2) | BIT(1) | BIT(0)))
41 (((seq) & (~(BIT(3) | BIT(2) | BIT(1) | BIT(0)))) >> 4)
57 #define WLAN_FC_STYPE_DISASSOC 10
64 #define WLAN_FC_STYPE_PSPOLL 10
82 #define WLAN_FC_STYPE_QOS_DATA_CFPOLL 10
105 #define WLAN_CAPABILITY_ESS BIT(0)
106 #define WLAN_CAPABILITY_IBSS BIT(1)
107 #define WLAN_CAPABILITY_CF_POLLABLE BIT(2)
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
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/freebsd/sys/contrib/device-tree/Bindings/
H A Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - acbel,fsg032
35 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
36 - ad,ad7414 # Deprecated, use adi,ad7414
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/freebsd/sys/contrib/dev/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
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/freebsd/sys/contrib/dev/athk/ath11k/
H A Dhal_rx.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
206 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9)
207 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10)
208 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11)
253 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
256 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
257 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
280 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
282 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
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/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822b.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8822be_efuse_parsing()
32 ether_addr_copy(efuse->addr, map->u.mac_addr); in rtw8822bu_efuse_parsing()
38 ether_addr_copy(efuse->addr, map->s.mac_addr); in rtw8822bs_efuse_parsing()
43 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8822b_read_efuse()
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); in rtw8822b_read_efuse()
50 efuse->rfe_option = map->rfe_option; in rtw8822b_read_efuse()
51 efuse->rf_board_option = map->rf_board_option; in rtw8822b_read_efuse()
52 efuse->crystal_cap = map->xtal_k; in rtw8822b_read_efuse()
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H A Drtw8723d.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
69 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_init()
72 dm_info->default_ofdm_index = RTW_DEF_OFDM_SWING_INDEX; in rtw8723d_pwrtrack_init()
74 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { in rtw8723d_pwrtrack_init()
75 ewma_thermal_init(&dm_info->avg_thermal[path]); in rtw8723d_pwrtrack_init()
76 dm_info->delta_power_index[path] = 0; in rtw8723d_pwrtrack_init()
78 dm_info->pwr_trk_triggered = false; in rtw8723d_pwrtrack_init()
79 dm_info->pwr_trk_init_trigger = true; in rtw8723d_pwrtrack_init()
80 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; in rtw8723d_pwrtrack_init()
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H A Drtw8812a.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
26 rx_pwr_all = -94 + 2 * (27 - vga_idx); in rtw8812a_cck_rx_pwr()
28 rx_pwr_all = -94; in rtw8812a_cck_rx_pwr()
31 rx_pwr_all = -42 + 2 * (2 - vga_idx); in rtw8812a_cck_rx_pwr()
34 rx_pwr_all = -36 + 2 * (7 - vga_idx); in rtw8812a_cck_rx_pwr()
37 rx_pwr_all = -30 + 2 * (7 - vga_idx); in rtw8812a_cck_rx_pwr()
40 rx_pwr_all = -18 + 2 * (7 - vga_idx); in rtw8812a_cck_rx_pwr()
43 rx_pwr_all = 2 * (5 - vga_idx); in rtw8812a_cck_rx_pwr()
46 rx_pwr_all = 14 - 2 * vga_idx; in rtw8812a_cck_rx_pwr()
49 rx_pwr_all = 20 - 2 * vga_idx; in rtw8812a_cck_rx_pwr()
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/freebsd/share/man/man7/
H A Dorders.738 .Bl -column -offset 2n \
39 "Kilobyte" "Prefix" "Power of 2" "Power of 10"
40 .It Sy Name Ta Sy Prefix Ta Sy Power of 2 Ta Sy Power of 10
41 .It Kilobyte Ta kB Ta 2^10 Ta 10^3
42 .It Megabyte Ta MB Ta 2^20 Ta 10^6
43 .It Gigabyte Ta GB Ta 2^30 Ta 10^9
44 .It Terabyte Ta TB Ta 2^40 Ta 10^12
45 .It Petabyte Ta PB Ta 2^50 Ta 10^15
46 .It Exabyte Ta EB Ta 2^60 Ta 10^18
47 .It Zettabyte Ta ZB Ta 2^70 Ta 10^21
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dsmmintrin.h1 /*===---- smmintrin.h - SSE4 intrinsics ------------------------------------===
5 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 *===-----------------------------------------------------------------------===
22 __target__("sse4.1,no-evex512"), __min_vector_width__(128)))
41 /// Rounds up each element of the 128-bit vector of [4 x float] to an
42 /// integer and returns the rounded values in a 128-bit vector of
54 /// A 128-bit vector of [4 x float] values to be rounded up.
55 /// \returns A 128-bit vector of [4 x float] containing the rounded values.
58 /// Rounds up each element of the 128-bit vector of [2 x double] to an
59 /// integer and returns the rounded values in a 128-bit vector of
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/freebsd/share/man/man4/
H A Dice.42 .\" SPDX-License-Identifier: BSD-3-Clause
4 .\" Copyright (c) 2019-2020, Intel Corporation
73 .Bl -bullet -compact
75 Intel\(rg Ethernet Controller E810\-C
77 Intel\(rg Ethernet Controller E810\-XXV
79 Intel\(rg Ethernet Connection E822\-C
81 Intel\(rg Ethernet Connection E822\-L
83 Intel\(rg Ethernet Connection E823\-C
85 Intel\(rg Ethernet Connection E823\-L
87 Intel\(rg Ethernet Connection E825\-C
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H A Dahc.42 .\" SPDX-License-Identifier: BSD-3-Clause
39 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
66 .Tn SCSI-Select
74 For systems that store non-volatil
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/freebsd/sys/contrib/dev/athk/ath12k/
H A Dhal_rx.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
245 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9)
246 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10)
247 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11)
299 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
302 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
303 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
326 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
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/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_inline.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
19 #define ADF_C4XXX_SADB_SIZE_BIT BIT(24)
21 ((accel_dev)->aram_info->sadb_region_size / 32)
24 /* SADB CTRL register bit offsets */
39 #define ADF_C4XXX_STATS_REQUEST_ENABLED BIT(16)
40 #define ADF_C4XXX_STATS_REQUEST_DISABLED ~BIT(16)
45 #define ADF_C4XXX_MAC_STATS_READY BIT(0)
46 #define ADF_C4XXX_MAX_NUM_STAT_READY_READS 10
48 #define ADF_C4XXX_MAC_ERROR_TX_UNDERRUN BIT(6)
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/freebsd/sys/dev/qat/include/
H A Dicp_qat_hw.h1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /* Copyright(c) 2007-2022 Intel Corporation */
17 ICP_QAT_HW_AE_10 = 10,
43 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
83 ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = BIT(0),
84 ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = BIT(1),
85 ICP_ACCEL_CAPABILITIES_CIPHER = BIT(2),
86 ICP_ACCEL_CAPABILITIES_AUTHENTICATION = BIT(3),
87 ICP_ACCEL_CAPABILITIES_RESERVED_1 = BIT(4),
88 ICP_ACCEL_CAPABILITIES_COMPRESSION = BIT(5),
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