Lines Matching +full:10 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
26 ether_addr_copy(efuse->addr, map->e.mac_addr);
32 ether_addr_copy(efuse->addr, map->u.mac_addr);
38 ether_addr_copy(efuse->addr, map->s.mac_addr);
43 struct rtw_efuse *efuse = &rtwdev->efuse;
49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7));
50 efuse->rfe_option = map->rfe_option;
51 efuse->rf_board_option = map->rf_board_option;
52 efuse->crystal_cap = map->xtal_k;
53 efuse->pa_type_2g = map->pa_type;
54 efuse->pa_type_5g = map->pa_type;
55 efuse->lna_type_2g = map->lna_type_2g[0];
56 efuse->lna_type_5g = map->lna_type_5g[0];
57 efuse->channel_plan = map->channel_plan;
58 efuse->country_code[0] = map->country_code[0];
59 efuse->country_code[1] = map->country_code[1];
60 efuse->bt_setting = map->rf_bt_setting;
61 efuse->regd = map->rf_board_option & 0x7;
62 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter;
63 efuse->thermal_meter_k = map->thermal_meter;
66 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
80 return -ENOTSUPP;
89 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3);
90 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0);
91 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1);
95 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3);
99 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3);
127 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
132 dm_info->default_ofdm_index = 24;
134 dm_info->default_ofdm_index = swing_idx;
136 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
137 ewma_thermal_init(&dm_info->avg_thermal[path]);
138 dm_info->delta_power_index[path] = 0;
140 dm_info->pwr_trk_triggered = false;
141 dm_info->pwr_trk_init_trigger = true;
142 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
154 struct rtw_hal *hal = &rtwdev->hal;
170 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
178 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
268 /* Set beacon cotnrol - enable TSF and other related functions */
292 struct rtw_hal *hal = &rtwdev->hal;
297 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0);
301 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0);
304 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
306 if (hal->antenna_rx == BB_PATH_AB ||
307 hal->antenna_tx == BB_PATH_AB) {
310 } else if (hal->antenna_rx == hal->antenna_tx) {
321 struct rtw_hal *hal = &rtwdev->hal;
333 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0);
336 if (hal->antenna_rx == BB_PATH_AB ||
337 hal->antenna_tx == BB_PATH_AB) {
340 } else if (hal->antenna_rx == hal->antenna_tx) {
387 *reg82c = cca_ccut->reg82c[col];
388 *reg830 = cca_ccut->reg830[col];
389 *reg838 = cca_ccut->reg838[col];
424 struct rtw_hal *hal = &rtwdev->hal;
425 struct rtw_efuse *efuse = &rtwdev->efuse;
432 cca_ccut = rfe_info->cca_ccut_2g;
434 if (hal->antenna_rx == BB_PATH_A ||
435 hal->antenna_rx == BB_PATH_B)
440 cca_ccut = rfe_info->cca_ccut_5g;
442 if (hal->antenna_rx == BB_PATH_A ||
443 hal->antenna_rx == BB_PATH_B)
451 switch (rfe_info->fem) {
455 if (rfe_info->ifem_ext)
470 if ((hal->cut_version == RTW_CHIP_VER_CUT_B &&
475 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G))
483 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B))
500 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8))
502 #define RF18_BAND_5G (BIT(16) | BIT(8))
504 #define RF18_RFSI_MASK (BIT(18) | BIT(17))
505 #define RF18_RFSI_GE_CH80 (BIT(17))
506 #define RF18_RFSI_GT_CH144 (BIT(18))
507 #define RF18_BW_MASK (BIT(11) | BIT(10))
508 #define RF18_BW_20M (BIT(11) | BIT(10))
509 #define RF18_BW_40M (BIT(11))
510 #define RF18_BW_80M (BIT(10))
511 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15))
513 struct rtw_hal *hal = &rtwdev->hal;
546 rf_reg_be = low_band[(channel - 36) >> 1];
548 rf_reg_be = middle_band[(channel - 100) >> 1];
550 rf_reg_be = high_band[(channel - 149) >> 1];
558 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1);
560 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0);
563 if (hal->rf_type > RF_1T1R)
566 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0);
567 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1);
577 struct rtw_hal *hal = &rtwdev->hal;
581 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2);
583 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2);
588 hal->antenna_rx | (hal->antenna_rx << 4));
595 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1);
596 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0);
597 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
600 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
601 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1);
602 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0);
605 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2);
606 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2);
607 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1);
614 struct rtw_efuse *efuse = &rtwdev->efuse;
615 u8 rfe_option = efuse->rfe_option;
619 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1);
620 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0);
621 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0);
636 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1);
637 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1);
638 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0);
668 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
672 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
674 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
681 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
689 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1);
693 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1);
699 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20));
702 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
703 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
708 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20));
711 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0);
712 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1);
720 struct rtw_efuse *efuse = &rtwdev->efuse;
723 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
724 "rfe_option %d is out of boundary\n", efuse->rfe_option))
727 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
735 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel);
741 struct rtw_efuse *efuse = &rtwdev->efuse;
743 u8 ch = rtwdev->hal.current_channel;
747 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info),
748 "rfe_option %d is out of boundary\n", efuse->rfe_option))
751 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option];
763 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3);
764 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1);
765 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1);
784 if (is_tx2_path || rtwdev->mp_mode) {
790 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0);
791 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0);
802 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0);
803 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0);
804 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0);
806 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1);
807 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1);
808 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1);
811 for (counter = 100; counter > 0; counter--) {
836 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch);
842 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
843 s8 min_rx_power = -120;
847 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110;
848 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
849 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
850 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
852 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
858 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
860 s8 min_rx_power = -120;
866 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
880 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
881 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
882 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
883 pkt_stat->bw = bw;
884 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
885 pkt_stat->rx_power[RF_PATH_B],
888 dm_info->curr_rx_rate = pkt_stat->rate;
890 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
891 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
893 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
894 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
896 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
897 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
899 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
900 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
901 dm_info->rssi[path] = rssi;
902 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
903 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
905 rx_evm = pkt_stat->rx_evm[path];
911 evm_dbm = ((u8)-rx_evm >> 1);
913 dm_info->rx_evm_dbm[path] = evm_dbm;
940 struct rtw_hal *hal = &rtwdev->hal;
948 pwr_index = hal->tx_pwr_tbl[path][rate];
962 struct rtw_hal *hal = &rtwdev->hal;
965 for (path = 0; path < hal->rf_path_num; path++) {
987 struct rtw_hal *hal = &rtwdev->hal;
994 return -EINVAL;
999 return -EINVAL;
1002 hal->antenna_tx = antenna_tx;
1003 hal->antenna_rx = antenna_rx;
1021 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1028 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28);
1032 dm_info->cck_fa_cnt = cck_fa_cnt;
1033 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1034 dm_info->total_fa_cnt = ofdm_fa_cnt;
1035 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
1038 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
1039 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1041 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
1042 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1044 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
1045 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1047 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
1048 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
1051 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
1052 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1055 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
1056 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1059 rtw_write32_set(rtwdev, 0x9a4, BIT(17));
1060 rtw_write32_clr(rtwdev, 0x9a4, BIT(17));
1061 rtw_write32_clr(rtwdev, 0xa2c, BIT(15));
1062 rtw_write32_set(rtwdev, 0xa2c, BIT(15));
1063 rtw_write32_set(rtwdev, 0xb58, BIT(0));
1064 rtw_write32_clr(rtwdev, 0xb58, BIT(0));
1085 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16));
1109 /* enable PTA (3-wire function form BT side) */
1124 struct rtw_coex *coex = &rtwdev->coex;
1125 struct rtw_coex_dm *coex_dm = &coex->dm;
1126 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1130 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status)
1133 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type;
1135 if (coex_rfe->ant_switch_diversity &&
1139 polarity_inverse = (coex_rfe->ant_switch_polarity == 1);
1152 if (coex_rfe->rfe_module_type != 0x4 &&
1153 coex_rfe->rfe_module_type != 0x2)
1220 struct rtw_coex *coex = &rtwdev->coex;
1221 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1222 struct rtw_efuse *efuse = &rtwdev->efuse;
1225 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
1226 coex_rfe->ant_switch_polarity = 0;
1227 coex_rfe->ant_switch_diversity = false;
1228 if (coex_rfe->rfe_module_type == 0x12 ||
1229 coex_rfe->rfe_module_type == 0x15 ||
1230 coex_rfe->rfe_module_type == 0x16)
1231 coex_rfe->ant_switch_exist = false;
1233 coex_rfe->ant_switch_exist = true;
1235 if (coex_rfe->rfe_module_type == 2 ||
1236 coex_rfe->rfe_module_type == 4) {
1243 coex_rfe->wlg_at_btg = false;
1245 if (efuse->share_ant &&
1246 coex_rfe->ant_switch_exist && !is_ext_fem)
1247 coex_rfe->ant_switch_with_bt = true;
1249 coex_rfe->ant_switch_with_bt = false;
1268 struct rtw_coex *coex = &rtwdev->coex;
1269 struct rtw_coex_dm *coex_dm = &coex->dm;
1274 if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
1277 coex_dm->cur_wl_pwr_lvl = wl_pwr;
1279 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power))
1280 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1;
1282 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl];
1290 struct rtw_coex *coex = &rtwdev->coex;
1291 struct rtw_coex_dm *coex_dm = &coex->dm;
1319 if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
1322 coex_dm->cur_wl_rx_low_gain_en = low_gain;
1324 if (coex_dm->cur_wl_rx_low_gain_en) {
1325 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
1335 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
1351 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1352 s8 delta_pwr_idx = dm_info->delta_power_index[path];
1353 u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1357 u8 swing_index = dm_info->default_ofdm_index;
1364 swing_index = dm_info->default_ofdm_index;
1367 swing_index = dm_info->default_ofdm_index +
1368 delta_pwr_idx - tx_pwr_idx_offset;
1372 if (dm_info->default_ofdm_index > abs(delta_pwr_idx))
1374 dm_info->default_ofdm_index + delta_pwr_idx;
1384 swing_index = RTW_TXSCALE_SIZE - 1;
1416 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1418 u8 channel = rtwdev->hal.current_channel;
1419 u8 band_width = rtwdev->hal.current_band_width;
1421 u8 tx_rate = dm_info->tx_rate;
1422 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1429 pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1438 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1445 power_idx_last = dm_info->delta_power_index[path];
1453 dm_info->delta_power_index[path] = power_idx_cur;
1459 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1465 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff)
1472 if (dm_info->pwr_trk_init_trigger)
1473 dm_info->pwr_trk_init_trigger = false;
1478 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
1488 struct rtw_efuse *efuse = &rtwdev->efuse;
1489 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1491 if (efuse->power_track_type != 0)
1494 if (!dm_info->pwr_trk_triggered) {
1497 dm_info->pwr_trk_triggered = true;
1502 dm_info->pwr_trk_triggered = false;
1528 if (bfee->role == RTW_BFEE_SU)
1530 else if (bfee->role == RTW_BFEE_MU)
1553 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1557 igi = dm_info->igi_history[0];
1558 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) {
1560 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL;
1562 l2h = min_t(s8, igi, dm_info->l2h_th_ini);
1563 h2l = l2h - EDCCA_L2H_H2L_DIFF;
1601 RTW_PWR_CMD_WRITE, BIT(0), 0},
1606 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1611 RTW_PWR_CMD_WRITE, BIT(0), 0},
1616 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1639 RTW_PWR_CMD_WRITE, BIT(1), 0},
1644 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1649 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1659 RTW_PWR_CMD_WRITE, BIT(5), 0},
1664 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1669 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1674 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1679 RTW_PWR_CMD_WRITE, BIT(0), 0},
1689 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1694 RTW_PWR_CMD_WRITE, BIT(7), 0},
1699 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1704 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1709 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1714 RTW_PWR_CMD_POLLING, BIT(0), 0},
1719 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1739 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1749 RTW_PWR_CMD_WRITE, BIT(2), 0},
1754 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1759 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1772 RTW_PWR_CMD_WRITE, BIT(2), 0},
1777 RTW_PWR_CMD_WRITE, BIT(3), 0},
1797 RTW_PWR_CMD_WRITE, BIT(1), 0},
1802 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1807 RTW_PWR_CMD_WRITE, BIT(1), 0},
1812 RTW_PWR_CMD_WRITE, BIT(0), 0},
1817 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1822 RTW_PWR_CMD_POLLING, BIT(1), 0},
1827 RTW_PWR_CMD_WRITE, BIT(3), 0},
1832 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1845 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1855 RTW_PWR_CMD_WRITE, BIT(5), 0},
1860 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1865 RTW_PWR_CMD_WRITE, BIT(0), 0},
1870 RTW_PWR_CMD_WRITE, BIT(5), 0},
1875 RTW_PWR_CMD_WRITE, BIT(4), 0},
1880 RTW_PWR_CMD_WRITE, BIT(0), 0},
1885 RTW_PWR_CMD_WRITE, BIT(1), 0},
1890 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1895 RTW_PWR_CMD_WRITE, BIT(2), 0},
1900 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1905 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1910 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1915 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1920 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1925 RTW_PWR_CMD_POLLING, BIT(1), 0},
1930 RTW_PWR_CMD_WRITE, BIT(1), 0},
2179 /* Shared-Antenna Coex Table */
2181 {0xffffffff, 0xffffffff}, /* case-0 */
2186 {0xfafafafa, 0xfafafafa}, /* case-5 */
2191 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2196 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2201 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2206 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2211 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2216 /* Non-Shared-Antenna Coex Table */
2218 {0xffffffff, 0xffffffff}, /* case-100 */
2223 {0xfafafafa, 0xfafafafa}, /* case-105 */
2228 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2233 {0xffff55ff, 0xffff55ff}, /* case-115 */
2238 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2244 /* Shared-Antenna TDMA */
2246 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2251 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2256 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2261 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2266 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2271 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2276 /* Non-Shared-Antenna TDMA */
2278 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2279 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2283 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2288 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2293 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2298 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2302 /* rssi in percentage % (dbm = % - 100) */
2309 {0, 16, false, 7}, /* for WL-CPT */
2318 {0, 16, false, 7}, /* for WL-CPT */
2329 {132, 26, 10},
2331 {140, 42, 10},
2334 {153, 71, 10},
2342 {122, 10, 20},
2355 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2358 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2361 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2368 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2371 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2374 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2381 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2384 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2387 8, 8, 9, 10, 11, 11, 12, 13, 14, 14,
2394 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2397 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2400 8, 9, 9, 10, 11, 12, 13, 14, 14, 15,
2407 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2413 9, 10, 10, 11, 11, 12, 12, 12, 13, 13
2419 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2424 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
2425 10, 11, 11, 12, 12, 13, 13, 14, 14, 15
2431 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2437 9, 10, 10, 11, 11, 12, 12, 12, 13, 13
2443 8, 9, 9, 9, 10, 10, 11, 11, 11, 12
2448 5, 6, 6, 7, 7, 8, 8, 9, 9, 10,
2449 10, 11, 11, 12, 12, 13, 13, 14, 14, 15
2487 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2493 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2496 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2497 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2498 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2499 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2504 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2542 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
2566 .l2h_th_ini_cs = 10 + EDCCA_IGI_BASE,
2567 .l2h_th_ini_ad = -14 + EDCCA_IGI_BASE,