Lines Matching +full:10 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
69 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_init()
72 dm_info->default_ofdm_index = RTW_DEF_OFDM_SWING_INDEX; in rtw8723d_pwrtrack_init()
74 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { in rtw8723d_pwrtrack_init()
75 ewma_thermal_init(&dm_info->avg_thermal[path]); in rtw8723d_pwrtrack_init()
76 dm_info->delta_power_index[path] = 0; in rtw8723d_pwrtrack_init()
78 dm_info->pwr_trk_triggered = false; in rtw8723d_pwrtrack_init()
79 dm_info->pwr_trk_init_trigger = true; in rtw8723d_pwrtrack_init()
80 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; in rtw8723d_pwrtrack_init()
81 dm_info->txagc_remnant_cck = 0; in rtw8723d_pwrtrack_init()
82 dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0; in rtw8723d_pwrtrack_init()
104 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8723d_phy_set_param()
108 if ((rtwdev->efuse.afe >> 4) == 14) { in rtw8723d_phy_set_param()
144 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8723d_phy_set_param()
159 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page0()
160 s8 min_rx_power = -120; in query_phy_status_page0()
163 pkt_stat->rx_power[RF_PATH_A] = pwdb - 97; in query_phy_status_page0()
164 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page0()
165 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; in query_phy_status_page0()
166 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page0()
168 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page0()
174 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in query_phy_status_page1()
176 s8 min_rx_power = -120; in query_phy_status_page1()
179 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) in query_phy_status_page1()
191 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; in query_phy_status_page1()
192 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); in query_phy_status_page1()
193 pkt_stat->bw = bw; in query_phy_status_page1()
194 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], in query_phy_status_page1()
196 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); in query_phy_status_page1()
197 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); in query_phy_status_page1()
198 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); in query_phy_status_page1()
200 dm_info->curr_rx_rate = pkt_stat->rate; in query_phy_status_page1()
201 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; in query_phy_status_page1()
202 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; in query_phy_status_page1()
203 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; in query_phy_status_page1()
205 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64); in query_phy_status_page1()
206 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ in query_phy_status_page1()
207 dm_info->rx_evm_dbm[RF_PATH_A] = rx_evm; in query_phy_status_page1()
361 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); in rtw8723d_set_channel_bb()
459 iqk_cfg->name); in rtw8723d_iqk_check_tx_failed()
489 iqk_cfg->name); in rtw8723d_iqk_check_rx_failed()
499 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000); in rtw8723d_iqk_one_shot()
508 iqk_cfg->name, tx ? "TX" : "RX", in rtw8723d_iqk_one_shot()
511 iqk_cfg->name, tx ? "TX" : "RX", in rtw8723d_iqk_one_shot()
519 rtw_warn(rtwdev, "%s %s IQK isn't done\n", iqk_cfg->name, in rtw8723d_iqk_one_shot()
528 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); in rtw8723d_iqk_txrx_path_post()
533 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0); in rtw8723d_iqk_txrx_path_post()
534 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0); in rtw8723d_iqk_txrx_path_post()
535 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0); in rtw8723d_iqk_txrx_path_post()
544 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s TXIQK!!\n", iqk_cfg->name); in rtw8723d_iqk_tx_path()
546 iqk_cfg->name, in rtw8723d_iqk_tx_path()
549 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); in rtw8723d_iqk_tx_path()
552 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); in rtw8723d_iqk_tx_path()
556 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); in rtw8723d_iqk_tx_path()
561 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, iqk_cfg->val_txiqk_pi); in rtw8723d_iqk_tx_path()
570 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); in rtw8723d_iqk_tx_path()
571 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); in rtw8723d_iqk_tx_path()
572 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3); in rtw8723d_iqk_tx_path()
576 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1); in rtw8723d_iqk_tx_path()
577 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1); in rtw8723d_iqk_tx_path()
579 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); in rtw8723d_iqk_tx_path()
580 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); in rtw8723d_iqk_tx_path()
583 iqk_cfg->name, in rtw8723d_iqk_tx_path()
586 iqk_cfg->name, in rtw8723d_iqk_tx_path()
605 iqk_cfg->name); in rtw8723d_iqk_rx_path()
607 iqk_cfg->name, in rtw8723d_iqk_rx_path()
609 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); in rtw8723d_iqk_rx_path()
629 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); in rtw8723d_iqk_rx_path()
633 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); in rtw8723d_iqk_rx_path()
636 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); in rtw8723d_iqk_rx_path()
637 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); in rtw8723d_iqk_rx_path()
638 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); in rtw8723d_iqk_rx_path()
639 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); in rtw8723d_iqk_rx_path()
642 iqk_cfg->name, in rtw8723d_iqk_rx_path()
645 iqk_cfg->name, in rtw8723d_iqk_rx_path()
664 iqk_cfg->name); in rtw8723d_iqk_rx_path()
666 iqk_cfg->name, in rtw8723d_iqk_rx_path()
683 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1); in rtw8723d_iqk_rx_path()
687 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); in rtw8723d_iqk_rx_path()
690 iqk_cfg->name, in rtw8723d_iqk_rx_path()
693 iqk_cfg->name, in rtw8723d_iqk_rx_path()
794 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path-%s standby mode!\n", in rtw8723d_iqk_rf_standby()
927 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_phy_calibration()
984 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; in rtw8723d_phy_calibration()
985 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; in rtw8723d_phy_calibration()
986 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; in rtw8723d_phy_calibration()
987 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; in rtw8723d_phy_calibration()
988 dm_info->iqk.done = true; in rtw8723d_phy_calibration()
1021 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_phy_cck_pd_set()
1025 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", in rtw8723d_phy_cck_pd_set()
1026 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); in rtw8723d_phy_cck_pd_set()
1028 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) in rtw8723d_phy_cck_pd_set()
1036 dm_info->cck_pd_default + new_lvl * 2, in rtw8723d_phy_cck_pd_set()
1037 pd[new_lvl], dm_info->cck_fa_avg); in rtw8723d_phy_cck_pd_set()
1039 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; in rtw8723d_phy_cck_pd_set()
1041 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; in rtw8723d_phy_cck_pd_set()
1044 dm_info->cck_pd_default + new_lvl * 2); in rtw8723d_phy_cck_pd_set()
1054 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0); in rtw8723d_coex_cfg_gnt_debug()
1055 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0); in rtw8723d_coex_cfg_gnt_debug()
1056 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0); in rtw8723d_coex_cfg_gnt_debug()
1057 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1058 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1059 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0); in rtw8723d_coex_cfg_gnt_debug()
1060 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0); in rtw8723d_coex_cfg_gnt_debug()
1061 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0); in rtw8723d_coex_cfg_gnt_debug()
1066 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8723d_coex_cfg_rfe_type()
1067 struct rtw_coex *coex = &rtwdev->coex; in rtw8723d_coex_cfg_rfe_type()
1068 struct rtw_coex_rfe *coex_rfe = &coex->rfe; in rtw8723d_coex_cfg_rfe_type()
1069 bool aux = efuse->bt_setting & BIT(6); in rtw8723d_coex_cfg_rfe_type()
1071 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; in rtw8723d_coex_cfg_rfe_type()
1072 coex_rfe->ant_switch_polarity = 0; in rtw8723d_coex_cfg_rfe_type()
1073 coex_rfe->ant_switch_exist = false; in rtw8723d_coex_cfg_rfe_type()
1074 coex_rfe->ant_switch_with_bt = false; in rtw8723d_coex_cfg_rfe_type()
1075 coex_rfe->ant_switch_diversity = false; in rtw8723d_coex_cfg_rfe_type()
1076 coex_rfe->wlg_at_btg = true; in rtw8723d_coex_cfg_rfe_type()
1079 if (efuse->share_ant) { in rtw8723d_coex_cfg_rfe_type()
1099 struct rtw_coex *coex = &rtwdev->coex; in rtw8723d_coex_cfg_wl_tx_power()
1100 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8723d_coex_cfg_wl_tx_power()
1104 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) in rtw8723d_coex_cfg_wl_tx_power()
1107 coex_dm->cur_wl_pwr_lvl = wl_pwr; in rtw8723d_coex_cfg_wl_tx_power()
1109 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) in rtw8723d_coex_cfg_wl_tx_power()
1110 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; in rtw8723d_coex_cfg_wl_tx_power()
1112 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; in rtw8723d_coex_cfg_wl_tx_power()
1119 struct rtw_coex *coex = &rtwdev->coex; in rtw8723d_coex_cfg_wl_rx_gain()
1120 struct rtw_coex_dm *coex_dm = &coex->dm; in rtw8723d_coex_cfg_wl_rx_gain()
1139 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) in rtw8723d_coex_cfg_wl_rx_gain()
1142 coex_dm->cur_wl_rx_low_gain_en = low_gain; in rtw8723d_coex_cfg_wl_rx_gain()
1144 if (coex_dm->cur_wl_rx_low_gain_en) { in rtw8723d_coex_cfg_wl_rx_gain()
1156 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_set_iqk_matrix_by_result()
1166 iqk_result_x = dm_info->iqk.result.s1_x; in rtw8723d_set_iqk_matrix_by_result()
1167 iqk_result_y = dm_info->iqk.result.s1_y; in rtw8723d_set_iqk_matrix_by_result()
1170 iqk_result_x = dm_info->iqk.result.s0_x; in rtw8723d_set_iqk_matrix_by_result()
1171 iqk_result_y = dm_info->iqk.result.s0_y; in rtw8723d_set_iqk_matrix_by_result()
1219 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_set_iqk_matrix()
1224 ofdm_index = RTW_OFDM_SWING_TABLE_SIZE - 1; in rtw8723d_set_iqk_matrix()
1230 if (dm_info->iqk.done) { in rtw8723d_set_iqk_matrix()
1266 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_set_ofdm_pwr()
1268 dm_info->txagc_remnant_ofdm[RF_PATH_A] = txagc_idx; in rtw8723d_pwrtrack_set_ofdm_pwr()
1277 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_set_cck_pwr()
1279 dm_info->txagc_remnant_cck = txagc_idx; in rtw8723d_pwrtrack_set_cck_pwr()
1287 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwrtrack_set()
1288 struct rtw_hal *hal = &rtwdev->hal; in rtw8723d_pwrtrack_set()
1297 dm_info->delta_power_index[path]; in rtw8723d_pwrtrack_set()
1299 dm_info->delta_power_index[path]; in rtw8723d_pwrtrack_set()
1303 final_ofdm_swing_index - limit_ofdm); in rtw8723d_pwrtrack_set()
1312 final_cck_swing_index - limit_cck); in rtw8723d_pwrtrack_set()
1319 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); in rtw8723d_pwrtrack_set()
1324 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_phy_pwrtrack()
1331 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8723d_phy_pwrtrack()
1343 if (dm_info->pwr_trk_init_trigger) in rtw8723d_phy_pwrtrack()
1344 dm_info->pwr_trk_init_trigger = false; in rtw8723d_phy_pwrtrack()
1351 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); in rtw8723d_phy_pwrtrack()
1353 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { in rtw8723d_phy_pwrtrack()
1356 delta_last = dm_info->delta_power_index[path]; in rtw8723d_phy_pwrtrack()
1362 dm_info->delta_power_index[path] = delta_cur; in rtw8723d_phy_pwrtrack()
1375 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8723d_pwr_track()
1376 struct rtw_dm_info *dm_info = &rtwdev->dm_info; in rtw8723d_pwr_track()
1378 if (efuse->power_track_type != 0) in rtw8723d_pwr_track()
1381 if (!dm_info->pwr_trk_triggered) { in rtw8723d_pwr_track()
1384 dm_info->pwr_trk_triggered = true; in rtw8723d_pwr_track()
1389 dm_info->pwr_trk_triggered = false; in rtw8723d_pwr_track()
1427 /* Shared-Antenna Coex Table */
1429 {0xffffffff, 0xffffffff}, /* case-0 */
1434 {0xfafafafa, 0xfafafafa}, /* case-5 */
1439 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1444 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1449 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1454 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1459 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1464 /* Non-Shared-Antenna Coex Table */
1466 {0xffffffff, 0xffffffff}, /* case-100 */
1471 {0xfafafafa, 0xfafafafa}, /* case-105 */
1476 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1481 {0xffff55ff, 0xffff55ff}, /* case-115 */
1486 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1492 /* Shared-Antenna TDMA */
1494 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1495 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1499 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
1504 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1509 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1514 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1519 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1524 /* Non-Shared-Antenna TDMA */
1526 { {0x00, 0x00, 0x00, 0x00, 0x01} }, /* case-100 */
1527 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
1531 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1536 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1541 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1546 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
1550 /* rssi in percentage % (dbm = % - 100) */
1562 {0, 10, false, 7}, /* for WL-CPT */
1565 {1, 10, true, 4},
1571 {0, 10, false, 7}, /* for WL-CPT */
1574 {1, 10, true, 5},
1583 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0},
1588 RTW_PWR_CMD_WRITE, BIT(0), 0},
1593 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1598 RTW_PWR_CMD_WRITE, BIT(0), 0},
1603 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0},
1608 RTW_PWR_CMD_WRITE, BIT(4), 0},
1626 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1636 RTW_PWR_CMD_WRITE, BIT(5), 0},
1641 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1646 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1651 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1656 RTW_PWR_CMD_WRITE, BIT(0), 0},
1661 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1666 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0},
1671 RTW_PWR_CMD_WRITE, BIT(7), 0},
1676 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1681 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1686 RTW_PWR_CMD_POLLING, BIT(0), 0},
1691 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1696 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1701 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1706 RTW_PWR_CMD_WRITE, BIT(1), 0},
1711 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1716 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1721 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1726 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1795 RTW_PWR_CMD_WRITE, BIT(0), 0},
1805 RTW_PWR_CMD_WRITE, BIT(1), 0},
1815 RTW_PWR_CMD_WRITE, BIT(1), 0},
1825 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1838 RTW_PWR_CMD_WRITE, BIT(2), 0},
1856 RTW_PWR_CMD_WRITE, BIT(0), 0},
1861 RTW_PWR_CMD_WRITE, BIT(1), 0},
1866 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1871 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1876 RTW_PWR_CMD_POLLING, BIT(1), 0},
1881 RTW_PWR_CMD_WRITE, BIT(6), 0},
1886 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1891 RTW_PWR_CMD_WRITE, BIT(0), 0},
1909 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1914 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1919 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)},
1924 RTW_PWR_CMD_WRITE, BIT(0), 1},
1929 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1934 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1939 RTW_PWR_CMD_POLLING, BIT(1), 0},
1952 RTW_PWR_CMD_WRITE, BIT(0), 0},
1957 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
2027 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10
2032 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10
2037 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10
2042 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10
2047 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11
2052 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11
2057 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11
2062 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11
2072 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16
2096 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8},
2098 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8},
2099 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8},
2100 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8},
2101 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8},
2107 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2109 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2110 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2113 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},