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Searched +full:0 +full:xcf8 (Results 1 – 19 of 19) sorted by relevance

/linux/arch/x86/pci/
H A Ddirect.c18 (0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
19 | (devfn << 8) | (reg & 0xFC))
33 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); in pci_conf1_read()
37 *value = inb(0xCFC + (reg & 3)); in pci_conf1_read()
40 *value = inw(0xCFC + (reg & 2)); in pci_conf1_read()
43 *value = inl(0xCFC); in pci_conf1_read()
49 return 0; in pci_conf1_read()
62 outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8); in pci_conf1_write()
66 outb((u8)value, 0xCFC + (reg & 3)); in pci_conf1_write()
69 outw((u16)value, 0xCFC + (reg & 2)); in pci_conf1_write()
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H A Dearly.c14 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config()
15 v = inl(0xcfc); in read_pci_config()
22 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_byte()
23 v = inb(0xcfc + (offset&3)); in read_pci_config_byte()
30 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in read_pci_config_16()
31 v = inw(0xcfc + (offset&2)); in read_pci_config_16()
38 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config()
39 outl(val, 0xcfc); in write_pci_config()
44 outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8); in write_pci_config_byte()
45 outb(val, 0xcfc + (offset&3)); in write_pci_config_byte()
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H A Dxen.c7 * 0xcf8 PCI configuration read/write.
50 share = 0; in xen_pcifront_enable_irq()
53 if (rc < 0) { in xen_pcifront_enable_irq()
61 return 0; in xen_pcifront_enable_irq()
69 int shareable = 0; in xen_register_pirq()
73 if (irq > 0) in xen_register_pirq()
91 shareable = 0; in xen_register_pirq()
99 if (irq < 0) in xen_register_pirq()
132 setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1); in xen_register_gsi()
133 setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1); in xen_register_gsi()
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/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,xrx200-net.yaml14 pattern: "^ethernet@[0-9a-f]+$"
36 const: 0
52 #size-cells = <0>;
54 reg = <0xe10b308 0xcf8>;
/linux/drivers/virt/acrn/
H A Dioreq.c43 int ret = 0; in ioreq_complete_request()
65 if (ret < 0) in ioreq_complete_request()
95 int ret = 0; in acrn_ioreq_request_default_complete()
113 * Return: 0 on success, <0 on error
122 "Invalid IO range [0x%llx,0x%llx]\n", start, end); in acrn_ioreq_range_add()
138 return 0; in acrn_ioreq_range_add()
194 if (ret < 0) { in ioreq_task()
203 return 0; in ioreq_task()
240 } while (has_pending && --retry > 0); in acrn_ioreq_request_clear()
241 if (retry == 0) in acrn_ioreq_request_clear()
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/linux/arch/x86/kernel/
H A Dreboot_fixups_32.c20 /* writing 1 to the reset control register, 0x44 causes the in cs5530a_warm_reset()
22 pci_write_config_byte(dev, 0x44, 0x1); in cs5530a_warm_reset()
38 outl(0x80003840, 0xCF8); in rdc321x_reset()
40 i = inl(0xCFC); in rdc321x_reset()
42 i |= 0x1600; in rdc321x_reset()
43 outl(i, 0xCFC); in rdc321x_reset()
44 outb(1, 0x92); in rdc321x_reset()
51 for (i = 0; i < 10; i++) { in ce4100_reset()
52 outb(0x2, 0xcf9); in ce4100_reset()
66 #define PCI_DEVICE_ID_INTEL_CE4100 0x0708
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/linux/arch/mips/pci/
H A Dops-sni.c19 * test for bus 0 and hope forwarding and decoding work properly for any
29 if (busno == 0 && devfn >= PCI_DEVFN(8, 0)) in set_config_address()
33 ((busno & 0xff) << 16) | in set_config_address()
34 ((devfn & 0xff) << 8) | in set_config_address()
35 (reg & 0xfc); in set_config_address()
60 return 0; in pcimt_read()
83 return 0; in pcimt_write()
96 outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); in pcit_set_config_address()
106 * on bus 0 we need to check, whether there is a device answering in pcit_read()
110 if (bus->number == 0) { in pcit_read()
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/linux/drivers/net/wireless/marvell/mwifiex/
H A Dpcie.h27 #define PCIE_VENDOR_ID_MARVELL (0x11ab)
28 #define PCIE_VENDOR_ID_V2_MARVELL (0x1b4b)
29 #define PCIE_DEVICE_ID_MARVELL_88W8766P (0x2b30)
30 #define PCIE_DEVICE_ID_MARVELL_88W8897 (0x2b38)
31 #define PCIE_DEVICE_ID_MARVELL_88W8997 (0x2b42)
33 #define PCIE8897_A0 0x1100
34 #define PCIE8897_B0 0x1200
35 #define PCIE8997_A0 0x10
36 #define PCIE8997_A1 0x11
37 #define CHIP_VER_PCIEUART 0x3
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/linux/arch/mips/sni/
H A Dpcit.c32 PORT(0x3f8, 0),
33 PORT(0x2f8, 3),
46 PORT(0x3f8, 0),
47 PORT(0x2f8, 3),
48 PORT(0x3e8, 4),
49 PORT(0x2e8, 3),
63 .start = 0x70,
64 .end = 0x71,
86 .start = 0x00000000UL,
87 .end = 0x03bfffffUL,
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/linux/drivers/watchdog/
H A Dibmasr.c36 #define TOPAZ_ASR_TOGGLE 0x40
37 #define TOPAZ_ASR_DISABLE 0x80
40 #define PEARL_BASE 0xe04
41 #define PEARL_WRITE 0xe06
42 #define PEARL_READ 0xe07
44 #define PEARL_ASR_DISABLE_MASK 0x80 /* bit 7: disable = 1, enable = 0 */
45 #define PEARL_ASR_TOGGLE_MASK 0x40 /* bit 6: 0, then 1, then 0 */
48 #define JASPER_ASR_REG_OFFSET 0x38
50 #define JASPER_ASR_DISABLE_MASK 0x01 /* bit 0: disable = 1, enable = 0 */
51 #define JASPER_ASR_TOGGLE_MASK 0x02 /* bit 1: 0, then 1, then 0 */
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/linux/arch/mips/include/asm/ip32/
H A Dmace.h18 #define MACE_BASE 0x1f000000 /* physical */
43 #define MACEPCI_ERROR_DEVSEL_MASK 0xc0
44 #define MACEPCI_ERROR_DEVSEL_FAST 0
45 #define MACEPCI_ERROR_DEVSEL_MED 0x40
46 #define MACEPCI_ERROR_DEVSEL_SLOW 0x80
48 #define MACEPCI_ERROR_66MHZ BIT(0)
51 #define MACEPCI_CONTROL_INT_MASK 0xff
61 #define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
71 unsigned int _pad[0xcf8/4 - 4];
79 #define MACEPCI_LOW_MEMORY 0x1a000000
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/linux/arch/mips/include/asm/
H A Dgt64120.h21 #define GT_CPU_OFS 0x000
23 #define GT_MULTI_OFS 0x120
26 #define GT_SCS10LD_OFS 0x008
27 #define GT_SCS10HD_OFS 0x010
28 #define GT_SCS32LD_OFS 0x018
29 #define GT_SCS32HD_OFS 0x020
30 #define GT_CS20LD_OFS 0x028
31 #define GT_CS20HD_OFS 0x030
32 #define GT_CS3BOOTLD_OFS 0x038
33 #define GT_CS3BOOTHD_OFS 0x040
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/linux/drivers/memory/tegra/
H A Dtegra210-emc.h21 #define EMC_INTSTATUS 0x0
23 #define EMC_DBG 0x8
26 #define EMC_CFG 0xc
31 #define EMC_PIN 0x24
32 #define EMC_PIN_PIN_CKE BIT(0)
35 #define EMC_TIMING_CONTROL 0x28
36 #define EMC_RC 0x2c
37 #define EMC_RFC 0x30
38 #define EMC_RAS 0x34
39 #define EMC_RP 0x38
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_ptp_hw.h133 #define ICE_ETH56G_MAC_CFG_RX_OFFSET_FRAC GENMASK(8, 0)
224 ICE_RCLKA_PIN = 0, /* SCL pin */
234 ZL_REF0P = 0,
248 ZL_OUT0 = 0,
259 SI_REF0P = 0,
271 SI_OUT0 = 0,
328 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
429 #define ICE_ETH56G_NOMINAL_INCVAL 0x140000000ULL
430 #define ICE_ETH56G_NOMINAL_PCS_REF_TUS 0x100000000ULL
431 #define ICE_ETH56G_NOMINAL_PCS_REF_INC 0x300000000ULL
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/linux/arch/x86/xen/
H A Denlighten_pv.c145 eax = cpuid_eax(0x80000000); in xen_set_mtrr_data()
146 if ((eax >> 16) == 0x8000 && eax >= 0x80000008) { in xen_set_mtrr_data()
147 eax = cpuid_eax(0x80000008); in xen_set_mtrr_data()
148 width = eax & 0xff; in xen_set_mtrr_data()
151 for (reg = 0; reg < MTRR_MAX_VAR_RANGES; reg++) { in xen_set_mtrr_data()
190 xen_vcpu_info_reset(0); in xen_pv_init_platform()
198 mtrr_overwrite_state(NULL, 0, MTRR_TYPE_WRBACK); in xen_pv_init_platform()
218 unsigned int maskebx = ~0; in xen_cpuid()
219 unsigned int or_ebx = 0; in xen_cpuid()
226 case 0x1: in xen_cpuid()
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/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dregs.h33 #define A_SG_CONTROL 0x0
35 #define S_CMDQ0_ENABLE 0
60 #define M_CMDQ_PRIORITY 0x3
93 #define M_RX_PKT_OFFSET 0x7
101 #define A_SG_DOORBELL 0x4
102 #define A_SG_CMD0BASELWR 0x8
103 #define A_SG_CMD0BASEUPR 0xc
104 #define A_SG_CMD1BASELWR 0x10
105 #define A_SG_CMD1BASEUPR 0x14
106 #define A_SG_FL0BASELWR 0x18
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/linux/drivers/clk/tegra/
H A Dclk-tegra210.c33 #define CLK_SOURCE_CSITE 0x1d4
34 #define CLK_SOURCE_EMC 0x19c
35 #define CLK_SOURCE_SOR1 0x410
36 #define CLK_SOURCE_SOR0 0x414
37 #define CLK_SOURCE_LA 0x1f8
38 #define CLK_SOURCE_SDMMC2 0x154
39 #define CLK_SOURCE_SDMMC4 0x164
40 #define CLK_SOURCE_EMC_DLL 0x664
42 #define PLLC_BASE 0x80
43 #define PLLC_OUT 0x84
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/linux/Documentation/admin-guide/
H A Dkernel-parameters.txt36 1,0: use 1st APIC table
37 default: 0
77 acpi.debug_layer=0x20000000
80 acpi.debug_layer=0xffffffff acpi.debug_level=0x2
82 acpi.debug_layer=0x2 acpi.debug_level=0xffffffff
291 behaviour to be specified. Bit 0 enables warnings,
376 to bias toward performance (0x0) or energy efficiency (0xff)
420 bsp: External NMI is delivered only to CPU 0
422 backup of CPU 0
434 Format: { "0" | "1" }
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/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
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