43 	int ret = 0;  in ioreq_complete_request()
65 		if (ret < 0)  in ioreq_complete_request()
95 	int ret = 0;  in acrn_ioreq_request_default_complete()
113  * Return: 0 on success, <0 on error
122 			"Invalid IO range [0x%llx,0x%llx]\n", start, end);  in acrn_ioreq_range_add()
138 	return 0;  in acrn_ioreq_range_add()
194 			if (ret < 0) {  in ioreq_task()
203 	return 0;  in ioreq_task()
240 	} while (has_pending && --retry > 0);  in acrn_ioreq_request_clear()
241 	if (retry == 0)  in acrn_ioreq_request_clear()
277 	return 0;  in acrn_ioreq_client_wait()
283 		(req->reqs.pio_request.address == 0xcf8));  in is_cfg_addr()
289 		((req->reqs.pio_request.address >= 0xcfc) &&  in is_cfg_data()
290 		 (req->reqs.pio_request.address < (0xcfc + 4))));  in is_cfg_data()
294 #define PCI_LOWREG_MASK  0xFC
296 #define PCI_HIGHREG_MASK 0xF00
303 #define CONF1_ENABLE	0x80000000UL
305  * A PCI configuration space access via PIO 0xCF8 and 0xCFC normally has two
307  *   1) writes address into 0xCF8 port
308  *   2) accesses data in/from 0xCFC
329 				req->reqs.pio_request.value = 0xffffffff;  in handle_cf8cfc()
332 			offset = req->reqs.pio_request.address - 0xcfc;  in handle_cf8cfc()
503 	for (i = 0; i < vm->vcpu_num; i++) {  in acrn_ioreq_dispatch()
528 				req->kernel_handled = 0;  in acrn_ioreq_dispatch()
541 	return 0;  in acrn_ioreq_dispatch()
586 	return 0;  in acrn_ioreq_intr_setup()
621 	if (ret < 0) {  in acrn_ioreq_init()
630 	ret = 0;  in acrn_ioreq_init()