Lines Matching +full:0 +full:xcf8
21 #define GT_CPU_OFS 0x000
23 #define GT_MULTI_OFS 0x120
26 #define GT_SCS10LD_OFS 0x008
27 #define GT_SCS10HD_OFS 0x010
28 #define GT_SCS32LD_OFS 0x018
29 #define GT_SCS32HD_OFS 0x020
30 #define GT_CS20LD_OFS 0x028
31 #define GT_CS20HD_OFS 0x030
32 #define GT_CS3BOOTLD_OFS 0x038
33 #define GT_CS3BOOTHD_OFS 0x040
34 #define GT_PCI0IOLD_OFS 0x048
35 #define GT_PCI0IOHD_OFS 0x050
36 #define GT_PCI0M0LD_OFS 0x058
37 #define GT_PCI0M0HD_OFS 0x060
38 #define GT_ISD_OFS 0x068
40 #define GT_PCI0M1LD_OFS 0x080
41 #define GT_PCI0M1HD_OFS 0x088
42 #define GT_PCI1IOLD_OFS 0x090
43 #define GT_PCI1IOHD_OFS 0x098
44 #define GT_PCI1M0LD_OFS 0x0a0
45 #define GT_PCI1M0HD_OFS 0x0a8
46 #define GT_PCI1M1LD_OFS 0x0b0
47 #define GT_PCI1M1HD_OFS 0x0b8
48 #define GT_PCI1M1LD_OFS 0x0b0
49 #define GT_PCI1M1HD_OFS 0x0b8
51 #define GT_SCS10AR_OFS 0x0d0
52 #define GT_SCS32AR_OFS 0x0d8
53 #define GT_CS20R_OFS 0x0e0
54 #define GT_CS3BOOTR_OFS 0x0e8
56 #define GT_PCI0IOREMAP_OFS 0x0f0
57 #define GT_PCI0M0REMAP_OFS 0x0f8
58 #define GT_PCI0M1REMAP_OFS 0x100
59 #define GT_PCI1IOREMAP_OFS 0x108
60 #define GT_PCI1M0REMAP_OFS 0x110
61 #define GT_PCI1M1REMAP_OFS 0x118
64 #define GT_CPUERR_ADDRLO_OFS 0x070
65 #define GT_CPUERR_ADDRHI_OFS 0x078
67 #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */
68 #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */
69 #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */
72 #define GT_PCI0SYNC_OFS 0x0c0
73 #define GT_PCI1SYNC_OFS 0x0c8
76 #define GT_SCS0LD_OFS 0x400
77 #define GT_SCS0HD_OFS 0x404
78 #define GT_SCS1LD_OFS 0x408
79 #define GT_SCS1HD_OFS 0x40c
80 #define GT_SCS2LD_OFS 0x410
81 #define GT_SCS2HD_OFS 0x414
82 #define GT_SCS3LD_OFS 0x418
83 #define GT_SCS3HD_OFS 0x41c
84 #define GT_CS0LD_OFS 0x420
85 #define GT_CS0HD_OFS 0x424
86 #define GT_CS1LD_OFS 0x428
87 #define GT_CS1HD_OFS 0x42c
88 #define GT_CS2LD_OFS 0x430
89 #define GT_CS2HD_OFS 0x434
90 #define GT_CS3LD_OFS 0x438
91 #define GT_CS3HD_OFS 0x43c
92 #define GT_BOOTLD_OFS 0x440
93 #define GT_BOOTHD_OFS 0x444
95 #define GT_ADERR_OFS 0x470
98 #define GT_SDRAM_CFG_OFS 0x448
100 #define GT_SDRAM_OPMODE_OFS 0x474
101 #define GT_SDRAM_BM_OFS 0x478
102 #define GT_SDRAM_ADDRDECODE_OFS 0x47c
105 #define GT_SDRAM_B0_OFS 0x44c
106 #define GT_SDRAM_B1_OFS 0x450
107 #define GT_SDRAM_B2_OFS 0x454
108 #define GT_SDRAM_B3_OFS 0x458
111 #define GT_DEV_B0_OFS 0x45c
112 #define GT_DEV_B1_OFS 0x460
113 #define GT_DEV_B2_OFS 0x464
114 #define GT_DEV_B3_OFS 0x468
115 #define GT_DEV_BOOT_OFS 0x46c
118 #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */
119 #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */
120 #define GT_ECC_MEM 0x488 /* GT-64120A only */
121 #define GT_ECC_CALC 0x48c /* GT-64120A only */
122 #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */
125 #define GT_DMA0_CNT_OFS 0x800
126 #define GT_DMA1_CNT_OFS 0x804
127 #define GT_DMA2_CNT_OFS 0x808
128 #define GT_DMA3_CNT_OFS 0x80c
129 #define GT_DMA0_SA_OFS 0x810
130 #define GT_DMA1_SA_OFS 0x814
131 #define GT_DMA2_SA_OFS 0x818
132 #define GT_DMA3_SA_OFS 0x81c
133 #define GT_DMA0_DA_OFS 0x820
134 #define GT_DMA1_DA_OFS 0x824
135 #define GT_DMA2_DA_OFS 0x828
136 #define GT_DMA3_DA_OFS 0x82c
137 #define GT_DMA0_NEXT_OFS 0x830
138 #define GT_DMA1_NEXT_OFS 0x834
139 #define GT_DMA2_NEXT_OFS 0x838
140 #define GT_DMA3_NEXT_OFS 0x83c
142 #define GT_DMA0_CUR_OFS 0x870
143 #define GT_DMA1_CUR_OFS 0x874
144 #define GT_DMA2_CUR_OFS 0x878
145 #define GT_DMA3_CUR_OFS 0x87c
148 #define GT_DMA0_CTRL_OFS 0x840
149 #define GT_DMA1_CTRL_OFS 0x844
150 #define GT_DMA2_CTRL_OFS 0x848
151 #define GT_DMA3_CTRL_OFS 0x84c
154 #define GT_DMA_ARB_OFS 0x860
157 #define GT_TC0_OFS 0x850
158 #define GT_TC1_OFS 0x854
159 #define GT_TC2_OFS 0x858
160 #define GT_TC3_OFS 0x85c
162 #define GT_TC_CONTROL_OFS 0x864
165 #define GT_PCI0_CMD_OFS 0xc00
166 #define GT_PCI0_TOR_OFS 0xc04
167 #define GT_PCI0_BS_SCS10_OFS 0xc08
168 #define GT_PCI0_BS_SCS32_OFS 0xc0c
169 #define GT_PCI0_BS_CS20_OFS 0xc10
170 #define GT_PCI0_BS_CS3BT_OFS 0xc14
172 #define GT_PCI1_IACK_OFS 0xc30
173 #define GT_PCI0_IACK_OFS 0xc34
175 #define GT_PCI0_BARE_OFS 0xc3c
176 #define GT_PCI0_PREFMBR_OFS 0xc40
178 #define GT_PCI0_SCS10_BAR_OFS 0xc48
179 #define GT_PCI0_SCS32_BAR_OFS 0xc4c
180 #define GT_PCI0_CS20_BAR_OFS 0xc50
181 #define GT_PCI0_CS3BT_BAR_OFS 0xc54
182 #define GT_PCI0_SSCS10_BAR_OFS 0xc58
183 #define GT_PCI0_SSCS32_BAR_OFS 0xc5c
185 #define GT_PCI0_SCS3BT_BAR_OFS 0xc64
187 #define GT_PCI1_CMD_OFS 0xc80
188 #define GT_PCI1_TOR_OFS 0xc84
189 #define GT_PCI1_BS_SCS10_OFS 0xc88
190 #define GT_PCI1_BS_SCS32_OFS 0xc8c
191 #define GT_PCI1_BS_CS20_OFS 0xc90
192 #define GT_PCI1_BS_CS3BT_OFS 0xc94
194 #define GT_PCI1_BARE_OFS 0xcbc
195 #define GT_PCI1_PREFMBR_OFS 0xcc0
197 #define GT_PCI1_SCS10_BAR_OFS 0xcc8
198 #define GT_PCI1_SCS32_BAR_OFS 0xccc
199 #define GT_PCI1_CS20_BAR_OFS 0xcd0
200 #define GT_PCI1_CS3BT_BAR_OFS 0xcd4
201 #define GT_PCI1_SSCS10_BAR_OFS 0xcd8
202 #define GT_PCI1_SSCS32_BAR_OFS 0xcdc
204 #define GT_PCI1_SCS3BT_BAR_OFS 0xce4
206 #define GT_PCI1_CFGADDR_OFS 0xcf0
207 #define GT_PCI1_CFGDATA_OFS 0xcf4
208 #define GT_PCI0_CFGADDR_OFS 0xcf8
209 #define GT_PCI0_CFGDATA_OFS 0xcfc
212 #define GT_INTRCAUSE_OFS 0xc18
213 #define GT_INTRMASK_OFS 0xc1c
215 #define GT_PCI0_ICMASK_OFS 0xc24
216 #define GT_PCI0_SERR0MASK_OFS 0xc28
218 #define GT_CPU_INTSEL_OFS 0xc70
219 #define GT_PCI0_INTSEL_OFS 0xc74
221 #define GT_HINTRCAUSE_OFS 0xc98
222 #define GT_HINTRMASK_OFS 0xc9c
224 #define GT_PCI0_HICMASK_OFS 0xca4
225 #define GT_PCI1_SERR1MASK_OFS 0xca8
231 #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
232 #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
233 #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
234 #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c
235 #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
236 #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
237 #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
238 #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c
239 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
240 #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
241 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
242 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
243 #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
244 #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
245 #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
246 #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
247 #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
248 #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c
249 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
250 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
251 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
252 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c
254 #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10
255 #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14
256 #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18
257 #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c
258 #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20
259 #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24
260 #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28
261 #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c
262 #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30
263 #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34
264 #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40
265 #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44
266 #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50
267 #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54
268 #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60
269 #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64
270 #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68
271 #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c
272 #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70
273 #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74
274 #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78
275 #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c
286 #define GT_CPU_WR_DXDXDXDX 0
291 #define GT_PCI_LD_SHF 0
293 #define GT_PCI_HD_SHF 0
295 #define GT_PCI_REMAP_SHF 0
320 #define GT_SDRAM_BM_ORDER_LIN 0
322 #define GT_SDRAM_BM_RSVD_ALL1 0xffb
325 #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
327 #define GT_SDRAM_ADDRDECODE_ADDR_0 0
337 #define GT_SDRAM_B0_CASLAT_SHF 0
349 #define GT_SDRAM_B0_SRASPRCHG_2 0
359 #define GT_SDRAM_B0_64BITINT_2 0
365 #define GT_SDRAM_B0_BW_32 0
383 #define GT_SDRAM_B0_SRAS2SCAS_2 0
389 #define GT_SDRAM_B0_SIZE_16M 0
399 #define GT_SDRAM_B0_BLEN_8 0
403 #define GT_SDRAM_CFG_REFINT_SHF 0
434 #define GT_SDRAM_OPMODE_OP_SHF 0
436 #define GT_SDRAM_OPMODE_OP_NORMAL 0
442 #define GT_TC_CONTROL_ENTC0_SHF 0
450 #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
508 #define GT_PCI0_CMD_MBYTESWAP_SHF 0
531 #define GT_DEF_PCI0_IO_BASE 0x10000000UL
532 #define GT_DEF_PCI0_IO_SIZE 0x02000000UL
533 #define GT_DEF_PCI0_MEM0_BASE 0x12000000UL
534 #define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL
535 #define GT_DEF_BASE 0x14000000UL
559 do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)