Lines Matching +full:0 +full:xcf8
21 #define EMC_INTSTATUS 0x0
23 #define EMC_DBG 0x8
26 #define EMC_CFG 0xc
31 #define EMC_PIN 0x24
32 #define EMC_PIN_PIN_CKE BIT(0)
35 #define EMC_TIMING_CONTROL 0x28
36 #define EMC_RC 0x2c
37 #define EMC_RFC 0x30
38 #define EMC_RAS 0x34
39 #define EMC_RP 0x38
40 #define EMC_R2W 0x3c
41 #define EMC_W2R 0x40
42 #define EMC_R2P 0x44
43 #define EMC_W2P 0x48
44 #define EMC_RD_RCD 0x4c
45 #define EMC_WR_RCD 0x50
46 #define EMC_RRD 0x54
47 #define EMC_REXT 0x58
48 #define EMC_WDV 0x5c
49 #define EMC_QUSE 0x60
50 #define EMC_QRST 0x64
51 #define EMC_QSAFE 0x68
52 #define EMC_RDV 0x6c
53 #define EMC_REFRESH 0x70
54 #define EMC_BURST_REFRESH_NUM 0x74
55 #define EMC_PDEX2WR 0x78
56 #define EMC_PDEX2RD 0x7c
57 #define EMC_PCHG2PDEN 0x80
58 #define EMC_ACT2PDEN 0x84
59 #define EMC_AR2PDEN 0x88
60 #define EMC_RW2PDEN 0x8c
61 #define EMC_TXSR 0x90
62 #define EMC_TCKE 0x94
63 #define EMC_TFAW 0x98
64 #define EMC_TRPAB 0x9c
65 #define EMC_TCLKSTABLE 0xa0
66 #define EMC_TCLKSTOP 0xa4
67 #define EMC_TREFBW 0xa8
68 #define EMC_TPPD 0xac
69 #define EMC_ODT_WRITE 0xb0
70 #define EMC_PDEX2MRR 0xb4
71 #define EMC_WEXT 0xb8
72 #define EMC_RFC_SLR 0xc0
73 #define EMC_MRS_WAIT_CNT2 0xc4
75 #define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT 0
76 #define EMC_MRS_WAIT_CNT 0xc8
77 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
79 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
81 #define EMC_MRS 0xcc
82 #define EMC_EMRS 0xd0
84 #define EMC_REF 0xd4
85 #define EMC_REF_REF_CMD BIT(0)
86 #define EMC_SELF_REF 0xe0
87 #define EMC_MRW 0xe8
88 #define EMC_MRW_MRW_OP_SHIFT 0
90 (0xff << EMC_MRW_MRW_OP_SHIFT)
95 #define EMC_MRR 0xec
97 #define EMC_MRR_DEV_SEL_MASK 0x3
99 #define EMC_MRR_MA_MASK 0xff
100 #define EMC_MRR_DATA_SHIFT 0
101 #define EMC_MRR_DATA_MASK 0xffff
103 #define EMC_FBIO_SPARE 0x100
104 #define EMC_FBIO_CFG5 0x104
105 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
107 (0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT)
110 #define EMC_PDEX2CKE 0x118
111 #define EMC_CKE2PDEN 0x11c
112 #define EMC_MPC 0x128
113 #define EMC_EMRS2 0x12c
115 #define EMC_MRW2 0x134
116 #define EMC_MRW3 0x138
117 #define EMC_MRW4 0x13c
118 #define EMC_R2R 0x144
119 #define EMC_EINPUT 0x14c
120 #define EMC_EINPUT_DURATION 0x150
121 #define EMC_PUTERM_EXTRA 0x154
122 #define EMC_TCKESR 0x158
123 #define EMC_TPD 0x15c
124 #define EMC_AUTO_CAL_CONFIG 0x2a4
125 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START BIT(0)
130 #define EMC_EMC_STATUS 0x2b4
135 (0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT)
138 (0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT)
140 #define EMC_CFG_2 0x2b8
141 #define EMC_CFG_DIG_DLL 0x2bc
142 #define EMC_CFG_DIG_DLL_CFG_DLL_EN BIT(0)
148 (0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT)
151 (0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT)
153 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
154 #define EMC_DIG_DLL_STATUS 0x2c4
157 #define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0
159 (0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT)
161 #define EMC_CFG_DIG_DLL_1 0x2c8
162 #define EMC_RDV_MASK 0x2cc
163 #define EMC_WDV_MASK 0x2d0
164 #define EMC_RDV_EARLY_MASK 0x2d4
165 #define EMC_RDV_EARLY 0x2d8
166 #define EMC_AUTO_CAL_CONFIG8 0x2dc
167 #define EMC_ZCAL_INTERVAL 0x2e0
168 #define EMC_ZCAL_WAIT_CNT 0x2e4
169 #define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK 0x7ff
170 #define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT 0
172 #define EMC_ZQ_CAL 0x2ec
176 #define EMC_ZQ_CAL_ZQ_CAL_CMD BIT(0)
177 #define EMC_FDPD_CTRL_DQ 0x310
178 #define EMC_FDPD_CTRL_CMD 0x314
179 #define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318
180 #define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c
181 #define EMC_PMACRO_BRICK_CTRL_RFU1 0x330
182 #define EMC_PMACRO_BRICK_CTRL_RFU2 0x334
183 #define EMC_TR_TIMING_0 0x3b4
184 #define EMC_TR_CTRL_1 0x3bc
185 #define EMC_TR_RDV 0x3c4
186 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
187 #define EMC_SEL_DPD_CTRL 0x3d8
193 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
194 #define EMC_DYN_SELF_REF_CONTROL 0x3e0
195 #define EMC_TXSRDLL 0x3e4
196 #define EMC_CCFIFO_ADDR 0x3e8
198 #define EMC_CCFIFO_ADDR_STALL(x) (((x) & 0x7fff) << 16)
199 #define EMC_CCFIFO_ADDR_OFFSET(x) ((x) & 0xffff)
200 #define EMC_CCFIFO_DATA 0x3ec
201 #define EMC_TR_QPOP 0x3f4
202 #define EMC_TR_RDV_MASK 0x3f8
203 #define EMC_TR_QSAFE 0x3fc
204 #define EMC_TR_QRST 0x400
205 #define EMC_ISSUE_QRST 0x428
206 #define EMC_AUTO_CAL_CONFIG2 0x458
207 #define EMC_AUTO_CAL_CONFIG3 0x45c
208 #define EMC_TR_DVFS 0x460
209 #define EMC_AUTO_CAL_CHANNEL 0x464
210 #define EMC_IBDLY 0x468
211 #define EMC_OBDLY 0x46c
212 #define EMC_TXDSRVTTGEN 0x480
213 #define EMC_WE_DURATION 0x48c
214 #define EMC_WS_DURATION 0x490
215 #define EMC_WEV 0x494
216 #define EMC_WSV 0x498
217 #define EMC_CFG_3 0x49c
218 #define EMC_MRW6 0x4a4
219 #define EMC_MRW7 0x4a8
220 #define EMC_MRW8 0x4ac
221 #define EMC_MRW9 0x4b0
222 #define EMC_MRW10 0x4b4
223 #define EMC_MRW11 0x4b8
224 #define EMC_MRW12 0x4bc
225 #define EMC_MRW13 0x4c0
226 #define EMC_MRW14 0x4c4
227 #define EMC_MRW15 0x4d0
228 #define EMC_CFG_SYNC 0x4d4
229 #define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8
230 #define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE BIT(0)
231 #define EMC_WDV_CHK 0x4e0
232 #define EMC_CFG_PIPE_2 0x554
233 #define EMC_CFG_PIPE_CLK 0x558
234 #define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON BIT(0)
235 #define EMC_CFG_PIPE_1 0x55c
236 #define EMC_CFG_PIPE 0x560
237 #define EMC_QPOP 0x564
238 #define EMC_QUSE_WIDTH 0x568
239 #define EMC_PUTERM_WIDTH 0x56c
240 #define EMC_AUTO_CAL_CONFIG7 0x574
241 #define EMC_REFCTRL2 0x580
242 #define EMC_FBIO_CFG7 0x584
245 #define EMC_DATA_BRLSHFT_0 0x588
248 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT)
251 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT)
254 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT)
257 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT)
260 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT)
263 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT)
266 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT)
267 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0
269 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT)
271 #define EMC_DATA_BRLSHFT_1 0x58c
274 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT)
277 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT)
280 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT)
283 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT)
286 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT)
289 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT)
292 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT)
293 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0
295 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT)
297 #define EMC_RFCPB 0x590
298 #define EMC_DQS_BRLSHFT_0 0x594
299 #define EMC_DQS_BRLSHFT_1 0x598
300 #define EMC_CMD_BRLSHFT_0 0x59c
301 #define EMC_CMD_BRLSHFT_1 0x5a0
302 #define EMC_CMD_BRLSHFT_2 0x5a4
303 #define EMC_CMD_BRLSHFT_3 0x5a8
304 #define EMC_QUSE_BRLSHFT_0 0x5ac
305 #define EMC_AUTO_CAL_CONFIG4 0x5b0
306 #define EMC_AUTO_CAL_CONFIG5 0x5b4
307 #define EMC_QUSE_BRLSHFT_1 0x5b8
308 #define EMC_QUSE_BRLSHFT_2 0x5bc
309 #define EMC_CCDMW 0x5c0
310 #define EMC_QUSE_BRLSHFT_3 0x5c4
311 #define EMC_AUTO_CAL_CONFIG6 0x5cc
312 #define EMC_DLL_CFG_0 0x5e4
313 #define EMC_DLL_CFG_1 0x5e8
316 (0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT)
318 #define EMC_CONFIG_SAMPLE_DELAY 0x5f0
319 #define EMC_CFG_UPDATE 0x5f4
322 (0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT)
324 #define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600
325 #define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604
326 #define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608
327 #define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c
328 #define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610
329 #define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614
330 #define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620
331 #define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624
332 #define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628
333 #define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c
334 #define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630
335 #define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634
336 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640
340 (0x3ff << \
343 0
345 (0x3ff << \
348 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644
352 (0x3ff << \
355 0
357 (0x3ff << \
360 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648
364 (0x3ff << \
367 0
369 (0x3ff << \
372 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c
376 (0x3ff << \
379 0
381 (0x3ff << \
384 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650
385 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654
386 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660
390 (0x3ff << \
393 0
395 (0x3ff << \
398 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664
402 (0x3ff << \
405 0
407 (0x3ff << \
410 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668
414 (0x3ff << \
417 0
419 (0x3ff << \
422 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c
426 (0x3ff << \
429 0
431 (0x3ff << \
434 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670
435 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674
436 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680
437 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684
438 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688
439 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c
440 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690
441 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694
442 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0
443 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4
444 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8
445 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac
446 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0
447 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4
448 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0
449 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4
450 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8
451 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc
452 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0
453 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4
454 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8
455 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec
456 #define EMC_PMACRO_TX_PWRD_0 0x720
457 #define EMC_PMACRO_TX_PWRD_1 0x724
458 #define EMC_PMACRO_TX_PWRD_2 0x728
459 #define EMC_PMACRO_TX_PWRD_3 0x72c
460 #define EMC_PMACRO_TX_PWRD_4 0x730
461 #define EMC_PMACRO_TX_PWRD_5 0x734
462 #define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740
463 #define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744
464 #define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c
465 #define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748
466 #define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750
467 #define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754
468 #define EMC_PMACRO_DDLL_BYPASS 0x760
469 #define EMC_PMACRO_DDLL_PWRD_0 0x770
470 #define EMC_PMACRO_DDLL_PWRD_1 0x774
471 #define EMC_PMACRO_DDLL_PWRD_2 0x778
472 #define EMC_PMACRO_CMD_CTRL_0 0x780
473 #define EMC_PMACRO_CMD_CTRL_1 0x784
474 #define EMC_PMACRO_CMD_CTRL_2 0x788
475 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800
476 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804
477 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808
478 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c
479 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810
480 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814
481 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818
482 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c
483 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820
484 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824
485 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828
486 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c
487 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830
488 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834
489 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838
490 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c
491 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840
492 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844
493 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848
494 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c
495 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850
496 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854
497 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858
498 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c
499 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860
500 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864
501 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868
502 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c
503 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870
504 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874
505 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878
506 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c
507 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880
508 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884
509 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888
510 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c
511 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890
512 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894
513 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898
514 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c
515 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0
516 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4
517 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8
518 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac
519 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0
520 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4
521 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8
522 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc
523 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900
524 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904
525 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908
526 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c
527 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910
528 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914
529 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918
530 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c
531 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920
532 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924
533 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928
534 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c
535 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930
536 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934
537 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938
538 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c
539 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940
540 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944
541 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948
542 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c
543 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950
544 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954
545 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958
546 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c
547 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960
548 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964
549 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968
550 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c
551 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970
552 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974
553 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978
554 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c
555 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980
556 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984
557 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988
558 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c
559 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990
560 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994
561 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998
562 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c
563 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0
564 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4
565 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8
566 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac
567 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0
568 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4
569 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8
570 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc
571 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00
572 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04
573 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08
574 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10
575 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14
576 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18
577 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20
578 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24
579 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28
580 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30
581 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34
582 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38
583 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40
584 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44
585 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48
586 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50
587 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54
588 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58
589 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60
590 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64
591 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68
592 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70
593 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74
594 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78
595 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00
596 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04
597 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08
598 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10
599 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14
600 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18
601 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20
602 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24
603 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28
604 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30
605 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34
606 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38
607 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40
608 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44
609 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48
610 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50
611 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54
612 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58
613 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60
614 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64
615 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68
616 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70
617 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74
618 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78
619 #define EMC_PMACRO_IB_VREF_DQ_0 0xbe0
620 #define EMC_PMACRO_IB_VREF_DQ_1 0xbe4
621 #define EMC_PMACRO_IB_VREF_DQS_0 0xbf0
622 #define EMC_PMACRO_IB_VREF_DQS_1 0xbf4
623 #define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00
624 #define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04
625 #define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08
626 #define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c
627 #define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10
628 #define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14
629 #define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20
630 #define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24
631 #define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28
632 #define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30
641 #define EMC_PMACRO_VTTGEN_CTRL_0 0xc34
642 #define EMC_PMACRO_VTTGEN_CTRL_1 0xc38
643 #define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c
644 #define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD BIT(0)
646 #define EMC_PMACRO_PAD_CFG_CTRL 0xc40
647 #define EMC_PMACRO_ZCTRL 0xc44
648 #define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50
649 #define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54
650 #define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58
651 #define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c
652 #define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60
659 #define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64
660 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF BIT(0)
667 #define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68
668 #define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78
670 #define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0
671 #define EMC_PMACRO_IB_RXRT 0xcf4
672 #define EMC_PMACRO_TRAINING_CTRL_0 0xcf8
674 #define EMC_PMACRO_TRAINING_CTRL_1 0xcfc
676 #define EMC_TRAINING_CTRL 0xe04
677 #define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c
678 #define EMC_TRAINING_QUSE_FINE_CTRL 0xe10
679 #define EMC_TRAINING_QUSE_CTRL_MISC 0xe14
680 #define EMC_TRAINING_WRITE_FINE_CTRL 0xe18
681 #define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c
682 #define EMC_TRAINING_WRITE_VREF_CTRL 0xe20
683 #define EMC_TRAINING_READ_FINE_CTRL 0xe24
684 #define EMC_TRAINING_READ_CTRL_MISC 0xe28
685 #define EMC_TRAINING_READ_VREF_CTRL 0xe2c
686 #define EMC_TRAINING_CA_FINE_CTRL 0xe30
687 #define EMC_TRAINING_CA_CTRL_MISC 0xe34
688 #define EMC_TRAINING_CA_CTRL_MISC1 0xe38
689 #define EMC_TRAINING_CA_VREF_CTRL 0xe3c
690 #define EMC_TRAINING_SETTLE 0xe44
691 #define EMC_TRAINING_MPC 0xe5c
692 #define EMC_TRAINING_VREF_SETTLE 0xe6c
693 #define EMC_TRAINING_QUSE_VREF_CTRL 0xed0
694 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4
695 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8
697 #define EMC_COPY_TABLE_PARAM_PERIODIC_FIELDS BIT(0)
754 AUTO_PD = 0,
759 ASSEMBLY = 0,
875 TEGRA210_EMC_REFRESH_NOMINAL = 0,
881 #define DRAM_TYPE_DDR3 0