Lines Matching +full:0 +full:xcf8
33 #define A_SG_CONTROL 0x0
35 #define S_CMDQ0_ENABLE 0
60 #define M_CMDQ_PRIORITY 0x3
93 #define M_RX_PKT_OFFSET 0x7
101 #define A_SG_DOORBELL 0x4
102 #define A_SG_CMD0BASELWR 0x8
103 #define A_SG_CMD0BASEUPR 0xc
104 #define A_SG_CMD1BASELWR 0x10
105 #define A_SG_CMD1BASEUPR 0x14
106 #define A_SG_FL0BASELWR 0x18
107 #define A_SG_FL0BASEUPR 0x1c
108 #define A_SG_FL1BASELWR 0x20
109 #define A_SG_FL1BASEUPR 0x24
110 #define A_SG_CMD0SIZE 0x28
112 #define S_CMDQ0_SIZE 0
113 #define M_CMDQ0_SIZE 0x1ffff
117 #define A_SG_FL0SIZE 0x2c
119 #define S_FL0_SIZE 0
120 #define M_FL0_SIZE 0x1ffff
124 #define A_SG_RSPSIZE 0x30
126 #define S_RESPQ_SIZE 0
127 #define M_RESPQ_SIZE 0x1ffff
131 #define A_SG_RSPBASELWR 0x34
132 #define A_SG_RSPBASEUPR 0x38
133 #define A_SG_FLTHRESHOLD 0x3c
135 #define S_FL_THRESHOLD 0
136 #define M_FL_THRESHOLD 0xffff
140 #define A_SG_RSPQUEUECREDIT 0x40
142 #define S_RESPQ_CREDIT 0
143 #define M_RESPQ_CREDIT 0x1ffff
147 #define A_SG_SLEEPING 0x48
149 #define S_SLEEPING 0
150 #define M_SLEEPING 0xffff
154 #define A_SG_INTRTIMER 0x4c
156 #define S_INTERRUPT_TIMER_COUNT 0
157 #define M_INTERRUPT_TIMER_COUNT 0xffffff
161 #define A_SG_CMD0PTR 0x50
163 #define S_CMDQ0_POINTER 0
164 #define M_CMDQ0_POINTER 0xffff
172 #define A_SG_CMD1PTR 0x54
174 #define S_CMDQ1_POINTER 0
175 #define M_CMDQ1_POINTER 0xffff
179 #define A_SG_FL0PTR 0x58
181 #define S_FL0_POINTER 0
182 #define M_FL0_POINTER 0xffff
186 #define A_SG_FL1PTR 0x5c
188 #define S_FL1_POINTER 0
189 #define M_FL1_POINTER 0xffff
193 #define A_SG_VERSION 0x6c
195 #define S_DAY 0
196 #define M_DAY 0x1f
201 #define M_MONTH 0xf
205 #define A_SG_CMD1SIZE 0xb0
207 #define S_CMDQ1_SIZE 0
208 #define M_CMDQ1_SIZE 0x1ffff
212 #define A_SG_FL1SIZE 0xb4
214 #define S_FL1_SIZE 0
215 #define M_FL1_SIZE 0x1ffff
219 #define A_SG_INT_ENABLE 0xb8
221 #define S_RESPQ_EXHAUSTED 0
241 #define A_SG_INT_CAUSE 0xbc
242 #define A_SG_RESPACCUTIMER 0xc0
245 #define A_MC3_CFG 0x100
247 #define S_CLK_ENABLE 0
256 #define M_READ_TO_WRITE_DELAY 0x7
261 #define M_WRITE_TO_READ_DELAY 0x7
266 #define M_MC3_BANK_CYCLE 0xf
271 #define M_REFRESH_CYCLE 0xf
276 #define M_PRECHARGE_CYCLE 0x3
285 #define M_ACTIVE_TO_PRECHARGE_DELAY 0x7
290 #define M_WRITE_RECOVERY_DELAY 0x3
295 #define M_DENSITY 0x3
312 #define M_MC3_WIDTH 0x3
320 #define A_MC3_MODE 0x104
322 #define S_MC3_MODE 0
323 #define M_MC3_MODE 0x3fff
331 #define A_MC3_EXT_MODE 0x108
333 #define S_MC3_EXTENDED_MODE 0
334 #define M_MC3_EXTENDED_MODE 0x3fff
338 #define A_MC3_PRECHARG 0x10c
339 #define A_MC3_REFRESH 0x110
341 #define S_REFRESH_ENABLE 0
346 #define M_REFRESH_DIVISOR 0x3fff
350 #define A_MC3_STROBE 0x114
352 #define S_MASTER_DLL_RESET 0
357 #define M_MASTER_DLL_TAP_COUNT 0xff
370 #define M_MASTER_DLL_TAP_COUNT_OFFSET 0x3f
379 #define M_SLAVE_DLL_DELTA 0xf
384 #define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT 0x3f
393 #define M_SLAVE_DELAY_LINE_TAP_COUNT 0x3f
397 #define A_MC3_ECC_CNTL 0x118
399 #define S_ECC_GENERATION_ENABLE 0
408 #define M_CORRECTABLE_ERROR_COUNT 0xff
413 #define M_UNCORRECTABLE_ERROR_COUNT 0xff
417 #define A_MC3_CE_ADDR 0x11c
420 #define M_MC3_CE_ADDR 0xfffffff
424 #define A_MC3_CE_DATA0 0x120
425 #define A_MC3_CE_DATA1 0x124
426 #define A_MC3_CE_DATA2 0x128
427 #define A_MC3_CE_DATA3 0x12c
428 #define A_MC3_CE_DATA4 0x130
429 #define A_MC3_UE_ADDR 0x134
432 #define M_MC3_UE_ADDR 0xfffffff
436 #define A_MC3_UE_DATA0 0x138
437 #define A_MC3_UE_DATA1 0x13c
438 #define A_MC3_UE_DATA2 0x140
439 #define A_MC3_UE_DATA3 0x144
440 #define A_MC3_UE_DATA4 0x148
441 #define A_MC3_BD_ADDR 0x14c
442 #define A_MC3_BD_DATA0 0x150
443 #define A_MC3_BD_DATA1 0x154
444 #define A_MC3_BD_DATA2 0x158
445 #define A_MC3_BD_DATA3 0x15c
446 #define A_MC3_BD_DATA4 0x160
447 #define A_MC3_BD_OP 0x164
449 #define S_BACK_DOOR_OPERATION 0
453 #define A_MC3_BIST_ADDR_BEG 0x168
454 #define A_MC3_BIST_ADDR_END 0x16c
455 #define A_MC3_BIST_DATA 0x170
456 #define A_MC3_BIST_OP 0x174
458 #define S_OP 0
463 #define M_DATA_PATTERN 0x3
471 #define A_MC3_INT_ENABLE 0x178
473 #define S_MC3_CORR_ERR 0
482 #define M_MC3_PARITY_ERR 0xff
490 #define A_MC3_INT_CAUSE 0x17c
493 #define A_MC4_CFG 0x180
495 #define S_POWER_UP 0
500 #define M_MC4_BANK_CYCLE 0x7
513 #define M_MC4A_WIDTH 0x3
521 #define A_MC4_MODE 0x184
523 #define S_MC4_MODE 0
524 #define M_MC4_MODE 0x7fff
528 #define A_MC4_EXT_MODE 0x188
530 #define S_MC4_EXTENDED_MODE 0
531 #define M_MC4_EXTENDED_MODE 0x7fff
535 #define A_MC4_REFRESH 0x190
536 #define A_MC4_STROBE 0x194
537 #define A_MC4_ECC_CNTL 0x198
538 #define A_MC4_CE_ADDR 0x19c
541 #define M_MC4_CE_ADDR 0xffffff
545 #define A_MC4_CE_DATA0 0x1a0
546 #define A_MC4_CE_DATA1 0x1a4
547 #define A_MC4_CE_DATA2 0x1a8
548 #define A_MC4_CE_DATA3 0x1ac
549 #define A_MC4_CE_DATA4 0x1b0
550 #define A_MC4_UE_ADDR 0x1b4
553 #define M_MC4_UE_ADDR 0xffffff
557 #define A_MC4_UE_DATA0 0x1b8
558 #define A_MC4_UE_DATA1 0x1bc
559 #define A_MC4_UE_DATA2 0x1c0
560 #define A_MC4_UE_DATA3 0x1c4
561 #define A_MC4_UE_DATA4 0x1c8
562 #define A_MC4_BD_ADDR 0x1cc
564 #define S_MC4_BACK_DOOR_ADDR 0
565 #define M_MC4_BACK_DOOR_ADDR 0xfffffff
569 #define A_MC4_BD_DATA0 0x1d0
570 #define A_MC4_BD_DATA1 0x1d4
571 #define A_MC4_BD_DATA2 0x1d8
572 #define A_MC4_BD_DATA3 0x1dc
573 #define A_MC4_BD_DATA4 0x1e0
574 #define A_MC4_BD_OP 0x1e4
576 #define S_OPERATION 0
580 #define A_MC4_BIST_ADDR_BEG 0x1e8
581 #define A_MC4_BIST_ADDR_END 0x1ec
582 #define A_MC4_BIST_DATA 0x1f0
583 #define A_MC4_BIST_OP 0x1f4
584 #define A_MC4_INT_ENABLE 0x1f8
586 #define S_MC4_CORR_ERR 0
598 #define A_MC4_INT_CAUSE 0x1fc
601 #define A_TPI_ADDR 0x280
603 #define S_TPI_ADDRESS 0
604 #define M_TPI_ADDRESS 0xffffff
608 #define A_TPI_WR_DATA 0x284
609 #define A_TPI_RD_DATA 0x288
610 #define A_TPI_CSR 0x28c
612 #define S_TPIWR 0
624 #define A_TPI_PAR 0x29c
626 #define S_TPIPAR 0
627 #define M_TPIPAR 0x7f
633 #define A_TP_IN_CONFIG 0x300
635 #define S_TP_IN_CSPI_TUNNEL 0
687 #define A_TP_OUT_CONFIG 0x304
689 #define S_TP_OUT_C_ETH 0
733 #define A_TP_GLOBAL_CONFIG 0x308
735 #define S_IP_TTL 0
736 #define M_IP_TTL 0xff
741 #define M_TCAM_SERVER_REGION_USAGE 0x3
770 #define M_5TUPLE_LOOKUP 0x3
803 #define M_SYN_COOKIE_PARAMETER 0x3f
807 #define A_TP_GLOBAL_RX_CREDITS 0x30c
808 #define A_TP_CM_SIZE 0x310
809 #define A_TP_CM_MM_BASE 0x314
811 #define S_CM_MEMMGR_BASE 0
812 #define M_CM_MEMMGR_BASE 0xfffffff
816 #define A_TP_CM_TIMER_BASE 0x318
818 #define S_CM_TIMER_BASE 0
819 #define M_CM_TIMER_BASE 0xfffffff
823 #define A_TP_PM_SIZE 0x31c
824 #define A_TP_PM_TX_BASE 0x320
825 #define A_TP_PM_DEFRAG_BASE 0x324
826 #define A_TP_PM_RX_BASE 0x328
827 #define A_TP_PM_RX_PG_SIZE 0x32c
828 #define A_TP_PM_RX_MAX_PGS 0x330
829 #define A_TP_PM_TX_PG_SIZE 0x334
830 #define A_TP_PM_TX_MAX_PGS 0x338
831 #define A_TP_TCP_OPTIONS 0x340
833 #define S_TIMESTAMP 0
834 #define M_TIMESTAMP 0x3
839 #define M_WINDOW_SCALE 0x3
844 #define M_SACK 0x3
849 #define M_ECN 0x3
854 #define M_SACK_ALGORITHM 0x3
863 #define M_DEFAULT_PEER_MSS 0xffff
867 #define A_TP_DACK_CONFIG 0x344
869 #define S_DACK_MODE 0
882 #define M_DACK_MSS_SELECTOR 0x3
887 #define M_DACK_BYTE_THRESHOLD 0xfffff
891 #define A_TP_PC_CONFIG 0x348
893 #define S_TP_ACCESS_LATENCY 0
894 #define M_TP_ACCESS_LATENCY 0xf
923 #define M_TP_PC_REV 0x3
927 #define A_TP_BACKOFF0 0x350
929 #define S_ELEMENT0 0
930 #define M_ELEMENT0 0xff
935 #define M_ELEMENT1 0xff
940 #define M_ELEMENT2 0xff
945 #define M_ELEMENT3 0xff
949 #define A_TP_BACKOFF1 0x354
950 #define A_TP_BACKOFF2 0x358
951 #define A_TP_BACKOFF3 0x35c
952 #define A_TP_PARA_REG0 0x360
954 #define S_VAR_MULT 0
955 #define M_VAR_MULT 0xf
960 #define M_VAR_GAIN 0xf
965 #define M_SRTT_GAIN 0xf
970 #define M_RTTVAR_INIT 0xf
975 #define M_DUP_THRESH 0xf
980 #define M_INIT_CONG_WIN 0x7
984 #define A_TP_PARA_REG1 0x364
986 #define S_INITIAL_SLOW_START_THRESHOLD 0
987 #define M_INITIAL_SLOW_START_THRESHOLD 0xffff
992 #define M_RECEIVE_BUFFER_SIZE 0xffff
996 #define A_TP_PARA_REG2 0x368
998 #define S_RX_COALESCE_SIZE 0
999 #define M_RX_COALESCE_SIZE 0xffff
1004 #define M_MAX_RX_SIZE 0xffff
1008 #define A_TP_PARA_REG3 0x36c
1010 #define S_RX_COALESCING_PSH_DELIVER 0
1023 #define M_MAX_REORDER_FRAGMENTS 0x7
1027 #define A_TP_TIMER_RESOLUTION 0x390
1029 #define S_DELAYED_ACK_TIMER_RESOLUTION 0
1030 #define M_DELAYED_ACK_TIMER_RESOLUTION 0x3f
1035 #define M_GENERIC_TIMER_RESOLUTION 0x3f
1039 #define A_TP_2MSL 0x394
1041 #define S_2MSL 0
1042 #define M_2MSL 0x3fffffff
1046 #define A_TP_RXT_MIN 0x398
1048 #define S_RETRANSMIT_TIMER_MIN 0
1049 #define M_RETRANSMIT_TIMER_MIN 0xffff
1053 #define A_TP_RXT_MAX 0x39c
1055 #define S_RETRANSMIT_TIMER_MAX 0
1056 #define M_RETRANSMIT_TIMER_MAX 0x3fffffff
1060 #define A_TP_PERS_MIN 0x3a0
1062 #define S_PERSIST_TIMER_MIN 0
1063 #define M_PERSIST_TIMER_MIN 0xffff
1067 #define A_TP_PERS_MAX 0x3a4
1069 #define S_PERSIST_TIMER_MAX 0
1070 #define M_PERSIST_TIMER_MAX 0x3fffffff
1074 #define A_TP_KEEP_IDLE 0x3ac
1076 #define S_KEEP_ALIVE_IDLE_TIME 0
1077 #define M_KEEP_ALIVE_IDLE_TIME 0x3fffffff
1081 #define A_TP_KEEP_INTVL 0x3b0
1083 #define S_KEEP_ALIVE_INTERVAL_TIME 0
1084 #define M_KEEP_ALIVE_INTERVAL_TIME 0x3fffffff
1088 #define A_TP_INIT_SRTT 0x3b4
1090 #define S_INITIAL_SRTT 0
1091 #define M_INITIAL_SRTT 0xffff
1095 #define A_TP_DACK_TIME 0x3b8
1097 #define S_DELAYED_ACK_TIME 0
1098 #define M_DELAYED_ACK_TIME 0x7ff
1102 #define A_TP_FINWAIT2_TIME 0x3bc
1104 #define S_FINWAIT2_TIME 0
1105 #define M_FINWAIT2_TIME 0x3fffffff
1109 #define A_TP_FAST_FINWAIT2_TIME 0x3c0
1111 #define S_FAST_FINWAIT2_TIME 0
1112 #define M_FAST_FINWAIT2_TIME 0x3fffffff
1116 #define A_TP_SHIFT_CNT 0x3c4
1118 #define S_KEEPALIVE_MAX 0
1119 #define M_KEEPALIVE_MAX 0xff
1124 #define M_WINDOWPROBE_MAX 0xff
1129 #define M_RETRANSMISSION_MAX 0xff
1134 #define M_SYN_MAX 0xff
1138 #define A_TP_QOS_REG0 0x3e0
1140 #define S_L3_VALUE 0
1141 #define M_L3_VALUE 0x3f
1145 #define A_TP_QOS_REG1 0x3e4
1146 #define A_TP_QOS_REG2 0x3e8
1147 #define A_TP_QOS_REG3 0x3ec
1148 #define A_TP_QOS_REG4 0x3f0
1149 #define A_TP_QOS_REG5 0x3f4
1150 #define A_TP_QOS_REG6 0x3f8
1151 #define A_TP_QOS_REG7 0x3fc
1152 #define A_TP_MTU_REG0 0x404
1153 #define A_TP_MTU_REG1 0x408
1154 #define A_TP_MTU_REG2 0x40c
1155 #define A_TP_MTU_REG3 0x410
1156 #define A_TP_MTU_REG4 0x414
1157 #define A_TP_MTU_REG5 0x418
1158 #define A_TP_MTU_REG6 0x41c
1159 #define A_TP_MTU_REG7 0x420
1160 #define A_TP_RESET 0x44c
1162 #define S_TP_RESET 0
1170 #define A_TP_MIB_INDEX 0x450
1171 #define A_TP_MIB_DATA 0x454
1172 #define A_TP_SYNC_TIME_HI 0x458
1173 #define A_TP_SYNC_TIME_LO 0x45c
1174 #define A_TP_CM_MM_RX_FLST_BASE 0x460
1176 #define S_CM_MEMMGR_RX_FREE_LIST_BASE 0
1177 #define M_CM_MEMMGR_RX_FREE_LIST_BASE 0xfffffff
1181 #define A_TP_CM_MM_TX_FLST_BASE 0x464
1183 #define S_CM_MEMMGR_TX_FREE_LIST_BASE 0
1184 #define M_CM_MEMMGR_TX_FREE_LIST_BASE 0xfffffff
1188 #define A_TP_CM_MM_P_FLST_BASE 0x468
1190 #define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0
1191 #define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE 0xfffffff
1195 #define A_TP_CM_MM_MAX_P 0x46c
1197 #define S_CM_MEMMGR_MAX_PSTRUCT 0
1198 #define M_CM_MEMMGR_MAX_PSTRUCT 0xfffffff
1202 #define A_TP_INT_ENABLE 0x470
1204 #define S_TX_FREE_LIST_EMPTY 0
1212 #define A_TP_INT_CAUSE 0x474
1213 #define A_TP_TIMER_SEPARATOR 0x4a4
1215 #define S_DISABLE_PAST_TIMER_INSERTION 0
1220 #define M_MODULATION_TIMER_SEPARATOR 0x7fff
1225 #define M_GLOBAL_TIMER_SEPARATOR 0xffff
1229 #define A_TP_CM_FC_MODE 0x4b0
1230 #define A_TP_PC_CONGESTION_CNTL 0x4b4
1231 #define A_TP_TX_DROP_CONFIG 0x4b8
1242 #define M_DROP_TICKS_CNT 0x3ffffff
1246 #define S_NUM_PKTS_DROPPED 0
1247 #define M_NUM_PKTS_DROPPED 0xf
1251 #define A_TP_TX_DROP_COUNT 0x4bc
1254 #define A_RAT_ROUTE_CONTROL 0x580
1256 #define S_USE_ROUTE_TABLE 0
1268 #define A_RAT_ROUTE_TABLE_INDEX 0x584
1270 #define S_ROUTE_TABLE_INDEX 0
1271 #define M_ROUTE_TABLE_INDEX 0xf
1275 #define A_RAT_ROUTE_TABLE_DATA 0x588
1276 #define A_RAT_NO_ROUTE 0x58c
1278 #define S_CPL_OPCODE 0
1279 #define M_CPL_OPCODE 0xff
1283 #define A_RAT_INTR_ENABLE 0x590
1285 #define S_ZEROROUTEERROR 0
1301 #define A_RAT_INTR_CAUSE 0x594
1304 #define A_CSPI_RX_AE_WM 0x810
1305 #define A_CSPI_RX_AF_WM 0x814
1306 #define A_CSPI_CALENDAR_LEN 0x818
1308 #define S_CALENDARLENGTH 0
1309 #define M_CALENDARLENGTH 0xffff
1313 #define A_CSPI_FIFO_STATUS_ENABLE 0x820
1315 #define S_FIFOSTATUSENABLE 0
1319 #define A_CSPI_MAXBURST1_MAXBURST2 0x828
1321 #define S_MAXBURST1 0
1322 #define M_MAXBURST1 0xffff
1327 #define M_MAXBURST2 0xffff
1331 #define A_CSPI_TRAIN 0x82c
1333 #define S_CSPI_TRAIN_ALPHA 0
1334 #define M_CSPI_TRAIN_ALPHA 0xffff
1339 #define M_CSPI_TRAIN_DATA_MAXT 0xffff
1343 #define A_CSPI_INTR_STATUS 0x848
1345 #define S_DIP4ERR 0
1365 #define A_CSPI_INTR_ENABLE 0x84c
1368 #define A_ESPI_SCH_TOKEN0 0x880
1370 #define S_SCHTOKEN0 0
1371 #define M_SCHTOKEN0 0xffff
1375 #define A_ESPI_SCH_TOKEN1 0x884
1377 #define S_SCHTOKEN1 0
1378 #define M_SCHTOKEN1 0xffff
1382 #define A_ESPI_SCH_TOKEN2 0x888
1384 #define S_SCHTOKEN2 0
1385 #define M_SCHTOKEN2 0xffff
1389 #define A_ESPI_SCH_TOKEN3 0x88c
1391 #define S_SCHTOKEN3 0
1392 #define M_SCHTOKEN3 0xffff
1396 #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
1398 #define S_ALMOSTEMPTY 0
1399 #define M_ALMOSTEMPTY 0xffff
1403 #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
1405 #define S_ALMOSTFULL 0
1406 #define M_ALMOSTFULL 0xffff
1410 #define A_ESPI_CALENDAR_LENGTH 0x898
1411 #define A_PORT_CONFIG 0x89c
1413 #define S_RX_NPORTS 0
1414 #define M_RX_NPORTS 0xff
1419 #define M_TX_NPORTS 0xff
1423 #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
1425 #define S_RXSTATUSENABLE 0
1445 #define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
1446 #define A_ESPI_TRAIN 0x8ac
1448 #define S_MAXTRAINALPHA 0
1449 #define M_MAXTRAINALPHA 0xffff
1454 #define M_MAXTRAINDATA 0xffff
1458 #define A_RAM_STATUS 0x8b0
1460 #define S_RXFIFOPARITYERROR 0
1461 #define M_RXFIFOPARITYERROR 0x3ff
1466 #define M_TXFIFOPARITYERROR 0x3ff
1471 #define M_RXFIFOOVERFLOW 0x3ff
1475 #define A_TX_DROP_COUNT0 0x8b4
1477 #define S_TXPORT0DROPCNT 0
1478 #define M_TXPORT0DROPCNT 0xffff
1483 #define M_TXPORT1DROPCNT 0xffff
1487 #define A_TX_DROP_COUNT1 0x8b8
1489 #define S_TXPORT2DROPCNT 0
1490 #define M_TXPORT2DROPCNT 0xffff
1495 #define M_TXPORT3DROPCNT 0xffff
1499 #define A_RX_DROP_COUNT0 0x8bc
1501 #define S_RXPORT0DROPCNT 0
1502 #define M_RXPORT0DROPCNT 0xffff
1507 #define M_RXPORT1DROPCNT 0xffff
1511 #define A_RX_DROP_COUNT1 0x8c0
1513 #define S_RXPORT2DROPCNT 0
1514 #define M_RXPORT2DROPCNT 0xffff
1519 #define M_RXPORT3DROPCNT 0xffff
1523 #define A_DIP4_ERROR_COUNT 0x8c4
1525 #define S_DIP4ERRORCNT 0
1526 #define M_DIP4ERRORCNT 0xfff
1531 #define M_DIP4ERRORCNTSHADOW 0xfff
1547 #define A_ESPI_INTR_STATUS 0x8c8
1553 #define A_ESPI_INTR_ENABLE 0x8cc
1554 #define A_RX_DROP_THRESHOLD 0x8d0
1555 #define A_ESPI_RX_RESET 0x8ec
1557 #define S_ESPI_RX_LNK_RST 0
1569 #define A_ESPI_MISC_CONTROL 0x8f0
1571 #define S_OUT_OF_SYNC_COUNT 0
1572 #define M_OUT_OF_SYNC_COUNT 0xf
1581 #define M_DIP2_PARITY_ERR_THRES 0xf
1586 #define M_DIP4_THRES 0xfff
1603 #define M_MONITORED_PORT_NUM 0x3
1615 #define A_ESPI_DIP2_ERR_COUNT 0x8f4
1617 #define S_DIP2_ERR_CNT 0
1618 #define M_DIP2_ERR_CNT 0xf
1622 #define A_ESPI_CMD_ADDR 0x8f8
1624 #define S_WRITE_DATA 0
1625 #define M_WRITE_DATA 0xff
1630 #define M_REGISTER_OFFSET 0xf
1635 #define M_CHANNEL_ADDR 0xf
1640 #define M_MODULE_ADDR 0x3
1645 #define M_BUNDLE_ADDR 0x3
1650 #define M_SPI4_COMMAND 0xff
1654 #define A_ESPI_GOSTAT 0x8fc
1656 #define S_READ_DATA 0
1657 #define M_READ_DATA 0xff
1674 #define M_TRANSACTION_TIMER 0xff
1680 #define A_ULP_ULIMIT 0x980
1681 #define A_ULP_TAGMASK 0x984
1682 #define A_ULP_HREG_INDEX 0x988
1683 #define A_ULP_HREG_DATA 0x98c
1684 #define A_ULP_INT_ENABLE 0x990
1685 #define A_ULP_INT_CAUSE 0x994
1687 #define S_HREG_PAR_ERR 0
1720 #define M_PM_PAR_ERR 0xffff
1732 #define A_ULP_PIO_CTRL 0x998
1735 #define A_PL_ENABLE 0xa00
1737 #define S_PL_INTR_SGE_ERR 0
1785 #define A_PL_CAUSE 0xa04
1788 #define A_MC5_CONFIG 0xc04
1790 #define S_MODE 0
1815 #define M_SYN_ISSUE_MODE 0x3
1828 #define M_NUM_LIP 0x3f
1833 #define M_TCAM_PART_CNT 0x3
1838 #define M_TCAM_PART_TYPE 0x3
1843 #define M_TCAM_PART_SIZE 0x3
1851 #define A_MC5_SIZE 0xc08
1853 #define S_SIZE 0
1854 #define M_SIZE 0x3fffff
1858 #define A_MC5_ROUTING_TABLE_INDEX 0xc0c
1860 #define S_START_OF_ROUTING_TABLE 0
1861 #define M_START_OF_ROUTING_TABLE 0x3fffff
1865 #define A_MC5_SERVER_INDEX 0xc14
1867 #define S_START_OF_SERVER_INDEX 0
1868 #define M_START_OF_SERVER_INDEX 0x3fffff
1872 #define A_MC5_LIP_RAM_ADDR 0xc18
1874 #define S_LOCAL_IP_RAM_ADDR 0
1875 #define M_LOCAL_IP_RAM_ADDR 0x3f
1883 #define A_MC5_LIP_RAM_DATA 0xc1c
1884 #define A_MC5_RSP_LATENCY 0xc20
1886 #define S_SEARCH_RESPONSE_LATENCY 0
1887 #define M_SEARCH_RESPONSE_LATENCY 0x1f
1892 #define M_LEARN_RESPONSE_LATENCY 0x1f
1896 #define A_MC5_PARITY_LATENCY 0xc24
1898 #define S_SRCHLAT 0
1899 #define M_SRCHLAT 0x1f
1904 #define M_PARLAT 0x1f
1908 #define A_MC5_WR_LRN_VERIFY 0xc28
1910 #define S_POVEREN 0
1922 #define A_MC5_PART_ID_INDEX 0xc2c
1924 #define S_IDINDEX 0
1925 #define M_IDINDEX 0xf
1929 #define A_MC5_RESET_MAX 0xc30
1931 #define S_RSTMAX 0
1932 #define M_RSTMAX 0x1ff
1936 #define A_MC5_INT_ENABLE 0xc40
1938 #define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR 0
2002 #define A_MC5_INT_CAUSE 0xc44
2003 #define A_MC5_INT_TID 0xc48
2004 #define A_MC5_INT_PTID 0xc4c
2005 #define A_MC5_DBGI_CONFIG 0xc74
2006 #define A_MC5_DBGI_REQ_CMD 0xc78
2008 #define S_CMDMODE 0
2009 #define M_CMDMODE 0x7
2018 #define M_WRITE_BURST_SIZE 0x3ff
2022 #define A_MC5_DBGI_REQ_ADDR0 0xc7c
2023 #define A_MC5_DBGI_REQ_ADDR1 0xc80
2024 #define A_MC5_DBGI_REQ_ADDR2 0xc84
2025 #define A_MC5_DBGI_REQ_DATA0 0xc88
2026 #define A_MC5_DBGI_REQ_DATA1 0xc8c
2027 #define A_MC5_DBGI_REQ_DATA2 0xc90
2028 #define A_MC5_DBGI_REQ_DATA3 0xc94
2029 #define A_MC5_DBGI_REQ_DATA4 0xc98
2030 #define A_MC5_DBGI_REQ_MASK0 0xc9c
2031 #define A_MC5_DBGI_REQ_MASK1 0xca0
2032 #define A_MC5_DBGI_REQ_MASK2 0xca4
2033 #define A_MC5_DBGI_REQ_MASK3 0xca8
2034 #define A_MC5_DBGI_REQ_MASK4 0xcac
2035 #define A_MC5_DBGI_RSP_STATUS 0xcb0
2037 #define S_DBGI_RSP_VALID 0
2050 #define M_DBGI_RSP_ERR_REASON 0x7
2054 #define A_MC5_DBGI_RSP_DATA0 0xcb4
2055 #define A_MC5_DBGI_RSP_DATA1 0xcb8
2056 #define A_MC5_DBGI_RSP_DATA2 0xcbc
2057 #define A_MC5_DBGI_RSP_DATA3 0xcc0
2058 #define A_MC5_DBGI_RSP_DATA4 0xcc4
2059 #define A_MC5_DBGI_RSP_LAST_CMD 0xcc8
2060 #define A_MC5_POPEN_DATA_WR_CMD 0xccc
2061 #define A_MC5_POPEN_MASK_WR_CMD 0xcd0
2062 #define A_MC5_AOPEN_SRCH_CMD 0xcd4
2063 #define A_MC5_AOPEN_LRN_CMD 0xcd8
2064 #define A_MC5_SYN_SRCH_CMD 0xcdc
2065 #define A_MC5_SYN_LRN_CMD 0xce0
2066 #define A_MC5_ACK_SRCH_CMD 0xce4
2067 #define A_MC5_ACK_LRN_CMD 0xce8
2068 #define A_MC5_ILOOKUP_CMD 0xcec
2069 #define A_MC5_ELOOKUP_CMD 0xcf0
2070 #define A_MC5_DATA_WRITE_CMD 0xcf4
2071 #define A_MC5_DATA_READ_CMD 0xcf8
2072 #define A_MC5_MASK_WRITE_CMD 0xcfc
2075 #define A_PCICFG_PM_CSR 0x44
2076 #define A_PCICFG_VPD_ADDR 0x4a
2078 #define S_VPD_ADDR 0
2079 #define M_VPD_ADDR 0x7fff
2087 #define A_PCICFG_VPD_DATA 0x4c
2088 #define A_PCICFG_PCIX_CMD 0x60
2089 #define A_PCICFG_INTR_ENABLE 0xf4
2091 #define S_MASTER_PARITY_ERR 0
2124 #define M_RF_PARITY_ERR 0x3
2129 #define M_CF_PARITY_ERR 0x3
2133 #define A_PCICFG_INTR_CAUSE 0xf8
2134 #define A_PCICFG_MODE 0xfc
2136 #define S_PCI_MODE_64BIT 0
2145 #define M_PCI_MODE_PCIX_INITPAT 0x7
2154 #define M_PCI_MODE_CLK 0x3