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/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c60 hws[IMX7ULP_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx7ulp_clk_scg1_init()
69 base = of_iomap(np, 0); in imx7ulp_clk_scg1_init()
73 …hws[IMX7ULP_CLK_APLL_PRE_SEL] = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_s… in imx7ulp_clk_scg1_init()
74 …hws[IMX7ULP_CLK_SPLL_PRE_SEL] = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_s… in imx7ulp_clk_scg1_init()
77 …hws[IMX7ULP_CLK_APLL_PRE_DIV] = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x… in imx7ulp_clk_scg1_init()
78 …hws[IMX7ULP_CLK_SPLL_PRE_DIV] = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x… in imx7ulp_clk_scg1_init()
81 …hws[IMX7ULP_CLK_APLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll", "apll_pre_div", base + 0x500… in imx7ulp_clk_scg1_init()
82 …hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll", "spll_pre_div", base + 0x600… in imx7ulp_clk_scg1_init()
85 …IMX7ULP_CLK_APLL_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd0", "apll", base + 0x50c, 0); in imx7ulp_clk_scg1_init()
86 …hws[IMX7ULP_CLK_APLL_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd1", "apll", base + 0x50c… in imx7ulp_clk_scg1_init()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/linux/drivers/phy/socionext/
H A Dphy-uniphier-usb2.c18 #define SG_USBPHY1CTRL 0x500
19 #define SG_USBPHY1CTRL2 0x504
20 #define SG_USBPHY2CTRL 0x508
21 #define SG_USBPHY2CTRL2 0x50c /* LD11 */
22 #define SG_USBPHY12PLL 0x50c /* Pro4 */
23 #define SG_USBPHY3CTRL 0x510
24 #define SG_USBPHY3CTRL2 0x514
25 #define SG_USBPHY4CTRL 0x518 /* Pro4 */
26 #define SG_USBPHY4CTRL2 0x51c /* Pro4 */
27 #define SG_USBPHY34PLL 0x51c /* Pro4 */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
H A Dgk20a.c29 #define BUSY_SLOT 0
55 return nvkm_clk_astate(clk, *state, 0, false); in gk20a_pmu_dvfs_target()
82 level = max(0, level); in gk20a_pmu_dvfs_get_target_state()
100 status->busy = nvkm_falcon_rd32(falcon, 0x508 + (BUSY_SLOT * 0x10)); in gk20a_pmu_dvfs_get_dev_status()
101 status->total= nvkm_falcon_rd32(falcon, 0x508 + (CLK_SLOT * 0x10)); in gk20a_pmu_dvfs_get_dev_status()
109 nvkm_falcon_wr32(falcon, 0x508 + (BUSY_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
110 nvkm_falcon_wr32(falcon, 0x508 + (CLK_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
125 u32 utilization = 0; in gk20a_pmu_dvfs_work()
161 nvkm_timer_alarm(pmu->subdev.device->timer, 0, &gpmu->alarm); in gk20a_pmu_fini()
182 nvkm_falcon_wr32(falcon, 0x504 + (BUSY_SLOT * 0x10), 0x00200001); in gk20a_pmu_init()
[all …]
/linux/drivers/memory/tegra/
H A Dtegra210-mc.h12 #define MC_LATENCY_ALLOWANCE_AVPC_0 0x2e4
13 #define MC_LATENCY_ALLOWANCE_HC_0 0x310
14 #define MC_LATENCY_ALLOWANCE_HC_1 0x314
15 #define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
16 #define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
17 #define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
18 #define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
19 #define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
20 #define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
21 #define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c
[all …]
/linux/drivers/media/usb/au0828/
H A Dau0828-reg.h11 #define REG_000 0x000
12 #define REG_001 0x001
13 #define REG_002 0x002
14 #define REG_003 0x003
16 #define AU0828_SENSORCTRL_100 0x100
17 #define AU0828_SENSORCTRL_VBI_103 0x103
20 #define AU0828_I2C_TRIGGER_200 0x200
21 #define AU0828_I2C_STATUS_201 0x201
22 #define AU0828_I2C_CLK_DIVIDER_202 0x202
23 #define AU0828_I2C_DEST_ADDR_203 0x203
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_hdmi.h17 #define SUN4I_HDMI_CTRL_REG 0x004
20 #define SUN4I_HDMI_IRQ_REG 0x008
21 #define SUN4I_HDMI_IRQ_STA_MASK 0x73
23 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
25 #define SUN4I_HDMI_HPD_REG 0x00c
26 #define SUN4I_HDMI_HPD_HIGH BIT(0)
28 #define SUN4I_HDMI_VID_CTRL_REG 0x010
32 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
33 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
34 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
[all …]
/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_reg.h16 #define ODM_BB_RESET 0x002
17 #define ODM_DUMMY 0x4fe
18 #define RF_T_METER_OLD 0x24
19 #define RF_T_METER_NEW 0x42
21 #define ODM_EDCA_VO_PARAM 0x500
22 #define ODM_EDCA_VI_PARAM 0x504
23 #define ODM_EDCA_BE_PARAM 0x508
24 #define ODM_EDCA_BK_PARAM 0x50C
25 #define ODM_TXPAUSE 0x522
28 #define ODM_FPGA_PHY0_PAGE8 0x800
[all …]
H A Dodm_RegDefine11N.h13 #define ODM_REG_RF_MODE_11N 0x00
14 #define ODM_REG_RF_0B_11N 0x0B
15 #define ODM_REG_CHNBW_11N 0x18
16 #define ODM_REG_T_METER_11N 0x24
17 #define ODM_REG_RF_25_11N 0x25
18 #define ODM_REG_RF_26_11N 0x26
19 #define ODM_REG_RF_27_11N 0x27
20 #define ODM_REG_RF_2B_11N 0x2B
21 #define ODM_REG_RF_2C_11N 0x2C
22 #define ODM_REG_RXRF_A3_11N 0x3C
[all …]
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_mst_types.h29 #define DP_BRANCH_DEVICE_ID_90CC24 0x90CC24
31 #define SYNAPTICS_RC_COMMAND 0x4B2
32 #define SYNAPTICS_RC_RESULT 0x4B3
33 #define SYNAPTICS_RC_LENGTH 0x4B8
34 #define SYNAPTICS_RC_OFFSET 0x4BC
35 #define SYNAPTICS_RC_DATA 0x4C0
37 #define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C
41 * Offset DPCD 050Eh == 0x5A indicates cascaded MST hub case
44 #define IS_SYNAPTICS_PANAMERA(branchDevName) (((int)branchDevName[4] & 0xF0) == 0x50 ? 1 : 0)
45 #define BRANCH_HW_REVISION_PANAMERA_A2 0x10
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/linux/drivers/media/usb/stk1160/
H A Dstk1160-reg.h14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
/linux/drivers/staging/media/atomisp/pci/
H A Datomisp-regs.h23 #define PCICMDSTS 0x01
24 #define INTR 0x0f
25 #define MSI_CAPID 0x24
26 #define MSI_ADDRESS 0x25
27 #define MSI_DATA 0x26
28 #define INTR_CTL 0x27
30 #define PCI_MSI_CAPID 0x90
31 #define PCI_MSI_ADDR 0x94
32 #define PCI_MSI_DATA 0x98
33 #define PCI_INTERRUPT_CTRL 0x9C
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
H A Ddm.h11 #define MF_USC_LSC 0
14 #define MAIN_ANT 0
17 #define AUX_ANT_CG_TRX 0
18 #define MAIN_ANT_CGCS_RX 0
22 #define DM_REG_RF_MODE_11N 0x00
23 #define DM_REG_RF_0B_11N 0x0B
24 #define DM_REG_CHNBW_11N 0x18
25 #define DM_REG_T_METER_11N 0x24
26 #define DM_REG_RF_25_11N 0x25
27 #define DM_REG_RF_26_11N 0x26
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
15 #define DM_REG_RF_MODE_11N 0x00
16 #define DM_REG_RF_0B_11N 0x0B
17 #define DM_REG_CHNBW_11N 0x18
18 #define DM_REG_T_METER_11N 0x24
19 #define DM_REG_RF_25_11N 0x25
20 #define DM_REG_RF_26_11N 0x26
21 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dusb_mac.c11 s8 offset = 0; in mt76x2u_mac_fixup_xtal()
16 offset = eep_val & 0x7f; in mt76x2u_mac_fixup_xtal()
17 if ((eep_val & 0xff) == 0xff) in mt76x2u_mac_fixup_xtal()
18 offset = 0; in mt76x2u_mac_fixup_xtal()
19 else if (eep_val & 0x80) in mt76x2u_mac_fixup_xtal()
20 offset = 0 - offset; in mt76x2u_mac_fixup_xtal()
23 if (eep_val == 0x00 || eep_val == 0xff) { in mt76x2u_mac_fixup_xtal()
25 eep_val &= 0xff; in mt76x2u_mac_fixup_xtal()
27 if (eep_val == 0x00 || eep_val == 0xff) in mt76x2u_mac_fixup_xtal()
28 eep_val = 0x14; in mt76x2u_mac_fixup_xtal()
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723be/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,pfc.yaml28 - renesas,pfc-r8a774a3 # RZ/G2M v3.0
132 $ref: "#/additionalProperties/anyOf/0"
138 reg = <0xe6050000 0x8000>,
139 <0xe605800c 0x20>;
142 gpio-ranges = <&pfc 0 0 212>;
144 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
145 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
146 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
147 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
148 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dhdmi.yaml91 port@0:
102 - port@0
188 reg = <0x04a00000 0x2f0>;
200 pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
213 reg = <0x009a0000 0x50c>,
214 <0x00070000 0x6158>,
215 <0x009e0000 0xfff>;
238 pinctrl-0 = <&hdmi_hpd_active &hdmi_ddc_active>;
246 #size-cells = <0>;
248 port@0 {
[all …]
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
17 #define DM_REG_RF_MODE_11N 0x00
18 #define DM_REG_RF_0B_11N 0x0B
19 #define DM_REG_CHNBW_11N 0x18
20 #define DM_REG_T_METER_11N 0x24
21 #define DM_REG_RF_25_11N 0x25
22 #define DM_REG_RF_26_11N 0x26
23 #define DM_REG_RF_27_11N 0x27
[all …]
/linux/drivers/net/ethernet/broadcom/asp2/
H A Dbcmasp_intf_defs.h6 ((((intf)->port) * 0x800) + 0xc000)
7 #define UMC_CMD 0x008
8 #define UMC_CMD_TX_EN BIT(0)
10 #define UMC_CMD_SPEED_SHIFT 0x2
11 #define UMC_CMD_SPEED_MASK 0x3
12 #define UMC_CMD_SPEED_10 0x0
13 #define UMC_CMD_SPEED_100 0x1
14 #define UMC_CMD_SPEED_1000 0x2
15 #define UMC_CMD_SPEED_2500 0x3
33 #define UMC_MAC0 0x0c
[all …]

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