1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 20c0d06caSMauro Carvalho Chehab /* 30c0d06caSMauro Carvalho Chehab * Driver for the Auvitek USB bridge 40c0d06caSMauro Carvalho Chehab * 50c0d06caSMauro Carvalho Chehab * Copyright (c) 2008 Steven Toth <stoth@linuxtv.org> 60c0d06caSMauro Carvalho Chehab */ 70c0d06caSMauro Carvalho Chehab 80c0d06caSMauro Carvalho Chehab /* We'll start to rename these registers once we have a better 90c0d06caSMauro Carvalho Chehab * understanding of their meaning. 100c0d06caSMauro Carvalho Chehab */ 110c0d06caSMauro Carvalho Chehab #define REG_000 0x000 120c0d06caSMauro Carvalho Chehab #define REG_001 0x001 130c0d06caSMauro Carvalho Chehab #define REG_002 0x002 140c0d06caSMauro Carvalho Chehab #define REG_003 0x003 150c0d06caSMauro Carvalho Chehab 160c0d06caSMauro Carvalho Chehab #define AU0828_SENSORCTRL_100 0x100 170c0d06caSMauro Carvalho Chehab #define AU0828_SENSORCTRL_VBI_103 0x103 180c0d06caSMauro Carvalho Chehab 190c0d06caSMauro Carvalho Chehab /* I2C registers */ 200c0d06caSMauro Carvalho Chehab #define AU0828_I2C_TRIGGER_200 0x200 210c0d06caSMauro Carvalho Chehab #define AU0828_I2C_STATUS_201 0x201 220c0d06caSMauro Carvalho Chehab #define AU0828_I2C_CLK_DIVIDER_202 0x202 230c0d06caSMauro Carvalho Chehab #define AU0828_I2C_DEST_ADDR_203 0x203 240c0d06caSMauro Carvalho Chehab #define AU0828_I2C_WRITE_FIFO_205 0x205 250c0d06caSMauro Carvalho Chehab #define AU0828_I2C_READ_FIFO_209 0x209 260c0d06caSMauro Carvalho Chehab #define AU0828_I2C_MULTIBYTE_MODE_2FF 0x2ff 270c0d06caSMauro Carvalho Chehab 280c0d06caSMauro Carvalho Chehab /* Audio registers */ 290c0d06caSMauro Carvalho Chehab #define AU0828_AUDIOCTRL_50C 0x50C 300c0d06caSMauro Carvalho Chehab 310c0d06caSMauro Carvalho Chehab #define REG_600 0x600 320c0d06caSMauro Carvalho Chehab 330c0d06caSMauro Carvalho Chehab /*********************************************************************/ 340c0d06caSMauro Carvalho Chehab /* Here are constants for values associated with the above registers */ 350c0d06caSMauro Carvalho Chehab 360c0d06caSMauro Carvalho Chehab /* I2C Trigger (Reg 0x200) */ 370c0d06caSMauro Carvalho Chehab #define AU0828_I2C_TRIGGER_WRITE 0x01 380c0d06caSMauro Carvalho Chehab #define AU0828_I2C_TRIGGER_READ 0x20 390c0d06caSMauro Carvalho Chehab #define AU0828_I2C_TRIGGER_HOLD 0x40 400c0d06caSMauro Carvalho Chehab 410c0d06caSMauro Carvalho Chehab /* I2C Status (Reg 0x201) */ 420c0d06caSMauro Carvalho Chehab #define AU0828_I2C_STATUS_READ_DONE 0x01 430c0d06caSMauro Carvalho Chehab #define AU0828_I2C_STATUS_NO_READ_ACK 0x02 440c0d06caSMauro Carvalho Chehab #define AU0828_I2C_STATUS_WRITE_DONE 0x04 450c0d06caSMauro Carvalho Chehab #define AU0828_I2C_STATUS_NO_WRITE_ACK 0x08 460c0d06caSMauro Carvalho Chehab #define AU0828_I2C_STATUS_BUSY 0x10 470c0d06caSMauro Carvalho Chehab 480c0d06caSMauro Carvalho Chehab /* I2C Clock Divider (Reg 0x202) */ 490c0d06caSMauro Carvalho Chehab #define AU0828_I2C_CLK_250KHZ 0x07 500c0d06caSMauro Carvalho Chehab #define AU0828_I2C_CLK_100KHZ 0x14 510c0d06caSMauro Carvalho Chehab #define AU0828_I2C_CLK_30KHZ 0x40 520c0d06caSMauro Carvalho Chehab #define AU0828_I2C_CLK_20KHZ 0x60 53