xref: /linux/drivers/media/usb/stk1160/stk1160-reg.h (revision 75bf465f0bc33e9b776a46d6a1b9b990f5fb7c37)
1*c942fddfSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
20c0d06caSMauro Carvalho Chehab /*
30c0d06caSMauro Carvalho Chehab  * STK1160 driver
40c0d06caSMauro Carvalho Chehab  *
50c0d06caSMauro Carvalho Chehab  * Copyright (C) 2012 Ezequiel Garcia
60c0d06caSMauro Carvalho Chehab  * <elezegarcia--a.t--gmail.com>
70c0d06caSMauro Carvalho Chehab  *
80c0d06caSMauro Carvalho Chehab  * Based on Easycap driver by R.M. Thomas
90c0d06caSMauro Carvalho Chehab  *	Copyright (C) 2010 R.M. Thomas
100c0d06caSMauro Carvalho Chehab  *	<rmthomas--a.t--sciolus.org>
110c0d06caSMauro Carvalho Chehab  */
120c0d06caSMauro Carvalho Chehab 
130c0d06caSMauro Carvalho Chehab /* GPIO Control */
140c0d06caSMauro Carvalho Chehab #define STK1160_GCTRL			0x000
150c0d06caSMauro Carvalho Chehab 
163e4d8f48SMauro Carvalho Chehab /* Remote Wakeup Control */
170c0d06caSMauro Carvalho Chehab #define STK1160_RMCTL			0x00c
180c0d06caSMauro Carvalho Chehab 
191dc7df4dSMarcel Hasler /* Power-on Strapping Data */
201dc7df4dSMarcel Hasler #define STK1160_POSVA			0x010
211dc7df4dSMarcel Hasler #define STK1160_POSV_L			0x010
221dc7df4dSMarcel Hasler #define STK1160_POSV_M			0x011
231dc7df4dSMarcel Hasler #define STK1160_POSV_H			0x012
241dc7df4dSMarcel Hasler #define  STK1160_POSV_L_ACDOUT		BIT(3)
251dc7df4dSMarcel Hasler #define  STK1160_POSV_L_ACSYNC		BIT(2)
261dc7df4dSMarcel Hasler 
270c0d06caSMauro Carvalho Chehab /*
280c0d06caSMauro Carvalho Chehab  * Decoder Control Register:
290c0d06caSMauro Carvalho Chehab  * This byte controls capture start/stop
300c0d06caSMauro Carvalho Chehab  * with bit #7 (0x?? OR 0x80 to activate).
310c0d06caSMauro Carvalho Chehab  */
320c0d06caSMauro Carvalho Chehab #define STK1160_DCTRL			0x100
330c0d06caSMauro Carvalho Chehab 
34d3194520SEzequiel Garcia /*
35d3194520SEzequiel Garcia  * Decimation Control Register:
36d3194520SEzequiel Garcia  * Byte 104: Horizontal Decimation Line Unit Count
37d3194520SEzequiel Garcia  * Byte 105: Vertical Decimation Line Unit Count
38d3194520SEzequiel Garcia  * Byte 106: Decimation Control
39d3194520SEzequiel Garcia  * Bit 0 - Horizontal Decimation Control
40d3194520SEzequiel Garcia  *   0 Horizontal decimation is disabled.
41d3194520SEzequiel Garcia  *   1 Horizontal decimation is enabled.
42d3194520SEzequiel Garcia  * Bit 1 - Decimates Half or More Column
43d3194520SEzequiel Garcia  *   0 Decimates less than half from original column,
44d3194520SEzequiel Garcia  *     send count unit (0x105) before each unit skipped.
45d3194520SEzequiel Garcia  *   1 Decimates half or more from original column,
46d3194520SEzequiel Garcia  *     skip count unit (0x105) before each unit sent.
47d3194520SEzequiel Garcia  * Bit 2 - Vertical Decimation Control
48d3194520SEzequiel Garcia  *   0 Vertical decimation is disabled.
49d3194520SEzequiel Garcia  *   1 Vertical decimation is enabled.
50d3194520SEzequiel Garcia  * Bit 3 - Vertical Greater or Equal to Half
51d3194520SEzequiel Garcia  *   0 Decimates less than half from original row,
52d3194520SEzequiel Garcia  *     send count unit (0x105) before each unit skipped.
53d3194520SEzequiel Garcia  *   1 Decimates half or more from original row,
54d3194520SEzequiel Garcia  *     skip count unit (0x105) before each unit sent.
55d3194520SEzequiel Garcia  * Bit 4 - Decimation Unit
56d3194520SEzequiel Garcia  *  0 Decimation will work with 2 rows or columns per unit.
57d3194520SEzequiel Garcia  *  1 Decimation will work with 4 rows or columns per unit.
58d3194520SEzequiel Garcia  */
59d3194520SEzequiel Garcia #define STK1160_DMCTRL_H_UNITS		0x104
60d3194520SEzequiel Garcia #define STK1160_DMCTRL_V_UNITS		0x105
61d3194520SEzequiel Garcia #define STK1160_DMCTRL			0x106
62d3194520SEzequiel Garcia #define  STK1160_H_DEC_EN		BIT(0)
63d3194520SEzequiel Garcia #define  STK1160_H_DEC_MODE		BIT(1)
64d3194520SEzequiel Garcia #define  STK1160_V_DEC_EN		BIT(2)
65d3194520SEzequiel Garcia #define  STK1160_V_DEC_MODE		BIT(3)
66d3194520SEzequiel Garcia #define  STK1160_DEC_UNIT_SIZE		BIT(4)
67d3194520SEzequiel Garcia 
680c0d06caSMauro Carvalho Chehab /* Capture Frame Start Position */
690c0d06caSMauro Carvalho Chehab #define STK116_CFSPO			0x110
700c0d06caSMauro Carvalho Chehab #define STK116_CFSPO_STX_L		0x110
710c0d06caSMauro Carvalho Chehab #define STK116_CFSPO_STX_H		0x111
720c0d06caSMauro Carvalho Chehab #define STK116_CFSPO_STY_L		0x112
730c0d06caSMauro Carvalho Chehab #define STK116_CFSPO_STY_H		0x113
740c0d06caSMauro Carvalho Chehab 
750c0d06caSMauro Carvalho Chehab /* Capture Frame End Position */
760c0d06caSMauro Carvalho Chehab #define STK116_CFEPO			0x114
770c0d06caSMauro Carvalho Chehab #define STK116_CFEPO_ENX_L		0x114
780c0d06caSMauro Carvalho Chehab #define STK116_CFEPO_ENX_H		0x115
790c0d06caSMauro Carvalho Chehab #define STK116_CFEPO_ENY_L		0x116
800c0d06caSMauro Carvalho Chehab #define STK116_CFEPO_ENY_H		0x117
810c0d06caSMauro Carvalho Chehab 
820c0d06caSMauro Carvalho Chehab /* Serial Interface Control  */
830c0d06caSMauro Carvalho Chehab #define STK1160_SICTL			0x200
840c0d06caSMauro Carvalho Chehab #define STK1160_SICTL_CD		0x202
850c0d06caSMauro Carvalho Chehab #define STK1160_SICTL_SDA		0x203
860c0d06caSMauro Carvalho Chehab 
870c0d06caSMauro Carvalho Chehab /* Serial Bus Write */
880c0d06caSMauro Carvalho Chehab #define STK1160_SBUSW			0x204
890c0d06caSMauro Carvalho Chehab #define STK1160_SBUSW_WA		0x204
900c0d06caSMauro Carvalho Chehab #define STK1160_SBUSW_WD		0x205
910c0d06caSMauro Carvalho Chehab 
920c0d06caSMauro Carvalho Chehab /* Serial Bus Read */
930c0d06caSMauro Carvalho Chehab #define STK1160_SBUSR			0x208
940c0d06caSMauro Carvalho Chehab #define STK1160_SBUSR_RA		0x208
950c0d06caSMauro Carvalho Chehab #define STK1160_SBUSR_RD		0x209
960c0d06caSMauro Carvalho Chehab 
973e4d8f48SMauro Carvalho Chehab /* Alternate Serial Interface Control */
980c0d06caSMauro Carvalho Chehab #define STK1160_ASIC			0x2fc
990c0d06caSMauro Carvalho Chehab 
1000c0d06caSMauro Carvalho Chehab /* PLL Select Options */
1010c0d06caSMauro Carvalho Chehab #define STK1160_PLLSO			0x018
1020c0d06caSMauro Carvalho Chehab 
1030c0d06caSMauro Carvalho Chehab /* PLL Frequency Divider */
1040c0d06caSMauro Carvalho Chehab #define STK1160_PLLFD			0x01c
1050c0d06caSMauro Carvalho Chehab 
1060c0d06caSMauro Carvalho Chehab /* Timing Generator */
1070c0d06caSMauro Carvalho Chehab #define STK1160_TIGEN			0x300
1080c0d06caSMauro Carvalho Chehab 
1090c0d06caSMauro Carvalho Chehab /* Timing Control Parameter */
1100c0d06caSMauro Carvalho Chehab #define STK1160_TICTL			0x350
1110c0d06caSMauro Carvalho Chehab 
1120c0d06caSMauro Carvalho Chehab /* AC97 Audio Control */
1130c0d06caSMauro Carvalho Chehab #define STK1160_AC97CTL_0		0x500
1140c0d06caSMauro Carvalho Chehab #define STK1160_AC97CTL_1		0x504
1159a4825edSMarcel Hasler #define  STK1160_AC97CTL_0_CR		BIT(1)
1169a4825edSMarcel Hasler #define  STK1160_AC97CTL_0_CW		BIT(2)
1170c0d06caSMauro Carvalho Chehab 
1180c0d06caSMauro Carvalho Chehab /* Use [0:6] bits of register 0x504 to set codec command address */
1190c0d06caSMauro Carvalho Chehab #define STK1160_AC97_ADDR		0x504
1200c0d06caSMauro Carvalho Chehab /* Use [16:31] bits of register 0x500 to set codec command data */
1210c0d06caSMauro Carvalho Chehab #define STK1160_AC97_CMD		0x502
1220c0d06caSMauro Carvalho Chehab 
1230c0d06caSMauro Carvalho Chehab /* Audio I2S Interface */
1240c0d06caSMauro Carvalho Chehab #define STK1160_I2SCTL			0x50c
1250c0d06caSMauro Carvalho Chehab 
1260c0d06caSMauro Carvalho Chehab /* EEPROM Interface */
1270c0d06caSMauro Carvalho Chehab #define STK1160_EEPROM_SZ		0x5f0
128