Lines Matching +full:0 +full:x50c
17 #define SUN4I_HDMI_CTRL_REG 0x004
20 #define SUN4I_HDMI_IRQ_REG 0x008
21 #define SUN4I_HDMI_IRQ_STA_MASK 0x73
23 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
25 #define SUN4I_HDMI_HPD_REG 0x00c
26 #define SUN4I_HDMI_HPD_HIGH BIT(0)
28 #define SUN4I_HDMI_VID_CTRL_REG 0x010
32 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
33 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
34 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
35 #define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020
37 #define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0)))
38 #define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16)
40 #define SUN4I_HDMI_VID_TIMING_POL_REG 0x024
41 #define SUN4I_HDMI_VID_TIMING_POL_TX_CLK (0x3e0 << 16)
43 #define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0)
45 #define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n))
47 #define SUN4I_HDMI_PAD_CTRL0_REG 0x200
57 #define SUN4I_HDMI_PAD_CTRL1_REG 0x204
74 #define SUN4I_HDMI_PAD_CTRL1_INVERT_B BIT(0)
76 #define SUN4I_HDMI_PLL_CTRL_REG 0x208
85 #define SUN4I_HDMI_PLL_CTRL_CP_S(n) (((n) & 0x1f) << 12)
86 #define SUN4I_HDMI_PLL_CTRL_CS(n) (((n) & 0xf) << 8)
87 #define SUN4I_HDMI_PLL_CTRL_DIV(n) (((n) & 0xf) << 4)
89 #define SUN4I_HDMI_PLL_CTRL_VCO_S(n) ((n) & 0xf)
91 #define SUN4I_HDMI_PLL_DBG0_REG 0x20c
96 #define SUN4I_HDMI_CEC 0x214
101 #define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n)))
104 #define SUN4I_HDMI_UNKNOWN_REG 0x300
107 #define SUN4I_HDMI_DDC_CTRL_REG 0x500
112 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8)
113 #define SUN4I_HDMI_DDC_CTRL_RESET BIT(0)
115 #define SUN4I_HDMI_DDC_ADDR_REG 0x504
116 #define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24)
117 #define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
118 #define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8)
119 #define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff)
121 #define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c
129 #define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0)
131 #define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510
133 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4)
136 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf)
137 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0)
140 #define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518
142 #define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c
145 #define SUN4I_HDMI_DDC_CMD_REG 0x520
150 #define SUN4I_HDMI_DDC_CLK_REG 0x528
151 #define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0xf) << 3)
152 #define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7)
154 #define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540
161 #define SUN6I_HDMI_DDC_CTRL_REG 0x500
166 #define SUN6I_HDMI_DDC_CTRL_ENABLE BIT(0)
168 #define SUN6I_HDMI_DDC_CMD_REG 0x508
172 #define SUN6I_HDMI_DDC_ADDR_REG 0x50c
173 #define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24)
174 #define SUN6I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
175 #define SUN6I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8)
176 #define SUN6I_HDMI_DDC_ADDR_SLAVE(addr) (((addr) & 0xff) << 1)
178 #define SUN6I_HDMI_DDC_INT_STATUS_REG 0x514
182 #define SUN6I_HDMI_DDC_FIFO_CTRL_REG 0x518
186 #define SUN6I_HDMI_DDC_CLK_REG 0x520
189 #define SUN6I_HDMI_DDC_FIFO_DATA_REG 0x580