xref: /linux/drivers/memory/tegra/tegra210-mc.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
1*10de2114SJoseph Lo /* SPDX-License-Identifier: GPL-2.0 */
2*10de2114SJoseph Lo /*
3*10de2114SJoseph Lo  * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
4*10de2114SJoseph Lo  */
5*10de2114SJoseph Lo 
6*10de2114SJoseph Lo #ifndef TEGRA210_MC_H
7*10de2114SJoseph Lo #define TEGRA210_MC_H
8*10de2114SJoseph Lo 
9*10de2114SJoseph Lo #include "mc.h"
10*10de2114SJoseph Lo 
11*10de2114SJoseph Lo /* register definitions */
12*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_AVPC_0				0x2e4
13*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_HC_0				0x310
14*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_HC_1				0x314
15*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_MPCORE_0				0x320
16*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_NVENC_0				0x328
17*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_PPCS_0				0x344
18*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_PPCS_1				0x348
19*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_ISP2_0				0x370
20*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_ISP2_1				0x374
21*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_XUSB_0				0x37c
22*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_XUSB_1				0x380
23*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_TSEC_0				0x390
24*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_VIC_0				0x394
25*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_VI2_0				0x398
26*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_GPU_0				0x3ac
27*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_SDMMCA_0				0x3b8
28*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_SDMMCAA_0				0x3bc
29*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_SDMMC_0				0x3c0
30*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_SDMMCAB_0				0x3c4
31*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_GPU2_0				0x3e8
32*10de2114SJoseph Lo #define MC_LATENCY_ALLOWANCE_NVDEC_0				0x3d8
33*10de2114SJoseph Lo #define MC_MLL_MPCORER_PTSA_RATE				0x44c
34*10de2114SJoseph Lo #define MC_FTOP_PTSA_RATE					0x50c
35*10de2114SJoseph Lo #define MC_EMEM_ARB_TIMING_RFCPB				0x6c0
36*10de2114SJoseph Lo #define MC_EMEM_ARB_TIMING_CCDMW				0x6c4
37*10de2114SJoseph Lo #define MC_EMEM_ARB_REFPB_HP_CTRL				0x6f0
38*10de2114SJoseph Lo #define MC_EMEM_ARB_REFPB_BANK_CTRL				0x6f4
39*10de2114SJoseph Lo #define MC_PTSA_GRANT_DECREMENT					0x960
40*10de2114SJoseph Lo #define MC_EMEM_ARB_DHYST_CTRL					0xbcc
41*10de2114SJoseph Lo #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0			0xbd0
42*10de2114SJoseph Lo #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1			0xbd4
43*10de2114SJoseph Lo #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2			0xbd8
44*10de2114SJoseph Lo #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3			0xbdc
45*10de2114SJoseph Lo #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4			0xbe0
46*10de2114SJoseph Lo #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5			0xbe4
47*10de2114SJoseph Lo #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6			0xbe8
48*10de2114SJoseph Lo #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7			0xbec
49*10de2114SJoseph Lo 
50*10de2114SJoseph Lo #endif
51