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12

/freebsd/sys/contrib/device-tree/Bindings/soc/imx/
H A Dimx8m-soc.yaml29 "^soc@[0-9a-f]+$":
76 soc@0 {
80 ranges = <0x0 0x0 0x0 0x3e000000>;
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm2166x-common.dtsi22 ranges = <0 0x34000000 0x102f83ac>;
28 reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
33 reg = <0x01001f00 0x24>;
38 reg = <0x01003000 0x524>;
51 reg = <0x01006000 0x1c>;
60 ranges = <0 0x3e000000 0x0001c070>;
64 uartb: serial@0 {
66 reg = <0x00000000 0x118>;
76 reg = <0x00001000 0x118>;
86 reg = <0x00002000 0x118>;
[all …]
H A Dbcm11351.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 secondary-boot-reg = <0x3500417c>;
41 #address-cells = <0>;
43 reg = <0x3ff01000 0x1000>,
44 <0x3ff00100 0x100>;
49 reg = <0x3404c00
[all...]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_an_lt_wrapper_regs.h60 /* [0x0] AN LT wrapper Version */
62 /* [0x4] AN LT general configuration */
67 /* [0x0] AN LT register file address */
69 /* [0x4] PCS register file data */
71 /* [0x8] AN LT control signals */
73 /* [0xc] AN LT status signals */
79 AL_ETH_AN_LT_UNIT_32_BIT = 0,
86 struct al_an_lt_wrapper_gen gen; /* [0x100] */
87 struct al_an_lt_wrapper_an_lt an_lt[3]; /* [0x140] */
98 #define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
[all …]
H A Dal_hal_eth_mac_regs.h59 uint32_t aFramesTransmittedOK; /* 0x68 */
60 uint32_t aFramesReceivedOK; /* 0x6c */
61 uint32_t aFrameCheckSequenceErrors; /* 0x70 */
62 uint32_t aAlignmentErrors; /* 0x74 */
63 uint32_t aOctetsTransmittedOK; /* 0x78 */
64 uint32_t aOctetsReceivedOK; /* 0x7c */
65 uint32_t aPAUSEMACCtrlFramesTransmitted; /* 0x80 */
66 uint32_t aPAUSEMACCtrlFramesReceived; /* 0x84 */
67 uint32_t ifInErrors ; /* 0x88 */
68 uint32_t ifOutErrors; /* 0x8c */
[all …]
H A Dal_hal_eth_ec_regs.h60 /* [0x0] Ethernet controller Version */
62 /* [0x4] Enable modules operation. */
64 /* [0x8] Enable FIFO operation on the EC side. */
66 /* [0xc] General L2 configuration for the Ethernet controlle ... */
68 /* [0x10] Configure protocol index values */
70 /* [0x14] Configure protocol index values (extended protocols ... */
72 /* [0x18] Enable modules operation (extended operations). */
77 /* [0x0] General configuration of the MAC side of the Ethern ... */
79 /* [0x4] Minimum packet size */
81 /* [0x8] Maximum packet size */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-ipq8064-rb3011.dts25 pinctrl-0 = <&buttons_pins>;
39 pinctrl-0 = <&leds_pins>;
42 led-0 {
51 reg = <0x42000000 0x3e000000>;
55 mdio0: mdio-0 {
59 <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
61 #size-cells = <0>;
63 pinctrl-0 = <&mdio0_pins>;
69 dsa,member = <0 0>;
71 pinctrl-0 = <&sw0_reset_pin>;
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_serdes_25g_regs.h57 /* [0x0] SERDES registers Version */
60 /* [0x10] SERDES register file address */
62 /* [0x14] SERDES register file data */
64 /* [0x18] SERDES control */
66 /* [0x1c] SERDES cpu mem address */
68 /* [0x20] SERDES cpu mem data */
70 /* [0x24] SERDES data mem address */
72 /* [0x28] SERDES data mem data */
74 /* [0x2c] SERDES control */
76 /* [0x30] SERDES control */
[all …]
H A Dal_hal_serdes_hssp_regs.h57 /* [0x0] SerDes Registers Version */
60 /* [0x10] SerDes register file address */
62 /* [0x14] SerDes register file data */
65 /* [0x20] SerDes control */
67 /* [0x24] SerDes control */
69 /* [0x28] SerDes control */
72 /* [0x30] SerDes control */
74 /* [0x34] SerDes control */
76 /* [0x38] SerDes control */
78 /* [0x3c] SerDes control */
[all …]
H A Dal_hal_serdes_regs.h58 /* [0x0] SerDes Registers Version */
61 /* [0x10] SerDes register file address */
63 /* [0x14] SerDes register file data */
66 /* [0x20] SerDes control */
68 /* [0x24] SerDes control */
70 /* [0x28] SerDes control */
73 /* [0x30] SerDes control */
75 /* [0x34] SerDes control */
77 /* [0x38] SerDes control */
79 /* [0x3c] SerDes control */
[all …]
H A Dal_hal_nb_regs.h60 /* [0x0] */
62 /* [0x4] */
64 /* [0x8] Force init reset. */
66 /* [0xc] Force init reset per DECEI mode. */
68 /* [0x10] */
70 /* [0x14] */
72 /* [0x18] */
74 /* [0x1c] */
76 /* [0x20] */
78 /* [0x24] */
[all …]
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DHexagon.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
56 defaultMaxPageSize = 0x10000; in Hexagon()
71 return ret.value_or(/* Default Arch Rev: */ 0x60); in calcEFlags()
75 uint32_t result = 0; in applyMask()
76 size_t off = 0; in applyMask()
78 for (size_t bit = 0; bit != 32; ++bit) { in applyMask()
170 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f},
171 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80},
172 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0},
173 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0},
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h49 0x00000001, 0x00000002, 0x00000004, 0x00000008,
50 0x00000010, 0x00000020, 0x00000040, 0x00000080,
51 0x0000001b, 0x00000036
57 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
58 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
59 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
60 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
61 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
62 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
63 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dmcp_public.h51 #define OFFSIZE_OFFSET_OFFSET 0
52 #define OFFSIZE_OFFSET_MASK 0x0000ffff
55 #define OFFSIZE_SIZE_MASK 0xffff0000
70 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
71 #define ETH_SPEED_AUTONEG 0
72 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */
75 #define ETH_PAUSE_NONE 0x0
76 #define ETH_PAUSE_AUTONEG 0x1
77 #define ETH_PAUSE_RX 0x2
78 #define ETH_PAUSE_TX 0x4
[all …]
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h46 #define CHIPC_GET_FLAG(_value, _flag) (((_value) & _flag) != 0)
50 #define CHIPC_ID 0x00
51 #define CHIPC_CAPABILITIES 0x04
52 #define CHIPC_CORECTRL 0x08 /* rev >= 1 */
53 #define CHIPC_BIST 0x0C
55 #define CHIPC_OTPST 0x10 /**< otp status */
56 #define CHIPC_OTPCTRL 0x14 /**< otp control */
57 #define CHIPC_OTPPROG 0x18
58 #define CHIPC_OTPLAYOUT 0x1C /**< otp layout (IPX OTP) */
60 #define CHIPC_INTST 0x20 /**< interrupt status */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
H A Dimx8mm.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
[all …]
H A Dimx8mq.dtsi47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
H A Dimx8mp.dtsi48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
[all …]
/freebsd/contrib/arm-optimized-routines/math/test/rtest/
H A Ddotest.c21 #if MPFR_VERSION < MPFR_VERSION_NUM(4, 2, 0)
102 uint32 exp = (hl >> 52) & 0x7ff; in set_mpfr_d()
105 if (exp == 0x7ff) { in set_mpfr_d()
106 if (mantissa == 0) in set_mpfr_d()
110 } else if (exp == 0 && mantissa == 0) { in set_mpfr_d()
111 mpfr_set_ui(x, 0, GMP_RNDN); in set_mpfr_d()
112 mpfr_setsign(x, x, sign < 0, GMP_RNDN); in set_mpfr_d()
114 if (exp != 0) in set_mpfr_d()
118 mpfr_set_sj_2exp(x, mantissa * sign, (int)exp - 0x3ff - 52, GMP_RNDN); in set_mpfr_d()
123 uint32 exp = (f >> 23) & 0xff; in set_mpfr_f()
[all …]
/freebsd/tests/sys/cddl/zfs/tests/txg_integrity/
H A Dtxg_integrity.c84 #define USE_MMAP 0
90 //partitions[-1] is understood to be 0 and partitions[NUM_CHUNKS] must be 1.0
94 //8 / (NUM_CHUNKS * CLUSTERSIZE) = 1 / 524288 = 0x0.00002
98 //chunk 0 corresponds to bit 1, chunk 1 to bit 2, etc
106 if (chunk == 0){ in get_chunk_range()
107 *begin = 0; in get_chunk_range()
117 leader_syncs = 0,
125 {0x2000000, 0x4000000, 0x6000000, 0x8000000, 0xa000000, 0xc000000, 0xe000000, 0x10000000,
126 0x12000000, 0x14000000, 0x16000000, 0x18000000, 0x1a000000, 0x1c000000, 0x1e000000, 0x20000000,
127 0x22000000, 0x24000000, 0x26000000, 0x28000000, 0x2a000000, 0x2c000000, 0x2e000000, 0x30000000,
[all …]
H A Dfsync_integrity.c61 * Every even-numbered thread, starting with the first (0th), will fsync()
98 //partitions[-1] is understood to be 0 and partitions[NUM_CHUNKS] must be 1.0
102 //8 / (NUM_CHUNKS * CLUSTERSIZE) = 1 / 524288 = 0x0.00002
116 if (chunk == 0){ in get_chunk_range()
117 *begin = 0; in get_chunk_range()
129 {0x2000000, 0x4000000, 0x6000000, 0x8000000, 0xa000000, 0xc000000, 0xe000000, 0x10000000,
130 0x12000000, 0x14000000, 0x16000000, 0x18000000, 0x1a000000, 0x1c000000, 0x1e000000, 0x20000000,
131 0x22000000, 0x24000000, 0x26000000, 0x28000000, 0x2a000000, 0x2c000000, 0x2e000000, 0x30000000,
132 0x32000000, 0x34000000, 0x36000000, 0x38000000, 0x3a000000, 0x3c000000, 0x3e000000, 0x40000000,
133 0x42000000, 0x44000000, 0x46000000, 0x48000000, 0x4a000000, 0x4c000000, 0x4e000000, 0x50000000,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMask.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 0xf0000000,
18 0xb0000000,
19 0x0fe03fe0,
20 0 },
23 0xffc00000,
24 0x76000000,
25 0x00203fe0,
26 0 },
29 0xff800000,
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Drtw8822c.c21 #define IQK_DONE_8822C 0xaa
56 efuse->country_code[0] = map->country_code[0]; in rtw8822c_read_efuse()
59 efuse->regd = map->rf_board_option & 0x7; in rtw8822c_read_efuse()
64 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; in rtw8822c_read_efuse()
66 for (i = 0; i < 4; i++) in rtw8822c_read_efuse()
84 return 0; in rtw8822c_read_efuse()
114 u32 rf_addr[DACK_RF_8822C] = {0x8f}; in rtw8822c_dac_backup_reg()
115 u32 addrs[DACK_REG_8822C] = {0x180c, 0x181 in rtw8822c_dac_backup_reg()
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]

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