Lines Matching +full:0 +full:x3e000000
57 /* [0x0] SERDES registers Version */
60 /* [0x10] SERDES register file address */
62 /* [0x14] SERDES register file data */
64 /* [0x18] SERDES control */
66 /* [0x1c] SERDES cpu mem address */
68 /* [0x20] SERDES cpu mem data */
70 /* [0x24] SERDES data mem address */
72 /* [0x28] SERDES data mem data */
74 /* [0x2c] SERDES control */
76 /* [0x30] SERDES control */
82 /* [0x10] Data configuration */
84 /* [0x14] Lane status */
86 /* [0x18] SERDES control */
93 struct al_serdes_c_gen gen; /* [0x100] */
94 struct al_serdes_c_lane lane[2]; /* [0x200] */
105 #define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
106 #define SERDES_C_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
108 #define SERDES_C_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
111 #define SERDES_C_GEN_VERSION_DATE_DAY_MASK 0x001F0000
114 #define SERDES_C_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
117 #define SERDES_C_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
120 #define SERDES_C_GEN_VERSION_RESERVED_MASK 0xC0000000
125 #define SERDES_C_GEN_REG_ADDR_VAL_MASK 0x00007FFF
126 #define SERDES_C_GEN_REG_ADDR_VAL_SHIFT 0
130 #define SERDES_C_GEN_REG_DATA_VAL_MASK 0x000000FF
131 #define SERDES_C_GEN_REG_DATA_VAL_SHIFT 0
133 #define SERDES_C_GEN_REG_DATA_STRB_MASK 0x0000FF00
138 * 0x0 – Select reference clock from Bump
139 * 0x1 – Select inter-macro reference clock from the left side
140 * 0x2 – Same as 0x0
141 * 0x3 – Select inter-macro reference clock from the right side
143 #define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_MASK 0x00000003
144 #define SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT 0
147 (0 << (SERDES_C_GEN_CTRL_REFCLK_INPUT_SEL_SHIFT))
154 * 0x0 – Tied to 0 to save power
155 * 0x1 – Select reference clock from Bump
156 * 0x2 – Select inter-macro reference clock input from right side
157 * 0x3 – Same as 0x2
159 #define SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_MASK 0x00000030
163 (0 << (SERDES_C_GEN_CTRL_REFCLK_LEFT_SEL_SHIFT))
170 * 0x0 – Tied to 0 to save power
171 * 0x1 – Select reference clock from Bump
172 * 0x2 – Select inter-macro reference clock input from left side
173 * 0x3 – Same as 0x2
175 #define SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_MASK 0x000000C0
179 (0 << (SERDES_C_GEN_CTRL_REFCLK_RIGHT_SEL_SHIFT))
189 * is driven to 0
196 * is driven to 0
200 * 0 - keep cpu clk as sb clk
205 * 0x0 – OIF CEI-28G-SR
206 * 0x1 – OIF CIE-25G-LR
207 * 0x8 – XFI
212 #define SERDES_C_GEN_CTRL_PHY_CTRL_CFG_MASK 0x00F00000
215 * 0 - Internal 8051 micro- controller is allowed to access the internal APB
228 #define SERDES_C_GEN_CPU_PROG_ADDR_VAL_MASK 0x00007FFF
229 #define SERDES_C_GEN_CPU_PROG_ADDR_VAL_SHIFT 0
233 #define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_MASK 0x00001FFF
234 #define SERDES_C_GEN_CPU_DATA_MEM_ADDR_VAL_SHIFT 0
238 #define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_MASK 0x000000FF
239 #define SERDES_C_GEN_CPU_DATA_MEM_DATA_VAL_SHIFT 0
243 #define SERDES_C_GEN_RST_POR_N (1 << 0)
247 * 0x0 – Normal / Active
248 * 0x1 – Partial power down
249 * 0x2 – Near complete power down (only
252 * 0x3 – complete power down (IDDQ mode)
259 #define SERDES_C_GEN_RST_CM0_PD_MASK 0x00000030
266 * 0x0 – Normal / Active
267 * 0x1 – Partial power down
268 * 0x2 – Most blocks powered down (only LOS
270 * 0x3 – complete power down (IDDQ mode)
277 #define SERDES_C_GEN_RST_LN0_PD_MASK 0x00000300
280 * 0x0 – Normal / Active
281 * 0x1 – Partial power down
282 * 0x2 – Most blocks powered down (only LOS
284 * 0x3 – complete power down (IDDQ mode)
291 #define SERDES_C_GEN_RST_LN1_PD_MASK 0x00000C00
302 * 0x0 – No error
303 * 0x1 – PHY has an internal error
305 #define SERDES_C_GEN_STATUS_ERR_O (1 << 0)
307 * 0x0 – PHY is not ready to respond to
308 * cm0_rst_n_i and cm0_pd_i[1:0]. The
310 * 0x1 - PHY is ready to respond to
311 * cm0_rst_n_i and cm0_pd_i[1:0]
321 * 0x0 – PHY is not ready to respond to
322 * ln0_rst_n and ln0_pd[1:0]. The signals
324 * 0x1 - PHY is ready to respond to lnX_rst_n_i
325 * and lnX_pd_i[1:0]
329 * 0x0 – PHY is not ready to respond to
330 * ln1_rst_n_i and ln1_pd[1:0]. The signals
332 * 0x1 - PHY is ready to respond to lnX_rst_n_i
333 * and lnX_pd_i[1:0]
342 #define SERDES_C_GEN_STATUS_TBUS_MASK 0x000FFF00
347 #define SERDES_C_LANE_CFG_RX_LANE_SWAP (1 << 0)
355 * 0x0 –Data on lnX_txdata_o will not be
358 * 0x1 – Data on the active bits of
366 * 0x0 – LOS operates as normal
367 * 0x1 – Bypass analog LOS output and
378 #define SERDES_C_LANE_CFG_TX_DATA_SRC_SELECT_MASK 0x00000F00
380 /* 0x0 - 20-bit 0x1 – 40-bit */
386 * 0x1 – lane is ready to send and receive data
388 #define SERDES_C_LANE_STAT_LNX_STAT_OK (1 << 0)
390 * 0x0 – received data run length has not
393 * 0x1 – received data run length has
399 * 0x0 – data on lnX_rxdata_o are invalid
400 * 0x1 – data on the active bits of
409 * 0x0 – Signal detected on lnX_rxp_i /
411 * 0x1 – No signal detected on lnX_rxp_i /
420 #define SERDES_C_LANE_RESERVED_DEF_0_MASK 0x0000FFFF
421 #define SERDES_C_LANE_RESERVED_DEF_0_SHIFT 0
423 #define SERDES_C_LANE_RESERVED_DEF_1_MASK 0xFFFF0000