Lines Matching +full:0 +full:x3e000000
21 #define IQK_DONE_8822C 0xaa
57 efuse->country_code[0] = map->country_code[0];
60 efuse->regd = map->rf_board_option & 0x7;
65 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf;
67 for (i = 0; i < 4; i++)
85 return 0;
115 u32 rf_addr[DACK_RF_8822C] = {0x8f};
116 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110,
117 0x1c3c, 0x1c24, 0x1d70, 0x9b4,
118 0x1a00, 0x1a14, 0x1d58, 0x1c38,
119 0x1e24, 0x1e28, 0x1860, 0x4160};
121 for (i = 0; i < DACK_REG_8822C; i++) {
127 for (path = 0; path < DACK_PATH_8822C; path++) {
128 for (i = 0; i < DACK_RF_8822C; i++) {
147 for (path = 0; path < DACK_PATH_8822C; path++) {
148 for (i = 0; i < DACK_RF_8822C; i++) {
159 if (value >= 0x200) {
160 if (*min >= 0x200) {
166 if (*max >= 0x200) {
171 if (*min < 0x200) {
176 if (*max >= 0x200) {
187 if (*v1 >= 0x200 && *v2 >= 0x200) {
190 } else if (*v1 < 0x200 && *v2 < 0x200) {
193 } else if (*v1 < 0x200 && *v2 >= 0x200) {
202 for (i = 0; i < DACK_SN_8822C - 1; i++) {
203 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
214 m = 0;
215 p = 0;
217 if (vec[i] > 0x200)
218 m = (0x400 - vec[i]) + m;
229 if (t != 0x0)
230 t = 0x400 - t;
242 base_addr = 0x1800;
245 base_addr = 0x4100;
261 base_addr = 0x2800;
264 base_addr = 0x4500;
278 if ((value >= 0x200 && (0x400 - value) > 0x64) ||
279 (value < 0x200 && value > 0x64)) {
290 int i = 0, cnt = 0;
294 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
295 iv[i] = (temp & 0x3ff000) >> 12;
296 qv[i] = temp & 0x3ff;
308 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0;
311 int i, cnt = 0;
314 i_min = iv[0];
315 i_max = iv[0];
316 q_min = qv[0];
317 q_max = qv[0];
318 for (i = 0; i < DACK_SN_8822C; i++) {
323 if (i_max < 0x200 && i_min < 0x200)
325 else if (i_max >= 0x200 && i_min >= 0x200)
328 i_delta = i_max + (0x400 - i_min);
330 if (q_max < 0x200 && q_min < 0x200)
332 else if (q_max >= 0x200 && q_min >= 0x200)
335 q_delta = q_max + (0x400 - q_min);
338 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n",
341 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n",
347 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
348 iv[0] = (temp & 0x3ff000) >> 12;
349 qv[0] = temp & 0x3ff;
350 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
351 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
352 qv[DACK_SN_8822C - 1] = temp & 0x3ff;
368 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
369 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
372 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
380 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
381 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
382 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
383 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
384 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
385 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
386 rtw_write32(rtwdev, 0x1b00, 0x00000008);
387 rtw_write8(rtwdev, 0x1bcc, 0x3f);
388 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
389 rtw_write8(rtwdev, 0x1bcc, 0x3f);
390 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
391 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
398 u32 ic = 0, qc = 0, temp = 0;
408 path_sel = 0xa0000;
411 path_sel = 0x80000;
419 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
421 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
422 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
423 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
424 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
425 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
426 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
427 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
428 for (i = 0; i < 10; i++) {
430 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
431 rtw_write32(rtwdev, 0x1c24, 0x00010002);
434 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc);
437 if (ic != 0x0) {
438 ic = 0x400 - ic;
441 if (qc != 0x0) {
442 qc = 0x400 - qc;
445 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
446 rtw_write32(rtwdev, base_addr + 0x68, temp);
448 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
449 base_addr + 0x68, temp);
451 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
454 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc);
455 if (ic >= 0x200)
456 ic = 0x400 - ic;
457 if (qc >= 0x200)
458 qc = 0x400 - qc;
464 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
465 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
466 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
469 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
481 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
482 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
484 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
485 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
487 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
488 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
489 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
490 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
491 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
492 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
493 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
494 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
495 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
497 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
499 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
500 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
502 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
503 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
505 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
506 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
508 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
510 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
511 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
512 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
513 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
514 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
524 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
525 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
526 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
527 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
529 rtw_write32(rtwdev, 0x1b00, 0x00000008);
530 rtw_write8(rtwdev, 0x1bcc, 0x03f);
531 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
532 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
533 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
540 if (ic != 0x0)
541 ic = 0x400 - ic;
542 if (qc != 0x0)
543 qc = 0x400 - qc;
544 if (ic < 0x300) {
546 ic = ic + 0x80;
548 ic = (0x400 - ic) * 2 * 6 / 5;
549 ic = 0x7f - ic;
551 if (qc < 0x300) {
553 qc = qc + 0x80;
555 qc = (0x400 - qc) * 2 * 6 / 5;
556 qc = 0x7f - qc;
562 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
563 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
581 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
582 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
583 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
584 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
585 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
586 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
587 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
588 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
589 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
590 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
591 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
592 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
593 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
594 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
596 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
598 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
599 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
601 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
602 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
604 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
605 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
607 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
609 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
610 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
613 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10);
614 rtw_write32(rtwdev, base_addr + 0x68, temp);
615 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
616 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
618 if (ic >= 0x10)
619 ic = ic - 0x10;
621 ic = 0x400 - (0x10 - ic);
623 if (qc >= 0x10)
624 qc = qc - 0x10;
626 qc = 0x400 - (0x10 - qc);
631 if (ic >= 0x200)
632 ic = 0x400 - ic;
633 if (qc >= 0x200)
634 qc = 0x400 - qc;
640 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out);
647 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
648 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
649 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
650 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
663 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
664 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
665 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
672 u32 w_off = 0x1c;
673 u32 r_off = 0x2c;
680 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0;
681 r_addr = rtw8822c_get_path_read_addr(path) + 0x10;
682 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
685 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
686 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off;
695 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
696 dm_info->dack_dck[RF_PATH_A][0][0] = val;
697 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
698 dm_info->dack_dck[RF_PATH_A][0][1] = val;
699 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
700 dm_info->dack_dck[RF_PATH_A][1][0] = val;
701 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
704 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
705 dm_info->dack_dck[RF_PATH_B][0][0] = val;
706 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
707 dm_info->dack_dck[RF_PATH_B][1][0] = val;
708 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
709 dm_info->dack_dck[RF_PATH_B][0][1] = val;
710 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
718 temp[0] = rtw_read32(rtwdev, 0x1860);
719 temp[1] = rtw_read32(rtwdev, 0x4160);
720 temp[2] = rtw_read32(rtwdev, 0x9b4);
723 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
726 rtw_write32_clr(rtwdev, 0x1830, BIT(30));
727 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
731 rtw_write32_clr(rtwdev, 0x4130, BIT(30));
732 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
736 rtw_write32_set(rtwdev, 0x1830, BIT(30));
737 rtw_write32_set(rtwdev, 0x4130, BIT(30));
739 rtw_write32(rtwdev, 0x1860, temp[0]);
740 rtw_write32(rtwdev, 0x4160, temp[1]);
741 rtw_write32(rtwdev, 0x9b4, temp[2]);
750 val = dm_info->dack_dck[RF_PATH_A][0][0];
751 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
752 val = dm_info->dack_dck[RF_PATH_A][0][1];
753 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
756 val = dm_info->dack_dck[RF_PATH_A][1][0];
757 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
759 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
762 val = dm_info->dack_dck[RF_PATH_B][0][0];
763 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
764 val = dm_info->dack_dck[RF_PATH_B][0][1];
765 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
768 val = dm_info->dack_dck[RF_PATH_B][1][0];
769 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
771 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
776 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
778 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
779 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
780 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
781 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
783 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
784 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
785 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
786 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
788 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
789 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
790 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
791 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
793 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
794 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
795 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
796 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
798 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
799 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
800 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
801 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
805 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
806 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
807 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
808 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
810 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
811 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
813 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
814 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
815 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
816 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
818 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
819 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
820 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
821 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
823 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
824 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
830 u32 cnt = 0;
833 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
834 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
836 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
847 u32 w_off = 0x1c;
848 u32 r_off = 0x2c;
853 w_i = rtw8822c_get_path_write_addr(path) + 0xb0;
854 r_i = rtw8822c_get_path_read_addr(path) + 0x08;
855 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
856 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off;
858 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
861 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
862 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
863 value = dm_info->dack_msbk[path][0][i];
864 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
865 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
866 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
869 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
871 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
874 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
875 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
877 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
878 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
879 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
881 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
883 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
884 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
885 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
886 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
908 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
909 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
910 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
911 dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
914 temp[0] = rtw_read32(rtwdev, 0x1860);
915 temp[1] = rtw_read32(rtwdev, 0x4160);
916 temp[2] = rtw_read32(rtwdev, 0x9b4);
919 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
920 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
921 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
922 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
930 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
931 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
932 rtw_write32(rtwdev, 0x1860, temp[0]);
933 rtw_write32(rtwdev, 0x4160, temp[1]);
934 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
935 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
936 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
937 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
938 rtw_write32(rtwdev, 0x9b4, temp[2]);
947 u32 ic = 0, qc = 0, i;
948 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
949 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
950 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
963 for (i = 0; i < 10; i++) {
979 for (i = 0; i < 10; i++) {
993 rtw_write32(rtwdev, 0x1b00, 0x00000008);
994 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
995 rtw_write8(rtwdev, 0x1bcc, 0x0);
996 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
997 rtw_write8(rtwdev, 0x1bcc, 0x0);
1004 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
1005 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
1006 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
1007 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
1015 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
1017 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
1018 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
1019 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
1028 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \
1029 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \
1031 } while (0)
1034 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1035 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1);
1036 RF_SET_POWER_TRIM(path, 0x0, 0);
1037 RF_SET_POWER_TRIM(path, 0x1, 1);
1038 RF_SET_POWER_TRIM(path, 0x2, 2);
1039 RF_SET_POWER_TRIM(path, 0x3, 2);
1040 RF_SET_POWER_TRIM(path, 0x4, 3);
1041 RF_SET_POWER_TRIM(path, 0x5, 4);
1042 RF_SET_POWER_TRIM(path, 0x6, 5);
1043 RF_SET_POWER_TRIM(path, 0x7, 6);
1044 RF_SET_POWER_TRIM(path, 0x8, 7);
1045 RF_SET_POWER_TRIM(path, 0x9, 3);
1046 RF_SET_POWER_TRIM(path, 0xa, 4);
1047 RF_SET_POWER_TRIM(path, 0xb, 5);
1048 RF_SET_POWER_TRIM(path, 0xc, 6);
1049 RF_SET_POWER_TRIM(path, 0xd, 7);
1050 RF_SET_POWER_TRIM(path, 0xe, 7);
1051 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0);
1058 u8 pg_pwr = 0xff, i, path, idx;
1067 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) {
1076 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) {
1077 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1096 u8 pg_therm = 0xff, thermal[2] = {0}, path;
1098 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1102 /* Efuse value of BIT(0) shall be move to BIT(3), and the value
1106 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0));
1107 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]);
1115 u8 pg_pa_bias = 0xff, path;
1117 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1125 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1146 u4b_tmp == 0, 20, 600000, false,
1184 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1187 is_power_save ? 0 : 1);
1196 for (i = 0; i < reg_num; i++) {
1199 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n",
1210 for (i = 0; i < reg_num; i++) {
1212 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n",
1238 rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2);
1252 rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1);
1254 BIT_IQK_DPK_CLOCK_SRC, 0x1);
1256 BIT_IQK_DPK_RESET_SRC, 0x1);
1257 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1);
1258 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0);
1259 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff);
1263 BIT_RFTXEN_GCK_FORCE_ON, 0x1);
1264 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1);
1266 BIT_TX_SCALE_0DB, 0x1);
1267 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0);
1270 BIT_RFTXEN_GCK_FORCE_ON, 0x1);
1272 BIT_DIS_SHARERX_TXGAT, 0x1);
1274 BIT_TX_SCALE_0DB, 0x1);
1275 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0);
1277 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2);
1296 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1297 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1298 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001);
1299 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001);
1300 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001);
1301 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001);
1302 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001);
1303 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001);
1304 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001);
1305 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001);
1306 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001);
1307 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001);
1308 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001);
1309 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001);
1310 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001);
1311 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001);
1312 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1313 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1330 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e);
1331 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041);
1332 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041);
1333 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041);
1334 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041);
1335 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041);
1336 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041);
1337 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041);
1338 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041);
1339 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041);
1340 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041);
1341 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041);
1342 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041);
1343 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041);
1344 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041);
1345 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041);
1346 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041);
1353 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0);
1354 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0);
1355 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0);
1357 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1358 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1359 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1360 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1361 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1);
1362 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1363 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1364 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1365 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1366 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0);
1370 BIT_RFTXEN_GCK_FORCE_ON, 0x0);
1371 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0);
1373 BIT_TX_SCALE_0DB, 0x0);
1374 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3);
1377 BIT_RFTXEN_GCK_FORCE_ON, 0x0);
1379 BIT_DIS_SHARERX_TXGAT, 0x0);
1381 BIT_TX_SCALE_0DB, 0x0);
1382 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3);
1385 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0);
1386 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5);
1391 if ((FIELD_GET(BIT_GAIN_TX_PAD_H, gain) >= 0xc) &&
1392 (FIELD_GET(BIT_GAIN_TX_PAD_L, gain) >= 0xe))
1402 u32 v, tmp_3f = 0;
1409 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1412 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2);
1415 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3);
1418 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4);
1424 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88);
1426 check_txgain = 0;
1427 for (gain = 0; gain < RF_GAIN_NUM; gain++) {
1435 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n",
1443 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1);
1444 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0);
1447 "[TXGAPK] Band=%d 0x1b98[11:0]=0x%03X path=%d\n",
1459 for (band = 0; band < RF_BAND_MAX; band++) {
1460 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1469 static const u32 cfg1_1b00[2] = {0x00000d18, 0x00000d2a};
1470 static const u32 cfg2_1b00[2] = {0x00000d19, 0x00000d2b};
1487 rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000);
1488 rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3);
1489 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312);
1490 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1);
1491 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0);
1492 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1);
1493 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820);
1495 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1497 rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018);
1509 val == 0x55, 1000, 100000, false,
1512 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2);
1514 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1);
1515 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12);
1516 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3);
1519 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1528 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4);
1534 for (i = 0; i < RF_HW_OFFSET_NUM; i++)
1537 0xf0;
1538 for (i = 0; i < RF_HW_OFFSET_NUM; i++)
1550 u32 reg_backup[ARRAY_SIZE(bb_reg)] = {0};
1560 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1562 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1563 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1564 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1565 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f);
1566 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0);
1567 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1);
1568 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f);
1569 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1570 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
1571 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1572 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1574 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00);
1575 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1582 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1584 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1585 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1586 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1587 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011);
1588 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3);
1589 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3);
1590 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
1592 RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0x2);
1593 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12);
1594 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1595 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1596 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1597 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5);
1599 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1603 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2);
1606 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3);
1609 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4);
1625 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3);
1626 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0);
1627 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0);
1639 "[TXGAPK] gain=0x%03X(>=0xCEX) offset=%d new_gain=0x%03X\n",
1645 new_gain = (gain_x2 >> 1) | (gain_x2 & BIT(0) ? BIT_GAIN_EXT : 0);
1648 "[TXGAPK] gain=0x%X offset=%d new_gain=0x%X\n",
1657 u32 i, j, tmp = 0x20, tmp_3f, v;
1658 s8 offset_tmp[RF_GAIN_NUM] = {0};
1664 tmp = 0x20;
1667 tmp = 0x200;
1670 tmp = 0x280;
1673 tmp = 0x300;
1680 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1681 for (i = 0; i < RF_GAIN_NUM; i++) {
1682 offset_tmp[i] = 0;
1695 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n",
1705 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000);
1706 for (i = 0; i < RF_GAIN_NUM; i++) {
1717 "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n",
1720 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0);
1729 static const u8 band_num[RF_BAND_MAX] = {0x0, 0x0, 0x1, 0x3, 0x5};
1730 static const u8 cck[RF_BAND_MAX] = {0x1, 0x0, 0x0, 0x0, 0x0};
1746 for (band = 0; band < RF_BAND_MAX; band++) {
1747 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1751 three_wire[path], BIT_3WIRE_EN, 0x0);
1760 gain = 0;
1769 "[TXGAPK] 0x5f=0x%03X band=%d path=%d\n",
1776 three_wire[path], BIT_3WIRE_EN, 0x3);
1794 if (txgapk->read_txgain == 0) {
1796 "[TXGAPK] txgapk->read_txgain == 0 return!!!\n");
1810 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1853 dm_info->delta_power_index[path] = 0;
1855 dm_info->thermal_avg[path] = 0xff;
1868 u8 cck_gi_u_bnd_msb = 0;
1869 u8 cck_gi_u_bnd_lsb = 0;
1870 u8 cck_gi_l_bnd_msb = 0;
1871 u8 cck_gi_l_bnd_lsb = 0;
1889 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1890 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1901 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1902 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1903 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1904 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1915 #define WLAN_TXQ_RPT_EN 0x1F
1916 #define WLAN_SLOT_TIME 0x09
1917 #define WLAN_PIFS_TIME 0x1C
1918 #define WLAN_SIFS_CCK_CONT_TX 0x0A
1919 #define WLAN_SIFS_OFDM_CONT_TX 0x0E
1920 #define WLAN_SIFS_CCK_TRX 0x0A
1921 #define WLAN_SIFS_OFDM_TRX 0x10
1922 #define WLAN_NAV_MAX 0xC8
1923 #define WLAN_RDG_NAV 0x05
1924 #define WLAN_TXOP_NAV 0x1B
1925 #define WLAN_CCK_RX_TSF 0x30
1926 #define WLAN_OFDM_RX_TSF 0x30
1927 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
1928 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
1929 #define WLAN_DRV_EARLY_INT 0x04
1930 #define WLAN_BCN_CTRL_CLT0 0x10
1931 #define WLAN_BCN_DMA_TIME 0x02
1932 #define WLAN_BCN_MAX_ERR 0xFF
1933 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A
1934 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10
1935 #define WLAN_SIFS_CCK_CTX 0x0A
1936 #define WLAN_SIFS_CCK_IRX 0x0A
1937 #define WLAN_SIFS_OFDM_CTX 0x0E
1938 #define WLAN_SIFS_OFDM_IRX 0x0E
1939 #define WLAN_EIFS_DUR_TUNE 0x40
1940 #define WLAN_EDCA_VO_PARAM 0x002FA226
1941 #define WLAN_EDCA_VI_PARAM 0x005EA328
1942 #define WLAN_EDCA_BE_PARAM 0x005EA42B
1943 #define WLAN_EDCA_BK_PARAM 0x0000A44F
1945 #define WLAN_RX_FILTER0 0xFFFFFFFF
1946 #define WLAN_RX_FILTER2 0xFFFF
1947 #define WLAN_RCR_CFG 0xE400220E
1951 #define WLAN_AMPDU_MAX_TIME 0x70
1952 #define WLAN_RTS_LEN_TH 0xFF
1953 #define WLAN_RTS_TX_TIME_TH 0x08
1954 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f
1955 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f
1956 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0
1957 #define FAST_EDCA_VO_TH 0x06
1958 #define FAST_EDCA_VI_TH 0x06
1959 #define FAST_EDCA_BE_TH 0x06
1960 #define FAST_EDCA_BK_TH 0x06
1961 #define WLAN_BAR_RETRY_LIMIT 0x01
1962 #define WLAN_BAR_ACK_TYPE 0x05
1963 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
1964 #define WLAN_RESP_TXRATE 0x84
1965 #define WLAN_ACK_TO 0x21
1966 #define WLAN_ACK_TO_CCK 0x6A
1967 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000
1968 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504
1969 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504
1970 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010
1971 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000
1972 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010
1973 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000
1974 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010
1975 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0
1976 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015
1977 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0
1978 #define WLAN_MULTI_ADDR 0xFFFFFFFF
1980 #define WLAN_TX_FUNC_CFG1 0x30
1981 #define WLAN_TX_FUNC_CFG2 0x30
1982 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
1983 #define WLAN_MAC_OPT_LB_FUNC1 0x80
1984 #define WLAN_MAC_OPT_FUNC2 0xb0810041
1985 #define WLAN_MAC_INT_MIG_CFG 0x33330000
2002 #define EFUSE_PCB_INFO_OFFSET 0xCA
2039 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
2074 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
2107 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
2111 value16 = 0;
2117 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
2122 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07);
2130 return 0;
2133 #define FWCD_SIZE_REG_8822C 0x2000
2134 #define FWCD_SIZE_DMEM_8822C 0x10000
2135 #define FWCD_SIZE_IMEM_8822C 0x10000
2136 #define FWCD_SIZE_EMEM_8822C 0x20000
2137 #define FWCD_SIZE_ROM_8822C 0x10000
2159 ret = rtw_dump_reg(rtwdev, 0x0, FWCD_SIZE_REG_8822C);
2175 return 0;
2183 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1);
2184 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1);
2185 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1);
2187 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0);
2194 #define RF18_BAND_2G (0)
2205 u32 rf_reg18 = 0;
2206 u32 rf_rxbb = 0;
2209 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2230 rf_rxbb = 0x18;
2235 rf_rxbb = 0x10;
2239 rf_rxbb = 0x8;
2245 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
2246 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
2247 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
2248 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
2250 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
2251 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
2252 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
2253 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
2265 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
2266 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
2267 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
2268 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
2269 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
2280 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
2285 0x5);
2287 0x5);
2289 0x6);
2291 0x6);
2295 0x4);
2297 0x4);
2299 0x0);
2301 0x0);
2305 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
2307 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
2309 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
2311 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
2313 0x4962c931);
2314 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
2315 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
2316 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
2317 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
2319 0xff012455);
2320 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
2322 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
2324 0x3e18fec8);
2325 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
2326 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
2327 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
2329 0x00faf0de);
2331 0x00122344);
2333 0x0fffffff);
2336 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2338 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
2344 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
2345 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2348 0x1);
2350 0x1);
2353 0x2);
2355 0x2);
2358 0x3);
2360 0x3);
2364 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
2366 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
2368 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
2370 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
2372 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
2374 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
2379 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
2380 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2381 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
2382 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
2383 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
2384 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2385 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2386 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2390 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
2391 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
2392 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2393 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2395 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
2396 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2397 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2400 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
2401 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2402 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2404 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
2405 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2408 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2409 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2410 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
2411 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
2412 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
2413 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2414 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2415 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2418 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2419 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2420 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
2421 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
2422 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
2423 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2424 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2425 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2442 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
2443 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
2445 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
2446 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
2450 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
2452 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
2454 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
2460 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
2461 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
2462 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
2463 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
2464 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
2466 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
2467 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
2468 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
2469 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
2470 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
2473 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
2474 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
2487 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2489 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
2492 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
2494 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2503 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
2504 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2506 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
2507 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2510 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
2511 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
2513 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x32);
2514 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2516 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
2517 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2537 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
2539 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
2541 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
2543 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
2583 if (channel != 0)
2591 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2610 u8 evm_dbm = 0;
2620 if (rxsc == 0)
2651 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2666 if (rx_evm < 0) {
2668 evm_dbm = 0;
2682 page = *phy_status & 0xf;
2685 case 0:
2702 u32 txref_cck[2] = {0x18a0, 0x41a0};
2703 u32 txref_ofdm[2] = {0x18e8, 0x41e8};
2706 for (path = 0; path < hal->rf_path_num; path++) {
2707 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2708 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
2711 for (path = 0; path < hal->rf_path_num; path++) {
2712 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2713 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
2721 u32 offset_txagc = 0x3a00;
2722 u8 rate_idx = rate & 0xfc;
2727 for (i = 0; i < 4; i++)
2728 pwr_idx[i] = diff_idx[i] & 0x7f;
2730 phy_pwr_idx = pwr_idx[0] |
2735 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
2753 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
2754 for (j = 0; j < rtw_rate_size[rs]; j++) {
2758 if (rs == 0) {
2759 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
2762 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
2785 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
2795 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
2804 return 0;
2838 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2);
2840 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3);
2841 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4);
2843 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5);
2852 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
2854 crc32_cnt = rtw_read32(rtwdev, 0x2c04);
2855 dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
2856 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2857 crc32_cnt = rtw_read32(rtwdev, 0x2c14);
2858 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
2859 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2860 crc32_cnt = rtw_read32(rtwdev, 0x2c10);
2861 dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
2862 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2863 crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
2864 dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
2865 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2867 cca32_cnt = rtw_read32(rtwdev, 0x2c08);
2868 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
2869 dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
2874 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
2876 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
2890 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2891 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA);
2893 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000);
2894 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001);
2895 read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000,
2896 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000);
2897 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8);
2898 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2900 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2901 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000);
2903 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2908 struct rtw_iqk_para para = {0};
2920 rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
2930 /* 0x790[5:0]=0x5 */
2931 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
2934 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
2950 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000);
2965 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
2966 rf_0x1 = 0x40021;
2968 rf_0x1 = 0x40000;
2974 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
2978 * disable:0x1860[3] = 1, enable:0x1860[3] = 0
2980 * enable "DAC off if GNT_WL = 0" for non-shared-antenna
2981 * disable 0x1c30[22] = 0,
2982 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1
2986 BIT_ANAPAR_BTPS >> 16, 0);
2991 BIT_DAC_OFF_ENABLE, 0);
3014 BIT_PI_IGNORE_GNT_BT, 0);
3024 BIT_PI_IGNORE_GNT_BT, 0);
3027 BIT_NOMASK_TXBT_ENABLE, 0);
3034 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
3035 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
3036 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
3037 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
3038 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
3048 coex_rfe->ant_switch_polarity = 0;
3059 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
3060 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
3061 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
3089 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22);
3090 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36);
3091 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22);
3092 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36);
3098 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20);
3099 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0);
3100 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20);
3101 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0);
3109 u8 csi_rsc = 0;
3122 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550);
3179 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
3180 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
3181 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
3182 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
3184 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
3186 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
3195 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3196 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
3205 for (i = 0; i < reg_num; i++) {
3218 for (i = 0; i < DPK_RF_REG_NUM; i++) {
3232 for (i = 0; i < DPK_RF_REG_NUM; i++) {
3247 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
3254 dpk_info->dpk_ch = FIELD_GET(0xff, reg);
3255 dpk_info->dpk_bw = FIELD_GET(0x3000, reg);
3260 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3262 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
3264 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3272 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
3274 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
3277 dc_i = 0x1000 - dc_i;
3279 dc_q = 0x1000 - dc_q;
3281 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3282 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
3288 return 0;
3295 u16 count = 0;
3297 rtw_write8(rtwdev, 0x522, 0xff);
3298 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
3301 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
3302 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
3326 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3327 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
3328 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3330 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
3332 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
3333 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
3334 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
3336 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3337 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
3338 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
3345 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
3348 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
3349 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
3350 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0);
3354 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1);
3355 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
3357 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
3358 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
3359 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
3360 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
3363 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3364 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
3365 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
3368 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
3370 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
3372 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
3376 return ori_txbb & 0x1f;
3382 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
3386 cmd = 0x14 + path;
3389 cmd = 0x16 + path + bw;
3392 cmd = 0x1a + path;
3395 cmd = 0x1c + path + bw;
3398 return 0;
3401 return (cmd << 8) | 0x48;
3407 u8 result = 0;
3412 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
3413 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
3414 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3416 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
3422 0x8 | (path << 1));
3423 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3429 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
3434 0x8 | (path << 1));
3435 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3440 rtw_write8(rtwdev, 0x1b10, 0x0);
3449 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3450 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
3459 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3460 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
3461 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3464 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
3471 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3472 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3473 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
3474 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3475 rtw_write32(rtwdev, 0x1b4c, 0x00080000);
3481 i_val = 0x10000 - i_val;
3483 q_val = 0x10000 - q_val;
3485 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3494 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174,
3496 42, 32, 23, 15, 7, 0};
3498 if (val == 0)
3499 return 0;
3520 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3521 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
3522 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
3524 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
3526 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3534 u8 result = 0;
3553 if (loss < 0x4000000)
3610 if (pga > 0xe)
3611 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3612 else if (pga > 0xb && pga < 0xf)
3613 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
3614 else if (pga < 0xc)
3625 if (pga < 0xc)
3626 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3627 else if (pga > 0xb && pga < 0xf)
3628 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3629 else if (pga > 0xe)
3638 u8 txbb_bound[] = {0x1f, 0};
3649 data->limited_pga = 0;
3663 return rtw8822c_gl_state(rtwdev, data, 0);
3687 struct rtw8822c_dpk_data data = {0};
3708 if (coef_i == 0x1000 || coef_i == 0x0fff ||
3709 coef_q == 0x1000 || coef_q == 0x0fff)
3717 u32 reg = 0;
3718 u16 coef_i = 0, coef_q = 0;
3722 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
3723 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
3725 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1;
3733 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0,
3734 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0,
3735 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0,
3736 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0,
3744 for (i = 0; i < 20; i++) {
3753 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
3756 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0);
3757 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080);
3759 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1);
3760 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080);
3772 for (addr = 0; addr < 20; addr++) {
3773 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]);
3774 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]);
3777 result = 0;
3787 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64};
3791 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
3792 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3794 for (addr = 0; addr < 20; addr++) {
3795 if (result == 0) {
3797 coef = 0x04001fff;
3799 coef = 0x00001fff;
3812 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3817 rtw_write8(rtwdev, REG_DPD_AGC, 0x00);
3848 tx_bb = 0;
3869 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3873 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
3883 u32 tmp_gs = 0;
3885 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3886 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0);
3887 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3888 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3889 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1);
3890 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3891 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf);
3895 0x1066680);
3896 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1);
3899 0x1066680);
3900 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1);
3904 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310);
3905 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310);
3906 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db);
3907 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db);
3908 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3910 0x05020000 | (BIT(path) << 28));
3912 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c);
3913 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c);
3914 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14);
3915 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14);
3916 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3918 0x05020008 | (BIT(path) << 28));
3921 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
3925 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0);
3926 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3927 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3928 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0);
3929 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3932 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b);
3934 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b);
3936 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3953 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58};
3957 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3958 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3959 rtw_write32(rtwdev, REG_NCTL0, 0x00001148);
3960 rtw_write32(rtwdev, REG_NCTL0, 0x00001149);
3962 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55);
3964 rtw_write8(rtwdev, 0x1b10, 0x0);
3965 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3967 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3968 i_scaling = 0x16c00 / dpk_info->dpk_gs[path];
3970 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
3973 GENMASK(31, 28), 0x9);
3975 GENMASK(31, 28), 0x1);
3977 GENMASK(31, 28), 0x0);
3979 BIT(14), 0x0);
3989 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3990 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
4020 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4023 0x8 | (path << 1));
4024 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0);
4026 dpk_info->dpk_txagc[path] = 0;
4027 dpk_info->result[path] = 0;
4028 dpk_info->dpk_gs[path] = 0x5b;
4029 dpk_info->pre_pwsf[path] = 0;
4070 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
4078 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0);
4082 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0);
4094 dpk_info->dpk_ch == 0)
4097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4099 0x8 | (path << 1));
4101 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
4103 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
4112 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
4132 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff);
4134 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK) & 0xff);
4153 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864,
4154 0x4164, 0x180c, 0x410c, 0x186c, 0x416c,
4155 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4};
4157 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde};
4184 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
4202 u8 thermal_value[DPK_RF_PATH_NUM] = {0};
4205 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0)
4208 for (path = 0; path < DPK_RF_PATH_NUM; path++) {
4218 offset[path] &= 0x7f;
4222 0x8 | (path << 1));
4223 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
4235 u32 val = 0;
4280 s32 cfo_avg, cfo_path_sum = 0, cfo_rpt_sum;
4283 for (i = 0; i < path_num; i++) {
4289 cfo_avg = 0;
4294 for (i = 0; i < path_num; i++) {
4295 cfo->cfo_tail[i] = 0;
4296 cfo->cfo_cnt[i] = 0;
4327 s32 cfo_avg = 0;
4347 crystal_cap = clamp_t(s8, crystal_cap, 0, XCAP_MASK);
4355 {0x1ac8, 0x00ff, 0x1ad0, 0x01f},
4356 {0x1ac8, 0xff00, 0x1ad0, 0x3e0}
4359 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000},
4360 {0x1acc, 0xff00, 0x1ad0, 0x3E000000}
4401 "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n",
4408 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8};
4409 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4};
4413 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
4414 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
4435 #define PWR_TRACK_MASK 0x7f
4442 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK,
4446 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK,
4458 if (rtwdev->efuse.thermal_meter[path] == 0xff)
4461 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e);
4486 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4490 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4499 if (efuse->power_track_type != 0)
4503 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
4504 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00);
4505 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
4507 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
4508 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00);
4509 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
4537 igi = dm_info->igi_history[0];
4583 {0x0086,
4587 RTW_PWR_CMD_WRITE, BIT(0), 0},
4588 {0x0086,
4593 {0x002E,
4598 {0x002D,
4602 RTW_PWR_CMD_WRITE, BIT(0), 0},
4603 {0x007F,
4607 RTW_PWR_CMD_WRITE, BIT(7), 0},
4608 {0x004A,
4612 RTW_PWR_CMD_WRITE, BIT(0), 0},
4613 {0x0005,
4617 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
4618 {0xFFFF,
4621 0,
4622 RTW_PWR_CMD_END, 0, 0},
4626 {0x0000,
4630 RTW_PWR_CMD_WRITE, BIT(5), 0},
4631 {0x0005,
4635 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
4636 {0x0075,
4640 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4641 {0x0006,
4646 {0x0075,
4650 RTW_PWR_CMD_WRITE, BIT(0), 0},
4651 {0xFF1A,
4655 RTW_PWR_CMD_WRITE, 0xFF, 0},
4656 {0x002E,
4660 RTW_PWR_CMD_WRITE, BIT(3), 0},
4661 {0x0006,
4665 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4666 {0x0005,
4670 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
4671 {0x1018,
4676 {0x0005,
4680 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4681 {0x0005,
4685 RTW_PWR_CMD_POLLING, BIT(0), 0},
4686 {0x0074,
4691 {0x0071,
4695 RTW_PWR_CMD_WRITE, BIT(4), 0},
4696 {0x0062,
4702 {0x0061,
4706 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
4707 {0x001F,
4712 {0x00EF,
4717 {0x1045,
4722 {0x0010,
4727 {0x1064,
4732 {0xFFFF,
4735 0,
4736 RTW_PWR_CMD_END, 0, 0},
4740 {0x0093,
4744 RTW_PWR_CMD_WRITE, BIT(3), 0},
4745 {0x001F,
4749 RTW_PWR_CMD_WRITE, 0xFF, 0},
4750 {0x00EF,
4754 RTW_PWR_CMD_WRITE, 0xFF, 0},
4755 {0x1045,
4759 RTW_PWR_CMD_WRITE, BIT(4), 0},
4760 {0xFF1A,
4764 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
4765 {0x0049,
4769 RTW_PWR_CMD_WRITE, BIT(1), 0},
4770 {0x0006,
4774 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4775 {0x0002,
4779 RTW_PWR_CMD_WRITE, BIT(1), 0},
4780 {0x0005,
4785 {0x0005,
4789 RTW_PWR_CMD_POLLING, BIT(1), 0},
4790 {0x0000,
4795 {0xFFFF,
4798 0,
4799 RTW_PWR_CMD_END, 0, 0},
4803 {0x0005,
4808 {0x0007,
4812 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
4813 {0x0067,
4817 RTW_PWR_CMD_WRITE, BIT(5), 0},
4818 {0x004A,
4822 RTW_PWR_CMD_WRITE, BIT(0), 0},
4823 {0x0081,
4827 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
4828 {0x0090,
4832 RTW_PWR_CMD_WRITE, BIT(1), 0},
4833 {0x0092,
4837 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
4838 {0x0093,
4842 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
4843 {0x0005,
4848 {0x0005,
4853 {0x0086,
4857 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
4858 {0xFFFF,
4861 0,
4862 RTW_PWR_CMD_END, 0, 0},
4878 {0xFFFF, 0x00,
4885 {0xFFFF, 0x0000,
4892 {0xFFFF, 0x0000,
4899 {0xFFFF, 0x0000,
4917 [0] = { .addr = 0x1d70, .mask = 0x7f },
4918 [1] = { .addr = 0x1d70, .mask = 0x7f00 },
4930 {64, 64, 0, 0, 1},
4931 {64, 64, 64, 0, 1},
5011 {0xffffffff, 0xffffffff}, /* case-0 */
5012 {0x55555555, 0x55555555},
5013 {0x66555555, 0x66555555},
5014 {0xaaaaaaaa, 0xaaaaaaaa},
5015 {0x5a5a5a5a, 0x5a5a5a5a},
5016 {0xfafafafa, 0xfafafafa}, /* case-5 */
5017 {0x6a5a5555, 0xaaaaaaaa},
5018 {0x6a5a56aa, 0x6a5a56aa},
5019 {0x6a5a5a5a, 0x6a5a5a5a},
5020 {0x66555555, 0x5a5a5a5a},
5021 {0x66555555, 0x6a5a5a5a}, /* case-10 */
5022 {0x66555555, 0x6a5a5aaa},
5023 {0x66555555, 0x5a5a5aaa},
5024 {0x66555555, 0x6aaa5aaa},
5025 {0x66555555, 0xaaaa5aaa},
5026 {0x66555555, 0xaaaaaaaa}, /* case-15 */
5027 {0xffff55ff, 0xfafafafa},
5028 {0xffff55ff, 0x6afa5afa},
5029 {0xaaffffaa, 0xfafafafa},
5030 {0xaa5555aa, 0x5a5a5a5a},
5031 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
5032 {0xaa5555aa, 0xaaaaaaaa},
5033 {0xffffffff, 0x5a5a5a5a},
5034 {0xffffffff, 0x5a5a5a5a},
5035 {0xffffffff, 0x55555555},
5036 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
5037 {0x55555555, 0x5a5a5a5a},
5038 {0x55555555, 0xaaaaaaaa},
5039 {0x55555555, 0x6a5a6a5a},
5040 {0x66556655, 0x66556655},
5041 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/
5042 {0xffffffff, 0x5aaa5aaa},
5043 {0x56555555, 0x5a5a5aaa},
5044 {0xdaffdaff, 0xdaffdaff},
5045 {0xddffddff, 0xddffddff},
5050 {0xffffffff, 0xffffffff}, /* case-100 */
5051 {0x55555555, 0x55555555},
5052 {0x66555555, 0x66555555},
5053 {0xaaaaaaaa, 0xaaaaaaaa},
5054 {0x5a5a5a5a, 0x5a5a5a5a},
5055 {0xfafafafa, 0xfafafafa}, /* case-105 */
5056 {0x5afa5afa, 0x5afa5afa},
5057 {0x55555555, 0xfafafafa},
5058 {0x66555555, 0xfafafafa},
5059 {0x66555555, 0x5a5a5a5a},
5060 {0x66555555, 0x6a5a5a5a}, /* case-110 */
5061 {0x66555555, 0xaaaaaaaa},
5062 {0xffff55ff, 0xfafafafa},
5063 {0xffff55ff, 0x5afa5afa},
5064 {0xffff55ff, 0xaaaaaaaa},
5065 {0xffff55ff, 0xffff55ff}, /* case-115 */
5066 {0xaaffffaa, 0x5afa5afa},
5067 {0xaaffffaa, 0xaaaaaaaa},
5068 {0xffffffff, 0xfafafafa},
5069 {0xffffffff, 0x5afa5afa},
5070 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
5071 {0x55ff55ff, 0x5afa5afa},
5072 {0x55ff55ff, 0xaaaaaaaa},
5073 {0x55ff55ff, 0x55ff55ff}
5078 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
5079 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
5080 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
5081 { {0x61, 0x30, 0x03, 0x11, 0x11} },
5082 { {0x61, 0x20, 0x03, 0x11, 0x11} },
5083 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
5084 { {0x61, 0x45, 0x03, 0x11, 0x10} },
5085 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
5086 { {0x61, 0x30, 0x03, 0x11, 0x10} },
5087 { {0x61, 0x20, 0x03, 0x11, 0x10} },
5088 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
5089 { {0x61, 0x08, 0x03, 0x11, 0x14} },
5090 { {0x61, 0x08, 0x03, 0x10, 0x14} },
5091 { {0x51, 0x08, 0x03, 0x10, 0x54} },
5092 { {0x51, 0x08, 0x03, 0x10, 0x55} },
5093 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
5094 { {0x51, 0x45, 0x03, 0x10, 0x50} },
5095 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
5096 { {0x51, 0x30, 0x03, 0x10, 0x50} },
5097 { {0x51, 0x20, 0x03, 0x10, 0x50} },
5098 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
5099 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
5100 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
5101 { {0x55, 0x08, 0x03, 0x10, 0x54} },
5102 { {0x65, 0x10, 0x03, 0x11, 0x10} },
5103 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
5104 { {0x51, 0x08, 0x03, 0x10, 0x50} },
5105 { {0x61, 0x08, 0x03, 0x11, 0x11} }
5110 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
5111 { {0x61, 0x45, 0x03, 0x11, 0x11} },
5112 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
5113 { {0x61, 0x30, 0x03, 0x11, 0x11} },
5114 { {0x61, 0x20, 0x03, 0x11, 0x11} },
5115 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
5116 { {0x61, 0x45, 0x03, 0x11, 0x10} },
5117 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
5118 { {0x61, 0x30, 0x03, 0x11, 0x10} },
5119 { {0x61, 0x20, 0x03, 0x11, 0x10} },
5120 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
5121 { {0x61, 0x08, 0x03, 0x11, 0x14} },
5122 { {0x61, 0x08, 0x03, 0x10, 0x14} },
5123 { {0x51, 0x08, 0x03, 0x10, 0x54} },
5124 { {0x51, 0x08, 0x03, 0x10, 0x55} },
5125 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
5126 { {0x51, 0x45, 0x03, 0x10, 0x50} },
5127 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
5128 { {0x51, 0x30, 0x03, 0x10, 0x50} },
5129 { {0x51, 0x20, 0x03, 0x10, 0x50} },
5130 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
5131 { {0x51, 0x08, 0x03, 0x10, 0x50} }
5137 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} };
5141 {0, 0, false, 7}, /* for normal */
5142 {0, 16, false, 7}, /* for WL-CPT */
5147 {0, 21, true, 4} /* for gamg hid */
5151 {0, 0, false, 7}, /* for normal */
5152 {0, 16, false, 7}, /* for WL-CPT */
5156 {0, 28, true, 5},
5157 {0, 28, true, 5} /* for gamg hid */
5168 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5171 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5174 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10,
5181 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5184 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5187 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5194 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5197 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5200 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10,
5207 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5210 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5213 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5219 0, 1, 2, 3, 4, 4, 5, 6, 7, 8,
5225 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5231 0, 1, 2, 2, 3, 4, 4, 5, 6, 6,
5237 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5243 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
5249 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
5255 0, 1, 2, 3, 3, 4, 5, 6, 6, 7,
5261 0, 1, 2, 3, 4, 5, 5, 6, 7, 8,
5290 [0] = RTW_DEF_RFE(8822c, 0, 0, 0),
5291 [1] = RTW_DEF_RFE(8822c, 0, 0, 0),
5292 [2] = RTW_DEF_RFE(8822c, 0, 0, 0),
5293 [3] = RTW_DEF_RFE(8822c, 0, 0, 0),
5294 [4] = RTW_DEF_RFE(8822c, 0, 0, 0),
5295 [5] = RTW_DEF_RFE(8822c, 0, 5, 0),
5296 [6] = RTW_DEF_RFE(8822c, 0, 0, 0),
5301 {.addr = 0x84c, .mask = MASKBYTE2}, .offset = 0x80
5304 {.addr = 0x84c, .mask = MASKBYTE3}, .offset = 0x80
5321 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8},
5322 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8},
5323 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8},
5324 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32},
5325 {0, 0, RTW_REG_DOMAIN_NL},
5326 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5327 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5328 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
5329 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5330 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
5331 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
5332 {0, 0, RTW_REG_DOMAIN_NL},
5333 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
5334 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
5335 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
5336 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
5337 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
5338 {0, 0, RTW_REG_DOMAIN_NL},
5339 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
5340 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5341 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
5342 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
5363 .max_power_index = 0x7f,
5367 .dig_min = 0x20,
5377 .sys_func_en = 0xD8,
5386 .rf_base_addr = {0x3c00, 0x4c00},
5387 .rf_sipi_addr = {0x1808, 0x4108},
5415 .coex_para_ver = 0x22020720,
5416 .bt_desired_ver = 0x20,
5438 .bt_afh_span_bw20 = 0x24,
5439 .bt_afh_span_bw40 = 0x36,
5446 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},