Home
last modified time | relevance | path

Searched +full:0 +full:x19000 (Results 1 – 25 of 39) sorted by relevance

12

/linux/sound/pci/au88x0/
H A Dau88x0_a3d.h18 #define HRTF_SZ 0x38
19 #define DLINE_SZ 0x28
48 #define A3D_A_HrtfCurrent 0x18000 /* 56 ULONG */
49 #define A3D_A_GainCurrent 0x180E0
50 #define A3D_A_GainTarget 0x180E4
51 #define A3D_A_A12Current 0x180E8 /* Atmospheric current. */
52 #define A3D_A_A21Target 0x180EC /* Atmospheric target */
53 #define A3D_A_B01Current 0x180F0 /* Atmospheric current */
54 #define A3D_A_B10Target 0x180F4 /* Atmospheric target */
55 #define A3D_A_B2Current 0x180F8 /* Atmospheric current */
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-sata2-1.dtsi2 * PQ3 SATAv2 device tree stub [ controller @ offset 0x19000 ]
37 reg = <0x19000 0x1000>;
39 interrupts = <41 0x2 0 0>;
H A Dmpc8536si-post.dtsi39 interrupts = <19 2 0 0>;
42 /* controller at 0x8000 */
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
53 /* controller at 0x9000 */
59 bus-range = <0 255>;
61 interrupts = <25 2 0 0>;
63 pcie@0 {
64 reg = <0 0 0 0 0>;
69 interrupts = <25 2 0 0>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
H A Dmpc8377_wlan.dts28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
55 ranges = <0x0 0x0 0xfc000000 0x04000000>;
[all …]
H A Dmpc8379_rdb.dts25 #size-cells = <0>;
27 PowerPC,8379@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
56 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8315erdb.dts28 #size-cells = <0>;
30 PowerPC,8315@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader
45 reg = <0x00000000 0x08000000>; // 128MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
59 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8377_rdb.dts27 #size-cells = <0>;
29 PowerPC,8377@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/linux/arch/mips/include/asm/sn/sn0/
H A Dkldir.h28 * 0x2000000 (32M) +-----------------------------------------+
30 * 0x1F80000 (31.5M) +-----------------------------------------+
32 * 0x1C00000 (30M) +-----------------------------------------+
34 * 0x0800000 (28M) +-----------------------------------------+
36 * 0x1B00000 (27M) +-----------------------------------------+
38 * 0x1A00000 (26M) +-----------------------------------------+
40 * 0x1800000 (24M) +-----------------------------------------+
42 * 0x1600000 (22M) +-----------------------------------------+
48 * 0x190000 (2M--) +-----------------------------------------+
51 * 0x34000 (208K) +-----------------------------------------+
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dfsl,pq-sata.yaml38 1 for controller @ 0x18000
39 2 for controller @ 0x19000
40 3 for controller @ 0x1a000
41 4 for controller @ 0x1b000
55 reg = <0x18000 0x1000>;
/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0 0>;
28 reg = <0 1>;
35 reg = <0 2>;
42 reg = <0 3>;
77 reg = <0 0xc0010000 0 0x10000>;
87 reg = <0 0xd1df9000 0 0x1000>,
88 <0 0xd1dfa000 0 0x2000>,
90 <0 0xd1dfc000 0 0x2000>,
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dqcom,bam-dma.yaml64 minimum: 0
67 Indicates the active Execution Environment identifier (0-7) used in the
114 reg = <0xf9944000 0x19000>;
119 qcom,ee = <0>;
/linux/drivers/soc/tegra/cbb/
H A Dtegra234-cbb.c8 * Error types supported by CBB2.0 are:
27 #define FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0 0x0
28 #define FABRIC_EN_CFG_STATUS_0_0 0x40
29 #define FABRIC_EN_CFG_ADDR_INDEX_0_0 0x60
30 #define FABRIC_EN_CFG_ADDR_LOW_0 0x80
31 #define FABRIC_EN_CFG_ADDR_HI_0 0x84
33 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_INDEX_0_0 0x100
34 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_LOW_0 0x140
35 #define FABRIC_EN_CFG_TARGET_NODE_ADDR_HI_0 0x144
37 #define FABRIC_MN_INITIATOR_ERR_EN_0 0x200
[all …]
/linux/drivers/net/wireless/rsi/
H A Drsi_hal.h45 #define FLASH_SIZE_ADDR 0x04000016
46 #define PING_BUFFER_ADDRESS 0x19000
47 #define PONG_BUFFER_ADDRESS 0x1a000
48 #define SWBL_REGIN 0x41050034
49 #define SWBL_REGOUT 0x4105003c
50 #define PING_WRITE 0x1
51 #define PONG_WRITE 0x2
56 #define REGIN_VALID 0xA
57 #define REGIN_INPUT 0xA0
58 #define REGOUT_VALID 0xAB
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux/arch/x86/platform/ce4100/
H A Dfalconfalls.dts16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
36 reg = <0xfec00000 0x1000>;
41 reg = <0xfed00000 0x200>;
46 reg = <0xfee00000 0x1000>;
54 bus-range = <0 0>;
55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega10_smumgr.c46 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega10_copy_table_from_smc()
48 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega10_copy_table_from_smc()
68 return 0; in vega10_copy_table_from_smc()
81 return 0; in vega10_copy_table_to_smc()
85 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega10_copy_table_to_smc()
87 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega10_copy_table_to_smc()
108 return 0; in vega10_copy_table_to_smc()
123 return 0; in vega10_enable_smc_features()
146 return 0; in vega10_get_enabled_smc_features()
151 uint64_t features_enabled = 0; in vega10_is_dpm_running()
[all …]
H A Dvega20_smumgr.c39 #define MP0_Public 0x03800000
40 #define MP0_SRAM 0x03900000
41 #define MP1_Public 0x03b00000
42 #define MP1_SRAM 0x03c00004
45 #define smnMP1_FIRMWARE_FLAGS 0x3010024
46 #define smnMP0_FW_INTF 0x30101c0
47 #define smnMP1_PUB_CTRL 0x3010b14
55 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in vega20_is_smc_ram_running()
75 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
78 0, MP1_C2PMSG_90__CONTENT_MASK); in vega20_wait_for_response()
[all …]
/linux/include/uapi/misc/
H A Dxilinx_sdfec.h17 #define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
18 #define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x10400)
19 #define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
20 #define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x19000)
21 #define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
22 #define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x28000)
42 XSDFEC_TURBO_CODE = 0,
55 XSDFEC_MAINTAIN_ORDER = 0,
70 XSDFEC_MAX_SCALE = 0,
86 XSDFEC_INIT = 0,
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dinit.c28 [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf), in mt7603_set_tmac_template()
36 for (i = 0; i < ARRAY_SIZE(desc); i++) in mt7603_set_tmac_template()
50 int reserved_count = 0; in mt7603_dma_sched_init()
65 mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553); in mt7603_dma_sched_init()
66 mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555); in mt7603_dma_sched_init()
68 mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e); in mt7603_dma_sched_init()
69 mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c); in mt7603_dma_sched_init()
71 mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff); in mt7603_dma_sched_init()
76 for (i = 0; i <= 4; i++) in mt7603_dma_sched_init()
90 reserved_count = 0; in mt7603_dma_sched_init()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Ddra7.dtsi60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
78 #size-cells = <0>;
80 cpu0: cpu@0 {
83 reg = <0>;
108 opp-supported-hw = <0xFF 0x01>;
118 opp-supported-hw = <0xFF 0x02>;
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.h12 #define RVU_AF_MSIXTR_BASE (0x10)
13 #define RVU_AF_ECO (0x20)
14 #define RVU_AF_BLK_RST (0x30)
15 #define RVU_AF_PF_BAR4_ADDR (0x40)
16 #define RVU_AF_RAS (0x100)
17 #define RVU_AF_RAS_W1S (0x108)
18 #define RVU_AF_RAS_ENA_W1S (0x110)
19 #define RVU_AF_RAS_ENA_W1C (0x118)
20 #define RVU_AF_GEN_INT (0x120)
21 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-sdx65.c36 .offset = 0x0,
39 .enable_reg = 0x6d000,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
73 { P_BI_TCXO, 0 },
91 { P_BI_TCXO, 0 },
105 { P_BI_TCXO, 0 },
119 { P_PCIE_PIPE_CLK, 0 },
129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
[all …]
/linux/drivers/net/ethernet/wangxun/libwx/
H A Dwx_type.h16 #define WX_NCSI_SUP 0x8000
17 #define WX_NCSI_MASK 0x8000
18 #define WX_WOL_SUP 0x4000
19 #define WX_WOL_MASK 0x4000
22 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
23 #define WX_PCI_LINK_STATUS 0xB2
29 #define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v))
32 #define WX_MIS_PWR 0x10000
33 #define WX_MIS_RST 0x1000C
35 #define WX_MIS_RST_SW_RST BIT(0)
[all …]

12