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/linux/sound/pci/au88x0/
H A Dau88x0_a3d.h18 #define HRTF_SZ 0x38
19 #define DLINE_SZ 0x28
48 #define A3D_A_HrtfCurrent 0x18000 /* 56 ULONG */
49 #define A3D_A_GainCurrent 0x180E0
50 #define A3D_A_GainTarget 0x180E4
51 #define A3D_A_A12Current 0x180E8 /* Atmospheric current. */
52 #define A3D_A_A21Target 0x180EC /* Atmospheric target */
53 #define A3D_A_B01Current 0x180F0 /* Atmospheric current */
54 #define A3D_A_B10Target 0x180F4 /* Atmospheric target */
55 #define A3D_A_B2Current 0x180F8 /* Atmospheric current */
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-sata2-1.dtsi2 * PQ3 SATAv2 device tree stub [ controller @ offset 0x19000 ]
37 reg = <0x19000 0x1000>;
39 interrupts = <41 0x2 0 0>;
H A Dmpc8536si-post.dtsi39 interrupts = <19 2 0 0>;
42 /* controller at 0x8000 */
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
53 /* controller at 0x9000 */
59 bus-range = <0 255>;
61 interrupts = <25 2 0 0>;
63 pcie@0 {
64 reg = <0 0 0 0 0>;
69 interrupts = <25 2 0 0>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
/linux/arch/mips/include/asm/sn/sn0/
H A Dkldir.h28 * 0x2000000 (32M) +-----------------------------------------+
30 * 0x1F80000 (31.5M) +-----------------------------------------+
32 * 0x1C00000 (30M) +-----------------------------------------+
34 * 0x0800000 (28M) +-----------------------------------------+
36 * 0x1B00000 (27M) +-----------------------------------------+
38 * 0x1A00000 (26M) +-----------------------------------------+
40 * 0x1800000 (24M) +-----------------------------------------+
42 * 0x1600000 (22M) +-----------------------------------------+
48 * 0x190000 (2M--) +-----------------------------------------+
51 * 0x34000 (208K) +-----------------------------------------+
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dfsl,pq-sata.yaml38 1 for controller @ 0x18000
39 2 for controller @ 0x19000
40 3 for controller @ 0x1a000
41 4 for controller @ 0x1b000
55 reg = <0x18000 0x1000>;
/linux/Documentation/devicetree/bindings/dma/
H A Dqcom,bam-dma.yaml66 minimum: 0
69 Indicates the active Execution Environment identifier (0-7) used in the
116 reg = <0xf9944000 0x19000>;
121 qcom,ee = <0>;
132 reg = <0x0 0x01dc4000 0x0 0x22000>;
135 iommus = <&apps_smmu 0xc0 0>, <&apps_smmu 0xc1 0>;
136 qcom,ee = <0>;
/linux/drivers/net/wireless/rsi/
H A Drsi_hal.h45 #define FLASH_SIZE_ADDR 0x04000016
46 #define PING_BUFFER_ADDRESS 0x19000
47 #define PONG_BUFFER_ADDRESS 0x1a000
48 #define SWBL_REGIN 0x41050034
49 #define SWBL_REGOUT 0x4105003c
50 #define PING_WRITE 0x1
51 #define PONG_WRITE 0x2
56 #define REGIN_VALID 0xA
57 #define REGIN_INPUT 0xA0
58 #define REGOUT_VALID 0xAB
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dgaudi_blocks.h16 #define mmNIC0_PHY0_BASE 0x0ull
17 #define NIC0_PHY0_MAX_OFFSET 0x9F13
18 #define mmMME0_ACC_BASE 0x7FFC020000ull
19 #define MME0_ACC_MAX_OFFSET 0x5C00
20 #define MME0_ACC_SECTION 0x20000
21 #define mmMME0_SBAB_BASE 0x7FFC040000ull
22 #define MME0_SBAB_MAX_OFFSET 0x5800
23 #define MME0_SBAB_SECTION 0x1000
24 #define mmMME0_PRTN_BASE 0x7FFC041000ull
25 #define MME0_PRTN_MAX_OFFSET 0x5000
[all …]
/linux/arch/x86/platform/ce4100/
H A Dfalconfalls.dts16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
36 reg = <0xfec00000 0x1000>;
41 reg = <0xfed00000 0x200>;
46 reg = <0xfee00000 0x1000>;
54 bus-range = <0 0>;
55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega10_smumgr.c46 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega10_copy_table_from_smc()
48 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega10_copy_table_from_smc()
68 return 0; in vega10_copy_table_from_smc()
81 return 0; in vega10_copy_table_to_smc()
85 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega10_copy_table_to_smc()
87 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega10_copy_table_to_smc()
108 return 0; in vega10_copy_table_to_smc()
123 return 0; in vega10_enable_smc_features()
146 return 0; in vega10_get_enabled_smc_features()
151 uint64_t features_enabled = 0; in vega10_is_dpm_running()
[all …]
H A Dvega12_smumgr.c49 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega12_copy_table_from_smc()
51 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega12_copy_table_from_smc()
56 NULL) == 0, in vega12_copy_table_from_smc()
61 NULL) == 0, in vega12_copy_table_from_smc()
67 NULL) == 0, in vega12_copy_table_from_smc()
76 return 0; in vega12_copy_table_from_smc()
93 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0, in vega12_copy_table_to_smc()
95 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0, in vega12_copy_table_to_smc()
106 NULL) == 0, in vega12_copy_table_to_smc()
112 NULL) == 0, in vega12_copy_table_to_smc()
[all …]
H A Dvega20_smumgr.c39 #define MP0_Public 0x03800000
40 #define MP0_SRAM 0x03900000
41 #define MP1_Public 0x03b00000
42 #define MP1_SRAM 0x03c00004
45 #define smnMP1_FIRMWARE_FLAGS 0x3010024
46 #define smnMP0_FW_INTF 0x30101c0
47 #define smnMP1_PUB_CTRL 0x3010b14
55 (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in vega20_is_smc_ram_running()
75 reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90); in vega20_wait_for_response()
78 0, MP1_C2PMSG_90__CONTENT_MASK); in vega20_wait_for_response()
[all …]
/linux/include/uapi/misc/
H A Dxilinx_sdfec.h17 #define XSDFEC_LDPC_SC_TABLE_ADDR_BASE (0x10000)
18 #define XSDFEC_LDPC_SC_TABLE_ADDR_HIGH (0x10400)
19 #define XSDFEC_LDPC_LA_TABLE_ADDR_BASE (0x18000)
20 #define XSDFEC_LDPC_LA_TABLE_ADDR_HIGH (0x19000)
21 #define XSDFEC_LDPC_QC_TABLE_ADDR_BASE (0x20000)
22 #define XSDFEC_LDPC_QC_TABLE_ADDR_HIGH (0x28000)
42 XSDFEC_TURBO_CODE = 0,
55 XSDFEC_MAINTAIN_ORDER = 0,
70 XSDFEC_MAX_SCALE = 0,
86 XSDFEC_INIT = 0,
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_9_1_sar2130p.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_8_4_sa8775p.h11 .max_mixer_blendstages = 0xb,
22 .base = 0x0, .len = 0x494,
24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
25 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_8_0_sc8280xp.h23 .base = 0x0, .len = 0x494,
25 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
26 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
33 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
[all …]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x290,
35 .base = 0x16000, .len = 0x290,
39 .base = 0x17000, .len = 0x290,
43 .base = 0x18000, .len = 0x290,
47 .base = 0x19000, .len = 0x290,
51 .base = 0x1a000, .len = 0x290,
59 .base = 0x4000, .len = 0x344,
[all …]
/linux/drivers/clk/qcom/
H A Dsegcc-nord.c39 .offset = 0x0,
42 .enable_reg = 0x0,
43 .enable_mask = BIT(0),
56 { 0x1, 2 },
61 .offset = 0x0,
78 .offset = 0x2000,
81 .enable_reg = 0x0,
95 .offset = 0x4000,
98 .enable_reg = 0x0,
112 .offset = 0x5000,
[all …]
H A Dnwgcc-nord.c36 .offset = 0x0,
39 .enable_reg = 0x0,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
75 { P_BI_TCXO, 0 },
89 F(60000000, P_NW_GCC_GPLL0_OUT_MAIN, 10, 0, 0),
90 F(100000000, P_NW_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
91 F(200000000, P_NW_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
96 .cmd_rcgr = 0x20004,
[all …]
H A Dgcc-sdx65.c36 .offset = 0x0,
39 .enable_reg = 0x6d000,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
73 { P_BI_TCXO, 0 },
91 { P_BI_TCXO, 0 },
105 { P_BI_TCXO, 0 },
119 { P_PCIE_PIPE_CLK, 0 },
129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
/linux/drivers/interconnect/qcom/
H A Dmilos.c142 .port_offsets = { 0xc000 },
144 .urg_fwd = 0,
159 .port_offsets = { 0xf200 },
161 .urg_fwd = 0,
176 .port_offsets = { 0x10000 },
178 .urg_fwd = 0,
193 .port_offsets = { 0x14000 },
195 .urg_fwd = 0,
210 .port_offsets = { 0x12000 },
212 .urg_fwd = 0,
[all …]

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