1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef GAUDI_BLOCKS_H_ 14*e65e175bSOded Gabbay #define GAUDI_BLOCKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay #define mmNIC0_PHY0_BASE 0x0ull 17*e65e175bSOded Gabbay #define NIC0_PHY0_MAX_OFFSET 0x9F13 18*e65e175bSOded Gabbay #define mmMME0_ACC_BASE 0x7FFC020000ull 19*e65e175bSOded Gabbay #define MME0_ACC_MAX_OFFSET 0x5C00 20*e65e175bSOded Gabbay #define MME0_ACC_SECTION 0x20000 21*e65e175bSOded Gabbay #define mmMME0_SBAB_BASE 0x7FFC040000ull 22*e65e175bSOded Gabbay #define MME0_SBAB_MAX_OFFSET 0x5800 23*e65e175bSOded Gabbay #define MME0_SBAB_SECTION 0x1000 24*e65e175bSOded Gabbay #define mmMME0_PRTN_BASE 0x7FFC041000ull 25*e65e175bSOded Gabbay #define MME0_PRTN_MAX_OFFSET 0x5000 26*e65e175bSOded Gabbay #define MME0_PRTN_SECTION 0x1F000 27*e65e175bSOded Gabbay #define mmMME0_CTRL_BASE 0x7FFC060000ull 28*e65e175bSOded Gabbay #define MME0_CTRL_MAX_OFFSET 0xDA80 29*e65e175bSOded Gabbay #define MME0_CTRL_SECTION 0x8000 30*e65e175bSOded Gabbay #define mmARCH_MME0_CTRL_BASE 0x7FFC060008ull 31*e65e175bSOded Gabbay #define ARCH_MME0_CTRL_MAX_OFFSET 0x3400 32*e65e175bSOded Gabbay #define ARCH_MME0_CTRL_SECTION 0x3400 33*e65e175bSOded Gabbay #define mmARCH_TENSOR_S_MME0_CTRL_BASE 0x7FFC06003Cull 34*e65e175bSOded Gabbay #define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 35*e65e175bSOded Gabbay #define ARCH_TENSOR_S_MME0_CTRL_SECTION 0x4C00 36*e65e175bSOded Gabbay #define mmARCH_AGU_S_MME0_CTRL_BASE 0x7FFC060088ull 37*e65e175bSOded Gabbay #define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 38*e65e175bSOded Gabbay #define ARCH_AGU_S_MME0_CTRL_SECTION 0x2400 39*e65e175bSOded Gabbay #define mmARCH_TENSOR_L_MME0_CTRL_BASE 0x7FFC0600ACull 40*e65e175bSOded Gabbay #define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 41*e65e175bSOded Gabbay #define ARCH_TENSOR_L_MME0_CTRL_SECTION 0x4C00 42*e65e175bSOded Gabbay #define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0600F8ull 43*e65e175bSOded Gabbay #define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 44*e65e175bSOded Gabbay #define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 45*e65e175bSOded Gabbay #define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06011Cull 46*e65e175bSOded Gabbay #define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 47*e65e175bSOded Gabbay #define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 48*e65e175bSOded Gabbay #define mmARCH_TENSOR_O_MME0_CTRL_BASE 0x7FFC060140ull 49*e65e175bSOded Gabbay #define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 50*e65e175bSOded Gabbay #define ARCH_TENSOR_O_MME0_CTRL_SECTION 0x4C00 51*e65e175bSOded Gabbay #define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06018Cull 52*e65e175bSOded Gabbay #define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 53*e65e175bSOded Gabbay #define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 54*e65e175bSOded Gabbay #define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0601B0ull 55*e65e175bSOded Gabbay #define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 56*e65e175bSOded Gabbay #define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 57*e65e175bSOded Gabbay #define mmARCH_DESC_MME0_CTRL_BASE 0x7FFC0601D4ull 58*e65e175bSOded Gabbay #define ARCH_DESC_MME0_CTRL_MAX_OFFSET 0x5400 59*e65e175bSOded Gabbay #define ARCH_DESC_MME0_CTRL_SECTION 0x2340 60*e65e175bSOded Gabbay #define mmSHADOW_0_MME0_CTRL_BASE 0x7FFC060408ull 61*e65e175bSOded Gabbay #define SHADOW_0_MME0_CTRL_MAX_OFFSET 0x3400 62*e65e175bSOded Gabbay #define SHADOW_0_MME0_CTRL_SECTION 0x3400 63*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE 0x7FFC06043Cull 64*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 65*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION 0x4C00 66*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_S_MME0_CTRL_BASE 0x7FFC060488ull 67*e65e175bSOded Gabbay #define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 68*e65e175bSOded Gabbay #define SHADOW_0_AGU_S_MME0_CTRL_SECTION 0x2400 69*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE 0x7FFC0604ACull 70*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 71*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION 0x4C00 72*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0604F8ull 73*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 74*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 75*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06051Cull 76*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 77*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 78*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE 0x7FFC060540ull 79*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 80*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION 0x4C00 81*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06058Cull 82*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 83*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 84*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0605B0ull 85*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 86*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 87*e65e175bSOded Gabbay #define mmSHADOW_0_DESC_MME0_CTRL_BASE 0x7FFC0605D4ull 88*e65e175bSOded Gabbay #define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET 0x5400 89*e65e175bSOded Gabbay #define SHADOW_0_DESC_MME0_CTRL_SECTION 0xB400 90*e65e175bSOded Gabbay #define mmSHADOW_1_MME0_CTRL_BASE 0x7FFC060688ull 91*e65e175bSOded Gabbay #define SHADOW_1_MME0_CTRL_MAX_OFFSET 0x3400 92*e65e175bSOded Gabbay #define SHADOW_1_MME0_CTRL_SECTION 0x3400 93*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE 0x7FFC0606BCull 94*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 95*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION 0x4C00 96*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_S_MME0_CTRL_BASE 0x7FFC060708ull 97*e65e175bSOded Gabbay #define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 98*e65e175bSOded Gabbay #define SHADOW_1_AGU_S_MME0_CTRL_SECTION 0x2400 99*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE 0x7FFC06072Cull 100*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 101*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION 0x4C00 102*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060778ull 103*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 104*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 105*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06079Cull 106*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 107*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 108*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE 0x7FFC0607C0ull 109*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 110*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION 0x4C00 111*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06080Cull 112*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 113*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 114*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060830ull 115*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 116*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 117*e65e175bSOded Gabbay #define mmSHADOW_1_DESC_MME0_CTRL_BASE 0x7FFC060854ull 118*e65e175bSOded Gabbay #define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET 0x5400 119*e65e175bSOded Gabbay #define SHADOW_1_DESC_MME0_CTRL_SECTION 0xB400 120*e65e175bSOded Gabbay #define mmSHADOW_2_MME0_CTRL_BASE 0x7FFC060908ull 121*e65e175bSOded Gabbay #define SHADOW_2_MME0_CTRL_MAX_OFFSET 0x3400 122*e65e175bSOded Gabbay #define SHADOW_2_MME0_CTRL_SECTION 0x3400 123*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE 0x7FFC06093Cull 124*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 125*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION 0x4C00 126*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_S_MME0_CTRL_BASE 0x7FFC060988ull 127*e65e175bSOded Gabbay #define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 128*e65e175bSOded Gabbay #define SHADOW_2_AGU_S_MME0_CTRL_SECTION 0x2400 129*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE 0x7FFC0609ACull 130*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 131*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION 0x4C00 132*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0609F8ull 133*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 134*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 135*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060A1Cull 136*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 137*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 138*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE 0x7FFC060A40ull 139*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 140*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION 0x4C00 141*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060A8Cull 142*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 143*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 144*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060AB0ull 145*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 146*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 147*e65e175bSOded Gabbay #define mmSHADOW_2_DESC_MME0_CTRL_BASE 0x7FFC060AD4ull 148*e65e175bSOded Gabbay #define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET 0x5400 149*e65e175bSOded Gabbay #define SHADOW_2_DESC_MME0_CTRL_SECTION 0xB400 150*e65e175bSOded Gabbay #define mmSHADOW_3_MME0_CTRL_BASE 0x7FFC060B88ull 151*e65e175bSOded Gabbay #define SHADOW_3_MME0_CTRL_MAX_OFFSET 0x3400 152*e65e175bSOded Gabbay #define SHADOW_3_MME0_CTRL_SECTION 0x3400 153*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE 0x7FFC060BBCull 154*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00 155*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION 0x4C00 156*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_S_MME0_CTRL_BASE 0x7FFC060C08ull 157*e65e175bSOded Gabbay #define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400 158*e65e175bSOded Gabbay #define SHADOW_3_AGU_S_MME0_CTRL_SECTION 0x2400 159*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE 0x7FFC060C2Cull 160*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00 161*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION 0x4C00 162*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060C78ull 163*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 164*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400 165*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060C9Cull 166*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 167*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400 168*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE 0x7FFC060CC0ull 169*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00 170*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION 0x4C00 171*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060D0Cull 172*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400 173*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400 174*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060D30ull 175*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400 176*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400 177*e65e175bSOded Gabbay #define mmSHADOW_3_DESC_MME0_CTRL_BASE 0x7FFC060D54ull 178*e65e175bSOded Gabbay #define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET 0x5400 179*e65e175bSOded Gabbay #define SHADOW_3_DESC_MME0_CTRL_SECTION 0x72AC 180*e65e175bSOded Gabbay #define mmMME0_QM_BASE 0x7FFC068000ull 181*e65e175bSOded Gabbay #define MME0_QM_MAX_OFFSET 0xD040 182*e65e175bSOded Gabbay #define MME0_QM_SECTION 0x38000 183*e65e175bSOded Gabbay #define mmMME1_ACC_BASE 0x7FFC0A0000ull 184*e65e175bSOded Gabbay #define MME1_ACC_MAX_OFFSET 0x5C00 185*e65e175bSOded Gabbay #define MME1_ACC_SECTION 0x20000 186*e65e175bSOded Gabbay #define mmMME1_SBAB_BASE 0x7FFC0C0000ull 187*e65e175bSOded Gabbay #define MME1_SBAB_MAX_OFFSET 0x5800 188*e65e175bSOded Gabbay #define MME1_SBAB_SECTION 0x1000 189*e65e175bSOded Gabbay #define mmMME1_PRTN_BASE 0x7FFC0C1000ull 190*e65e175bSOded Gabbay #define MME1_PRTN_MAX_OFFSET 0x5000 191*e65e175bSOded Gabbay #define MME1_PRTN_SECTION 0x1F000 192*e65e175bSOded Gabbay #define mmMME1_CTRL_BASE 0x7FFC0E0000ull 193*e65e175bSOded Gabbay #define MME1_CTRL_MAX_OFFSET 0xDA80 194*e65e175bSOded Gabbay #define MME1_CTRL_SECTION 0x8000 195*e65e175bSOded Gabbay #define mmARCH_MME1_CTRL_BASE 0x7FFC0E0008ull 196*e65e175bSOded Gabbay #define ARCH_MME1_CTRL_MAX_OFFSET 0x3400 197*e65e175bSOded Gabbay #define ARCH_MME1_CTRL_SECTION 0x3400 198*e65e175bSOded Gabbay #define mmARCH_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E003Cull 199*e65e175bSOded Gabbay #define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 200*e65e175bSOded Gabbay #define ARCH_TENSOR_S_MME1_CTRL_SECTION 0x4C00 201*e65e175bSOded Gabbay #define mmARCH_AGU_S_MME1_CTRL_BASE 0x7FFC0E0088ull 202*e65e175bSOded Gabbay #define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 203*e65e175bSOded Gabbay #define ARCH_AGU_S_MME1_CTRL_SECTION 0x2400 204*e65e175bSOded Gabbay #define mmARCH_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E00ACull 205*e65e175bSOded Gabbay #define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 206*e65e175bSOded Gabbay #define ARCH_TENSOR_L_MME1_CTRL_SECTION 0x4C00 207*e65e175bSOded Gabbay #define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E00F8ull 208*e65e175bSOded Gabbay #define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 209*e65e175bSOded Gabbay #define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 210*e65e175bSOded Gabbay #define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E011Cull 211*e65e175bSOded Gabbay #define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 212*e65e175bSOded Gabbay #define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 213*e65e175bSOded Gabbay #define mmARCH_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0140ull 214*e65e175bSOded Gabbay #define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 215*e65e175bSOded Gabbay #define ARCH_TENSOR_O_MME1_CTRL_SECTION 0x4C00 216*e65e175bSOded Gabbay #define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E018Cull 217*e65e175bSOded Gabbay #define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 218*e65e175bSOded Gabbay #define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 219*e65e175bSOded Gabbay #define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E01B0ull 220*e65e175bSOded Gabbay #define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 221*e65e175bSOded Gabbay #define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 222*e65e175bSOded Gabbay #define mmARCH_DESC_MME1_CTRL_BASE 0x7FFC0E01D4ull 223*e65e175bSOded Gabbay #define ARCH_DESC_MME1_CTRL_MAX_OFFSET 0x5400 224*e65e175bSOded Gabbay #define ARCH_DESC_MME1_CTRL_SECTION 0x2340 225*e65e175bSOded Gabbay #define mmSHADOW_0_MME1_CTRL_BASE 0x7FFC0E0408ull 226*e65e175bSOded Gabbay #define SHADOW_0_MME1_CTRL_MAX_OFFSET 0x3400 227*e65e175bSOded Gabbay #define SHADOW_0_MME1_CTRL_SECTION 0x3400 228*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E043Cull 229*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 230*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION 0x4C00 231*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_S_MME1_CTRL_BASE 0x7FFC0E0488ull 232*e65e175bSOded Gabbay #define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 233*e65e175bSOded Gabbay #define SHADOW_0_AGU_S_MME1_CTRL_SECTION 0x2400 234*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E04ACull 235*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 236*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION 0x4C00 237*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E04F8ull 238*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 239*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 240*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E051Cull 241*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 242*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 243*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0540ull 244*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 245*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION 0x4C00 246*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E058Cull 247*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 248*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 249*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E05B0ull 250*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 251*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 252*e65e175bSOded Gabbay #define mmSHADOW_0_DESC_MME1_CTRL_BASE 0x7FFC0E05D4ull 253*e65e175bSOded Gabbay #define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET 0x5400 254*e65e175bSOded Gabbay #define SHADOW_0_DESC_MME1_CTRL_SECTION 0xB400 255*e65e175bSOded Gabbay #define mmSHADOW_1_MME1_CTRL_BASE 0x7FFC0E0688ull 256*e65e175bSOded Gabbay #define SHADOW_1_MME1_CTRL_MAX_OFFSET 0x3400 257*e65e175bSOded Gabbay #define SHADOW_1_MME1_CTRL_SECTION 0x3400 258*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E06BCull 259*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 260*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION 0x4C00 261*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_S_MME1_CTRL_BASE 0x7FFC0E0708ull 262*e65e175bSOded Gabbay #define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 263*e65e175bSOded Gabbay #define SHADOW_1_AGU_S_MME1_CTRL_SECTION 0x2400 264*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E072Cull 265*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 266*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION 0x4C00 267*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0778ull 268*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 269*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 270*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E079Cull 271*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 272*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 273*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E07C0ull 274*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 275*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION 0x4C00 276*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E080Cull 277*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 278*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 279*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0830ull 280*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 281*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 282*e65e175bSOded Gabbay #define mmSHADOW_1_DESC_MME1_CTRL_BASE 0x7FFC0E0854ull 283*e65e175bSOded Gabbay #define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET 0x5400 284*e65e175bSOded Gabbay #define SHADOW_1_DESC_MME1_CTRL_SECTION 0xB400 285*e65e175bSOded Gabbay #define mmSHADOW_2_MME1_CTRL_BASE 0x7FFC0E0908ull 286*e65e175bSOded Gabbay #define SHADOW_2_MME1_CTRL_MAX_OFFSET 0x3400 287*e65e175bSOded Gabbay #define SHADOW_2_MME1_CTRL_SECTION 0x3400 288*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E093Cull 289*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 290*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION 0x4C00 291*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_S_MME1_CTRL_BASE 0x7FFC0E0988ull 292*e65e175bSOded Gabbay #define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 293*e65e175bSOded Gabbay #define SHADOW_2_AGU_S_MME1_CTRL_SECTION 0x2400 294*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E09ACull 295*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 296*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION 0x4C00 297*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E09F8ull 298*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 299*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 300*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0A1Cull 301*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 302*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 303*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0A40ull 304*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 305*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION 0x4C00 306*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0A8Cull 307*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 308*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 309*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0AB0ull 310*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 311*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 312*e65e175bSOded Gabbay #define mmSHADOW_2_DESC_MME1_CTRL_BASE 0x7FFC0E0AD4ull 313*e65e175bSOded Gabbay #define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET 0x5400 314*e65e175bSOded Gabbay #define SHADOW_2_DESC_MME1_CTRL_SECTION 0xB400 315*e65e175bSOded Gabbay #define mmSHADOW_3_MME1_CTRL_BASE 0x7FFC0E0B88ull 316*e65e175bSOded Gabbay #define SHADOW_3_MME1_CTRL_MAX_OFFSET 0x3400 317*e65e175bSOded Gabbay #define SHADOW_3_MME1_CTRL_SECTION 0x3400 318*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E0BBCull 319*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00 320*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION 0x4C00 321*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_S_MME1_CTRL_BASE 0x7FFC0E0C08ull 322*e65e175bSOded Gabbay #define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400 323*e65e175bSOded Gabbay #define SHADOW_3_AGU_S_MME1_CTRL_SECTION 0x2400 324*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E0C2Cull 325*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00 326*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION 0x4C00 327*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0C78ull 328*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 329*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400 330*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0C9Cull 331*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 332*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400 333*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0CC0ull 334*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00 335*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION 0x4C00 336*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0D0Cull 337*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400 338*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400 339*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0D30ull 340*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400 341*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400 342*e65e175bSOded Gabbay #define mmSHADOW_3_DESC_MME1_CTRL_BASE 0x7FFC0E0D54ull 343*e65e175bSOded Gabbay #define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET 0x5400 344*e65e175bSOded Gabbay #define SHADOW_3_DESC_MME1_CTRL_SECTION 0x72AC 345*e65e175bSOded Gabbay #define mmMME1_QM_BASE 0x7FFC0E8000ull 346*e65e175bSOded Gabbay #define MME1_QM_MAX_OFFSET 0xD040 347*e65e175bSOded Gabbay #define MME1_QM_SECTION 0x38000 348*e65e175bSOded Gabbay #define mmMME2_ACC_BASE 0x7FFC120000ull 349*e65e175bSOded Gabbay #define MME2_ACC_MAX_OFFSET 0x5C00 350*e65e175bSOded Gabbay #define MME2_ACC_SECTION 0x20000 351*e65e175bSOded Gabbay #define mmMME2_SBAB_BASE 0x7FFC140000ull 352*e65e175bSOded Gabbay #define MME2_SBAB_MAX_OFFSET 0x5800 353*e65e175bSOded Gabbay #define MME2_SBAB_SECTION 0x1000 354*e65e175bSOded Gabbay #define mmMME2_PRTN_BASE 0x7FFC141000ull 355*e65e175bSOded Gabbay #define MME2_PRTN_MAX_OFFSET 0x5000 356*e65e175bSOded Gabbay #define MME2_PRTN_SECTION 0x1F000 357*e65e175bSOded Gabbay #define mmMME2_CTRL_BASE 0x7FFC160000ull 358*e65e175bSOded Gabbay #define MME2_CTRL_MAX_OFFSET 0xDA80 359*e65e175bSOded Gabbay #define MME2_CTRL_SECTION 0x8000 360*e65e175bSOded Gabbay #define mmARCH_MME2_CTRL_BASE 0x7FFC160008ull 361*e65e175bSOded Gabbay #define ARCH_MME2_CTRL_MAX_OFFSET 0x3400 362*e65e175bSOded Gabbay #define ARCH_MME2_CTRL_SECTION 0x3400 363*e65e175bSOded Gabbay #define mmARCH_TENSOR_S_MME2_CTRL_BASE 0x7FFC16003Cull 364*e65e175bSOded Gabbay #define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 365*e65e175bSOded Gabbay #define ARCH_TENSOR_S_MME2_CTRL_SECTION 0x4C00 366*e65e175bSOded Gabbay #define mmARCH_AGU_S_MME2_CTRL_BASE 0x7FFC160088ull 367*e65e175bSOded Gabbay #define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 368*e65e175bSOded Gabbay #define ARCH_AGU_S_MME2_CTRL_SECTION 0x2400 369*e65e175bSOded Gabbay #define mmARCH_TENSOR_L_MME2_CTRL_BASE 0x7FFC1600ACull 370*e65e175bSOded Gabbay #define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 371*e65e175bSOded Gabbay #define ARCH_TENSOR_L_MME2_CTRL_SECTION 0x4C00 372*e65e175bSOded Gabbay #define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1600F8ull 373*e65e175bSOded Gabbay #define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 374*e65e175bSOded Gabbay #define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 375*e65e175bSOded Gabbay #define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16011Cull 376*e65e175bSOded Gabbay #define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 377*e65e175bSOded Gabbay #define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 378*e65e175bSOded Gabbay #define mmARCH_TENSOR_O_MME2_CTRL_BASE 0x7FFC160140ull 379*e65e175bSOded Gabbay #define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 380*e65e175bSOded Gabbay #define ARCH_TENSOR_O_MME2_CTRL_SECTION 0x4C00 381*e65e175bSOded Gabbay #define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16018Cull 382*e65e175bSOded Gabbay #define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 383*e65e175bSOded Gabbay #define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 384*e65e175bSOded Gabbay #define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1601B0ull 385*e65e175bSOded Gabbay #define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 386*e65e175bSOded Gabbay #define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 387*e65e175bSOded Gabbay #define mmARCH_DESC_MME2_CTRL_BASE 0x7FFC1601D4ull 388*e65e175bSOded Gabbay #define ARCH_DESC_MME2_CTRL_MAX_OFFSET 0x5400 389*e65e175bSOded Gabbay #define ARCH_DESC_MME2_CTRL_SECTION 0x2340 390*e65e175bSOded Gabbay #define mmSHADOW_0_MME2_CTRL_BASE 0x7FFC160408ull 391*e65e175bSOded Gabbay #define SHADOW_0_MME2_CTRL_MAX_OFFSET 0x3400 392*e65e175bSOded Gabbay #define SHADOW_0_MME2_CTRL_SECTION 0x3400 393*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE 0x7FFC16043Cull 394*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 395*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION 0x4C00 396*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_S_MME2_CTRL_BASE 0x7FFC160488ull 397*e65e175bSOded Gabbay #define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 398*e65e175bSOded Gabbay #define SHADOW_0_AGU_S_MME2_CTRL_SECTION 0x2400 399*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE 0x7FFC1604ACull 400*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 401*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION 0x4C00 402*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1604F8ull 403*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 404*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 405*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16051Cull 406*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 407*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 408*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE 0x7FFC160540ull 409*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 410*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION 0x4C00 411*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16058Cull 412*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 413*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 414*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1605B0ull 415*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 416*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 417*e65e175bSOded Gabbay #define mmSHADOW_0_DESC_MME2_CTRL_BASE 0x7FFC1605D4ull 418*e65e175bSOded Gabbay #define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET 0x5400 419*e65e175bSOded Gabbay #define SHADOW_0_DESC_MME2_CTRL_SECTION 0xB400 420*e65e175bSOded Gabbay #define mmSHADOW_1_MME2_CTRL_BASE 0x7FFC160688ull 421*e65e175bSOded Gabbay #define SHADOW_1_MME2_CTRL_MAX_OFFSET 0x3400 422*e65e175bSOded Gabbay #define SHADOW_1_MME2_CTRL_SECTION 0x3400 423*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE 0x7FFC1606BCull 424*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 425*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION 0x4C00 426*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_S_MME2_CTRL_BASE 0x7FFC160708ull 427*e65e175bSOded Gabbay #define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 428*e65e175bSOded Gabbay #define SHADOW_1_AGU_S_MME2_CTRL_SECTION 0x2400 429*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE 0x7FFC16072Cull 430*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 431*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION 0x4C00 432*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160778ull 433*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 434*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 435*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16079Cull 436*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 437*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 438*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE 0x7FFC1607C0ull 439*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 440*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION 0x4C00 441*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16080Cull 442*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 443*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 444*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160830ull 445*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 446*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 447*e65e175bSOded Gabbay #define mmSHADOW_1_DESC_MME2_CTRL_BASE 0x7FFC160854ull 448*e65e175bSOded Gabbay #define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET 0x5400 449*e65e175bSOded Gabbay #define SHADOW_1_DESC_MME2_CTRL_SECTION 0xB400 450*e65e175bSOded Gabbay #define mmSHADOW_2_MME2_CTRL_BASE 0x7FFC160908ull 451*e65e175bSOded Gabbay #define SHADOW_2_MME2_CTRL_MAX_OFFSET 0x3400 452*e65e175bSOded Gabbay #define SHADOW_2_MME2_CTRL_SECTION 0x3400 453*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE 0x7FFC16093Cull 454*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 455*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION 0x4C00 456*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_S_MME2_CTRL_BASE 0x7FFC160988ull 457*e65e175bSOded Gabbay #define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 458*e65e175bSOded Gabbay #define SHADOW_2_AGU_S_MME2_CTRL_SECTION 0x2400 459*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE 0x7FFC1609ACull 460*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 461*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION 0x4C00 462*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1609F8ull 463*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 464*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 465*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160A1Cull 466*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 467*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 468*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE 0x7FFC160A40ull 469*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 470*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION 0x4C00 471*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160A8Cull 472*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 473*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 474*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160AB0ull 475*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 476*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 477*e65e175bSOded Gabbay #define mmSHADOW_2_DESC_MME2_CTRL_BASE 0x7FFC160AD4ull 478*e65e175bSOded Gabbay #define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET 0x5400 479*e65e175bSOded Gabbay #define SHADOW_2_DESC_MME2_CTRL_SECTION 0xB400 480*e65e175bSOded Gabbay #define mmSHADOW_3_MME2_CTRL_BASE 0x7FFC160B88ull 481*e65e175bSOded Gabbay #define SHADOW_3_MME2_CTRL_MAX_OFFSET 0x3400 482*e65e175bSOded Gabbay #define SHADOW_3_MME2_CTRL_SECTION 0x3400 483*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE 0x7FFC160BBCull 484*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00 485*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION 0x4C00 486*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_S_MME2_CTRL_BASE 0x7FFC160C08ull 487*e65e175bSOded Gabbay #define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400 488*e65e175bSOded Gabbay #define SHADOW_3_AGU_S_MME2_CTRL_SECTION 0x2400 489*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE 0x7FFC160C2Cull 490*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00 491*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION 0x4C00 492*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160C78ull 493*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 494*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400 495*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160C9Cull 496*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 497*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400 498*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE 0x7FFC160CC0ull 499*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00 500*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION 0x4C00 501*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160D0Cull 502*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400 503*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400 504*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160D30ull 505*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400 506*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400 507*e65e175bSOded Gabbay #define mmSHADOW_3_DESC_MME2_CTRL_BASE 0x7FFC160D54ull 508*e65e175bSOded Gabbay #define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET 0x5400 509*e65e175bSOded Gabbay #define SHADOW_3_DESC_MME2_CTRL_SECTION 0x72AC 510*e65e175bSOded Gabbay #define mmMME2_QM_BASE 0x7FFC168000ull 511*e65e175bSOded Gabbay #define MME2_QM_MAX_OFFSET 0xD040 512*e65e175bSOded Gabbay #define MME2_QM_SECTION 0x38000 513*e65e175bSOded Gabbay #define mmMME3_ACC_BASE 0x7FFC1A0000ull 514*e65e175bSOded Gabbay #define MME3_ACC_MAX_OFFSET 0x5C00 515*e65e175bSOded Gabbay #define MME3_ACC_SECTION 0x20000 516*e65e175bSOded Gabbay #define mmMME3_SBAB_BASE 0x7FFC1C0000ull 517*e65e175bSOded Gabbay #define MME3_SBAB_MAX_OFFSET 0x5800 518*e65e175bSOded Gabbay #define MME3_SBAB_SECTION 0x1000 519*e65e175bSOded Gabbay #define mmMME3_PRTN_BASE 0x7FFC1C1000ull 520*e65e175bSOded Gabbay #define MME3_PRTN_MAX_OFFSET 0x5000 521*e65e175bSOded Gabbay #define MME3_PRTN_SECTION 0x1F000 522*e65e175bSOded Gabbay #define mmMME3_CTRL_BASE 0x7FFC1E0000ull 523*e65e175bSOded Gabbay #define MME3_CTRL_MAX_OFFSET 0xDA80 524*e65e175bSOded Gabbay #define MME3_CTRL_SECTION 0x8000 525*e65e175bSOded Gabbay #define mmARCH_MME3_CTRL_BASE 0x7FFC1E0008ull 526*e65e175bSOded Gabbay #define ARCH_MME3_CTRL_MAX_OFFSET 0x3400 527*e65e175bSOded Gabbay #define ARCH_MME3_CTRL_SECTION 0x3400 528*e65e175bSOded Gabbay #define mmARCH_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E003Cull 529*e65e175bSOded Gabbay #define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 530*e65e175bSOded Gabbay #define ARCH_TENSOR_S_MME3_CTRL_SECTION 0x4C00 531*e65e175bSOded Gabbay #define mmARCH_AGU_S_MME3_CTRL_BASE 0x7FFC1E0088ull 532*e65e175bSOded Gabbay #define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 533*e65e175bSOded Gabbay #define ARCH_AGU_S_MME3_CTRL_SECTION 0x2400 534*e65e175bSOded Gabbay #define mmARCH_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E00ACull 535*e65e175bSOded Gabbay #define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 536*e65e175bSOded Gabbay #define ARCH_TENSOR_L_MME3_CTRL_SECTION 0x4C00 537*e65e175bSOded Gabbay #define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E00F8ull 538*e65e175bSOded Gabbay #define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 539*e65e175bSOded Gabbay #define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 540*e65e175bSOded Gabbay #define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E011Cull 541*e65e175bSOded Gabbay #define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 542*e65e175bSOded Gabbay #define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 543*e65e175bSOded Gabbay #define mmARCH_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0140ull 544*e65e175bSOded Gabbay #define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 545*e65e175bSOded Gabbay #define ARCH_TENSOR_O_MME3_CTRL_SECTION 0x4C00 546*e65e175bSOded Gabbay #define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E018Cull 547*e65e175bSOded Gabbay #define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 548*e65e175bSOded Gabbay #define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 549*e65e175bSOded Gabbay #define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E01B0ull 550*e65e175bSOded Gabbay #define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 551*e65e175bSOded Gabbay #define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 552*e65e175bSOded Gabbay #define mmARCH_DESC_MME3_CTRL_BASE 0x7FFC1E01D4ull 553*e65e175bSOded Gabbay #define ARCH_DESC_MME3_CTRL_MAX_OFFSET 0x5400 554*e65e175bSOded Gabbay #define ARCH_DESC_MME3_CTRL_SECTION 0x2340 555*e65e175bSOded Gabbay #define mmSHADOW_0_MME3_CTRL_BASE 0x7FFC1E0408ull 556*e65e175bSOded Gabbay #define SHADOW_0_MME3_CTRL_MAX_OFFSET 0x3400 557*e65e175bSOded Gabbay #define SHADOW_0_MME3_CTRL_SECTION 0x3400 558*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E043Cull 559*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 560*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION 0x4C00 561*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_S_MME3_CTRL_BASE 0x7FFC1E0488ull 562*e65e175bSOded Gabbay #define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 563*e65e175bSOded Gabbay #define SHADOW_0_AGU_S_MME3_CTRL_SECTION 0x2400 564*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E04ACull 565*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 566*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION 0x4C00 567*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E04F8ull 568*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 569*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 570*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E051Cull 571*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 572*e65e175bSOded Gabbay #define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 573*e65e175bSOded Gabbay #define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0540ull 574*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 575*e65e175bSOded Gabbay #define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION 0x4C00 576*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E058Cull 577*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 578*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 579*e65e175bSOded Gabbay #define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E05B0ull 580*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 581*e65e175bSOded Gabbay #define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 582*e65e175bSOded Gabbay #define mmSHADOW_0_DESC_MME3_CTRL_BASE 0x7FFC1E05D4ull 583*e65e175bSOded Gabbay #define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET 0x5400 584*e65e175bSOded Gabbay #define SHADOW_0_DESC_MME3_CTRL_SECTION 0xB400 585*e65e175bSOded Gabbay #define mmSHADOW_1_MME3_CTRL_BASE 0x7FFC1E0688ull 586*e65e175bSOded Gabbay #define SHADOW_1_MME3_CTRL_MAX_OFFSET 0x3400 587*e65e175bSOded Gabbay #define SHADOW_1_MME3_CTRL_SECTION 0x3400 588*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E06BCull 589*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 590*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION 0x4C00 591*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_S_MME3_CTRL_BASE 0x7FFC1E0708ull 592*e65e175bSOded Gabbay #define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 593*e65e175bSOded Gabbay #define SHADOW_1_AGU_S_MME3_CTRL_SECTION 0x2400 594*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E072Cull 595*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 596*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION 0x4C00 597*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0778ull 598*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 599*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 600*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E079Cull 601*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 602*e65e175bSOded Gabbay #define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 603*e65e175bSOded Gabbay #define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E07C0ull 604*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 605*e65e175bSOded Gabbay #define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION 0x4C00 606*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E080Cull 607*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 608*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 609*e65e175bSOded Gabbay #define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0830ull 610*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 611*e65e175bSOded Gabbay #define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 612*e65e175bSOded Gabbay #define mmSHADOW_1_DESC_MME3_CTRL_BASE 0x7FFC1E0854ull 613*e65e175bSOded Gabbay #define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET 0x5400 614*e65e175bSOded Gabbay #define SHADOW_1_DESC_MME3_CTRL_SECTION 0xB400 615*e65e175bSOded Gabbay #define mmSHADOW_2_MME3_CTRL_BASE 0x7FFC1E0908ull 616*e65e175bSOded Gabbay #define SHADOW_2_MME3_CTRL_MAX_OFFSET 0x3400 617*e65e175bSOded Gabbay #define SHADOW_2_MME3_CTRL_SECTION 0x3400 618*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E093Cull 619*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 620*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION 0x4C00 621*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_S_MME3_CTRL_BASE 0x7FFC1E0988ull 622*e65e175bSOded Gabbay #define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 623*e65e175bSOded Gabbay #define SHADOW_2_AGU_S_MME3_CTRL_SECTION 0x2400 624*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E09ACull 625*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 626*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION 0x4C00 627*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E09F8ull 628*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 629*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 630*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0A1Cull 631*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 632*e65e175bSOded Gabbay #define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 633*e65e175bSOded Gabbay #define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0A40ull 634*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 635*e65e175bSOded Gabbay #define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION 0x4C00 636*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0A8Cull 637*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 638*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 639*e65e175bSOded Gabbay #define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0AB0ull 640*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 641*e65e175bSOded Gabbay #define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 642*e65e175bSOded Gabbay #define mmSHADOW_2_DESC_MME3_CTRL_BASE 0x7FFC1E0AD4ull 643*e65e175bSOded Gabbay #define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET 0x5400 644*e65e175bSOded Gabbay #define SHADOW_2_DESC_MME3_CTRL_SECTION 0xB400 645*e65e175bSOded Gabbay #define mmSHADOW_3_MME3_CTRL_BASE 0x7FFC1E0B88ull 646*e65e175bSOded Gabbay #define SHADOW_3_MME3_CTRL_MAX_OFFSET 0x3400 647*e65e175bSOded Gabbay #define SHADOW_3_MME3_CTRL_SECTION 0x3400 648*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E0BBCull 649*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00 650*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION 0x4C00 651*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_S_MME3_CTRL_BASE 0x7FFC1E0C08ull 652*e65e175bSOded Gabbay #define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400 653*e65e175bSOded Gabbay #define SHADOW_3_AGU_S_MME3_CTRL_SECTION 0x2400 654*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E0C2Cull 655*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00 656*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION 0x4C00 657*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0C78ull 658*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 659*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400 660*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0C9Cull 661*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 662*e65e175bSOded Gabbay #define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400 663*e65e175bSOded Gabbay #define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0CC0ull 664*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00 665*e65e175bSOded Gabbay #define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION 0x4C00 666*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0D0Cull 667*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400 668*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400 669*e65e175bSOded Gabbay #define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0D30ull 670*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400 671*e65e175bSOded Gabbay #define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400 672*e65e175bSOded Gabbay #define mmSHADOW_3_DESC_MME3_CTRL_BASE 0x7FFC1E0D54ull 673*e65e175bSOded Gabbay #define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET 0x5400 674*e65e175bSOded Gabbay #define SHADOW_3_DESC_MME3_CTRL_SECTION 0x72AC 675*e65e175bSOded Gabbay #define mmMME3_QM_BASE 0x7FFC1E8000ull 676*e65e175bSOded Gabbay #define MME3_QM_MAX_OFFSET 0xD040 677*e65e175bSOded Gabbay #define MME3_QM_SECTION 0x18000 678*e65e175bSOded Gabbay #define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull 679*e65e175bSOded Gabbay #define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4000 680*e65e175bSOded Gabbay #define SRAM_Y0_X0_BANK_SECTION 0x1000 681*e65e175bSOded Gabbay #define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull 682*e65e175bSOded Gabbay #define SRAM_Y0_X0_RTR_MAX_OFFSET 0x3340 683*e65e175bSOded Gabbay #define SRAM_Y0_X0_RTR_SECTION 0x7000 684*e65e175bSOded Gabbay #define mmSRAM_Y0_X1_BANK_BASE 0x7FFC208000ull 685*e65e175bSOded Gabbay #define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4000 686*e65e175bSOded Gabbay #define SRAM_Y0_X1_BANK_SECTION 0x1000 687*e65e175bSOded Gabbay #define mmSRAM_Y0_X1_RTR_BASE 0x7FFC209000ull 688*e65e175bSOded Gabbay #define SRAM_Y0_X1_RTR_MAX_OFFSET 0x3340 689*e65e175bSOded Gabbay #define SRAM_Y0_X1_RTR_SECTION 0x7000 690*e65e175bSOded Gabbay #define mmSRAM_Y0_X2_BANK_BASE 0x7FFC210000ull 691*e65e175bSOded Gabbay #define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4000 692*e65e175bSOded Gabbay #define SRAM_Y0_X2_BANK_SECTION 0x1000 693*e65e175bSOded Gabbay #define mmSRAM_Y0_X2_RTR_BASE 0x7FFC211000ull 694*e65e175bSOded Gabbay #define SRAM_Y0_X2_RTR_MAX_OFFSET 0x3340 695*e65e175bSOded Gabbay #define SRAM_Y0_X2_RTR_SECTION 0x7000 696*e65e175bSOded Gabbay #define mmSRAM_Y0_X3_BANK_BASE 0x7FFC218000ull 697*e65e175bSOded Gabbay #define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4000 698*e65e175bSOded Gabbay #define SRAM_Y0_X3_BANK_SECTION 0x1000 699*e65e175bSOded Gabbay #define mmSRAM_Y0_X3_RTR_BASE 0x7FFC219000ull 700*e65e175bSOded Gabbay #define SRAM_Y0_X3_RTR_MAX_OFFSET 0x3340 701*e65e175bSOded Gabbay #define SRAM_Y0_X3_RTR_SECTION 0x7000 702*e65e175bSOded Gabbay #define mmSRAM_Y0_X4_BANK_BASE 0x7FFC220000ull 703*e65e175bSOded Gabbay #define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4000 704*e65e175bSOded Gabbay #define SRAM_Y0_X4_BANK_SECTION 0x1000 705*e65e175bSOded Gabbay #define mmSRAM_Y0_X4_RTR_BASE 0x7FFC221000ull 706*e65e175bSOded Gabbay #define SRAM_Y0_X4_RTR_MAX_OFFSET 0x3340 707*e65e175bSOded Gabbay #define SRAM_Y0_X4_RTR_SECTION 0x7000 708*e65e175bSOded Gabbay #define mmSRAM_Y0_X5_BANK_BASE 0x7FFC228000ull 709*e65e175bSOded Gabbay #define SRAM_Y0_X5_BANK_MAX_OFFSET 0x4000 710*e65e175bSOded Gabbay #define SRAM_Y0_X5_BANK_SECTION 0x1000 711*e65e175bSOded Gabbay #define mmSRAM_Y0_X5_RTR_BASE 0x7FFC229000ull 712*e65e175bSOded Gabbay #define SRAM_Y0_X5_RTR_MAX_OFFSET 0x3340 713*e65e175bSOded Gabbay #define SRAM_Y0_X5_RTR_SECTION 0x7000 714*e65e175bSOded Gabbay #define mmSRAM_Y0_X6_BANK_BASE 0x7FFC230000ull 715*e65e175bSOded Gabbay #define SRAM_Y0_X6_BANK_MAX_OFFSET 0x4000 716*e65e175bSOded Gabbay #define SRAM_Y0_X6_BANK_SECTION 0x1000 717*e65e175bSOded Gabbay #define mmSRAM_Y0_X6_RTR_BASE 0x7FFC231000ull 718*e65e175bSOded Gabbay #define SRAM_Y0_X6_RTR_MAX_OFFSET 0x3340 719*e65e175bSOded Gabbay #define SRAM_Y0_X6_RTR_SECTION 0x7000 720*e65e175bSOded Gabbay #define mmSRAM_Y0_X7_BANK_BASE 0x7FFC238000ull 721*e65e175bSOded Gabbay #define SRAM_Y0_X7_BANK_MAX_OFFSET 0x4000 722*e65e175bSOded Gabbay #define SRAM_Y0_X7_BANK_SECTION 0x1000 723*e65e175bSOded Gabbay #define mmSRAM_Y0_X7_RTR_BASE 0x7FFC239000ull 724*e65e175bSOded Gabbay #define SRAM_Y0_X7_RTR_MAX_OFFSET 0x3340 725*e65e175bSOded Gabbay #define SRAM_Y0_X7_RTR_SECTION 0x7000 726*e65e175bSOded Gabbay #define mmSRAM_Y1_X0_BANK_BASE 0x7FFC240000ull 727*e65e175bSOded Gabbay #define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4000 728*e65e175bSOded Gabbay #define SRAM_Y1_X0_BANK_SECTION 0x1000 729*e65e175bSOded Gabbay #define mmSRAM_Y1_X0_RTR_BASE 0x7FFC241000ull 730*e65e175bSOded Gabbay #define SRAM_Y1_X0_RTR_MAX_OFFSET 0x3340 731*e65e175bSOded Gabbay #define SRAM_Y1_X0_RTR_SECTION 0x7000 732*e65e175bSOded Gabbay #define mmSRAM_Y1_X1_BANK_BASE 0x7FFC248000ull 733*e65e175bSOded Gabbay #define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4000 734*e65e175bSOded Gabbay #define SRAM_Y1_X1_BANK_SECTION 0x1000 735*e65e175bSOded Gabbay #define mmSRAM_Y1_X1_RTR_BASE 0x7FFC249000ull 736*e65e175bSOded Gabbay #define SRAM_Y1_X1_RTR_MAX_OFFSET 0x3340 737*e65e175bSOded Gabbay #define SRAM_Y1_X1_RTR_SECTION 0x7000 738*e65e175bSOded Gabbay #define mmSRAM_Y1_X2_BANK_BASE 0x7FFC250000ull 739*e65e175bSOded Gabbay #define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4000 740*e65e175bSOded Gabbay #define SRAM_Y1_X2_BANK_SECTION 0x1000 741*e65e175bSOded Gabbay #define mmSRAM_Y1_X2_RTR_BASE 0x7FFC251000ull 742*e65e175bSOded Gabbay #define SRAM_Y1_X2_RTR_MAX_OFFSET 0x3340 743*e65e175bSOded Gabbay #define SRAM_Y1_X2_RTR_SECTION 0x7000 744*e65e175bSOded Gabbay #define mmSRAM_Y1_X3_BANK_BASE 0x7FFC258000ull 745*e65e175bSOded Gabbay #define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4000 746*e65e175bSOded Gabbay #define SRAM_Y1_X3_BANK_SECTION 0x1000 747*e65e175bSOded Gabbay #define mmSRAM_Y1_X3_RTR_BASE 0x7FFC259000ull 748*e65e175bSOded Gabbay #define SRAM_Y1_X3_RTR_MAX_OFFSET 0x3340 749*e65e175bSOded Gabbay #define SRAM_Y1_X3_RTR_SECTION 0x7000 750*e65e175bSOded Gabbay #define mmSRAM_Y1_X4_BANK_BASE 0x7FFC260000ull 751*e65e175bSOded Gabbay #define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4000 752*e65e175bSOded Gabbay #define SRAM_Y1_X4_BANK_SECTION 0x1000 753*e65e175bSOded Gabbay #define mmSRAM_Y1_X4_RTR_BASE 0x7FFC261000ull 754*e65e175bSOded Gabbay #define SRAM_Y1_X4_RTR_MAX_OFFSET 0x3340 755*e65e175bSOded Gabbay #define SRAM_Y1_X4_RTR_SECTION 0x7000 756*e65e175bSOded Gabbay #define mmSRAM_Y1_X5_BANK_BASE 0x7FFC268000ull 757*e65e175bSOded Gabbay #define SRAM_Y1_X5_BANK_MAX_OFFSET 0x4000 758*e65e175bSOded Gabbay #define SRAM_Y1_X5_BANK_SECTION 0x1000 759*e65e175bSOded Gabbay #define mmSRAM_Y1_X5_RTR_BASE 0x7FFC269000ull 760*e65e175bSOded Gabbay #define SRAM_Y1_X5_RTR_MAX_OFFSET 0x3340 761*e65e175bSOded Gabbay #define SRAM_Y1_X5_RTR_SECTION 0x7000 762*e65e175bSOded Gabbay #define mmSRAM_Y1_X6_BANK_BASE 0x7FFC270000ull 763*e65e175bSOded Gabbay #define SRAM_Y1_X6_BANK_MAX_OFFSET 0x4000 764*e65e175bSOded Gabbay #define SRAM_Y1_X6_BANK_SECTION 0x1000 765*e65e175bSOded Gabbay #define mmSRAM_Y1_X6_RTR_BASE 0x7FFC271000ull 766*e65e175bSOded Gabbay #define SRAM_Y1_X6_RTR_MAX_OFFSET 0x3340 767*e65e175bSOded Gabbay #define SRAM_Y1_X6_RTR_SECTION 0x7000 768*e65e175bSOded Gabbay #define mmSRAM_Y1_X7_BANK_BASE 0x7FFC278000ull 769*e65e175bSOded Gabbay #define SRAM_Y1_X7_BANK_MAX_OFFSET 0x4000 770*e65e175bSOded Gabbay #define SRAM_Y1_X7_BANK_SECTION 0x1000 771*e65e175bSOded Gabbay #define mmSRAM_Y1_X7_RTR_BASE 0x7FFC279000ull 772*e65e175bSOded Gabbay #define SRAM_Y1_X7_RTR_MAX_OFFSET 0x3340 773*e65e175bSOded Gabbay #define SRAM_Y1_X7_RTR_SECTION 0x7000 774*e65e175bSOded Gabbay #define mmSRAM_Y2_X0_BANK_BASE 0x7FFC280000ull 775*e65e175bSOded Gabbay #define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4000 776*e65e175bSOded Gabbay #define SRAM_Y2_X0_BANK_SECTION 0x1000 777*e65e175bSOded Gabbay #define mmSRAM_Y2_X0_RTR_BASE 0x7FFC281000ull 778*e65e175bSOded Gabbay #define SRAM_Y2_X0_RTR_MAX_OFFSET 0x3340 779*e65e175bSOded Gabbay #define SRAM_Y2_X0_RTR_SECTION 0x7000 780*e65e175bSOded Gabbay #define mmSRAM_Y2_X1_BANK_BASE 0x7FFC288000ull 781*e65e175bSOded Gabbay #define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4000 782*e65e175bSOded Gabbay #define SRAM_Y2_X1_BANK_SECTION 0x1000 783*e65e175bSOded Gabbay #define mmSRAM_Y2_X1_RTR_BASE 0x7FFC289000ull 784*e65e175bSOded Gabbay #define SRAM_Y2_X1_RTR_MAX_OFFSET 0x3340 785*e65e175bSOded Gabbay #define SRAM_Y2_X1_RTR_SECTION 0x7000 786*e65e175bSOded Gabbay #define mmSRAM_Y2_X2_BANK_BASE 0x7FFC290000ull 787*e65e175bSOded Gabbay #define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4000 788*e65e175bSOded Gabbay #define SRAM_Y2_X2_BANK_SECTION 0x1000 789*e65e175bSOded Gabbay #define mmSRAM_Y2_X2_RTR_BASE 0x7FFC291000ull 790*e65e175bSOded Gabbay #define SRAM_Y2_X2_RTR_MAX_OFFSET 0x3340 791*e65e175bSOded Gabbay #define SRAM_Y2_X2_RTR_SECTION 0x7000 792*e65e175bSOded Gabbay #define mmSRAM_Y2_X3_BANK_BASE 0x7FFC298000ull 793*e65e175bSOded Gabbay #define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4000 794*e65e175bSOded Gabbay #define SRAM_Y2_X3_BANK_SECTION 0x1000 795*e65e175bSOded Gabbay #define mmSRAM_Y2_X3_RTR_BASE 0x7FFC299000ull 796*e65e175bSOded Gabbay #define SRAM_Y2_X3_RTR_MAX_OFFSET 0x3340 797*e65e175bSOded Gabbay #define SRAM_Y2_X3_RTR_SECTION 0x7000 798*e65e175bSOded Gabbay #define mmSRAM_Y2_X4_BANK_BASE 0x7FFC2A0000ull 799*e65e175bSOded Gabbay #define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4000 800*e65e175bSOded Gabbay #define SRAM_Y2_X4_BANK_SECTION 0x1000 801*e65e175bSOded Gabbay #define mmSRAM_Y2_X4_RTR_BASE 0x7FFC2A1000ull 802*e65e175bSOded Gabbay #define SRAM_Y2_X4_RTR_MAX_OFFSET 0x3340 803*e65e175bSOded Gabbay #define SRAM_Y2_X4_RTR_SECTION 0x7000 804*e65e175bSOded Gabbay #define mmSRAM_Y2_X5_BANK_BASE 0x7FFC2A8000ull 805*e65e175bSOded Gabbay #define SRAM_Y2_X5_BANK_MAX_OFFSET 0x4000 806*e65e175bSOded Gabbay #define SRAM_Y2_X5_BANK_SECTION 0x1000 807*e65e175bSOded Gabbay #define mmSRAM_Y2_X5_RTR_BASE 0x7FFC2A9000ull 808*e65e175bSOded Gabbay #define SRAM_Y2_X5_RTR_MAX_OFFSET 0x3340 809*e65e175bSOded Gabbay #define SRAM_Y2_X5_RTR_SECTION 0x7000 810*e65e175bSOded Gabbay #define mmSRAM_Y2_X6_BANK_BASE 0x7FFC2B0000ull 811*e65e175bSOded Gabbay #define SRAM_Y2_X6_BANK_MAX_OFFSET 0x4000 812*e65e175bSOded Gabbay #define SRAM_Y2_X6_BANK_SECTION 0x1000 813*e65e175bSOded Gabbay #define mmSRAM_Y2_X6_RTR_BASE 0x7FFC2B1000ull 814*e65e175bSOded Gabbay #define SRAM_Y2_X6_RTR_MAX_OFFSET 0x3340 815*e65e175bSOded Gabbay #define SRAM_Y2_X6_RTR_SECTION 0x7000 816*e65e175bSOded Gabbay #define mmSRAM_Y2_X7_BANK_BASE 0x7FFC2B8000ull 817*e65e175bSOded Gabbay #define SRAM_Y2_X7_BANK_MAX_OFFSET 0x4000 818*e65e175bSOded Gabbay #define SRAM_Y2_X7_BANK_SECTION 0x1000 819*e65e175bSOded Gabbay #define mmSRAM_Y2_X7_RTR_BASE 0x7FFC2B9000ull 820*e65e175bSOded Gabbay #define SRAM_Y2_X7_RTR_MAX_OFFSET 0x3340 821*e65e175bSOded Gabbay #define SRAM_Y2_X7_RTR_SECTION 0x7000 822*e65e175bSOded Gabbay #define mmSRAM_Y3_X0_BANK_BASE 0x7FFC2C0000ull 823*e65e175bSOded Gabbay #define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4000 824*e65e175bSOded Gabbay #define SRAM_Y3_X0_BANK_SECTION 0x1000 825*e65e175bSOded Gabbay #define mmSRAM_Y3_X0_RTR_BASE 0x7FFC2C1000ull 826*e65e175bSOded Gabbay #define SRAM_Y3_X0_RTR_MAX_OFFSET 0x3340 827*e65e175bSOded Gabbay #define SRAM_Y3_X0_RTR_SECTION 0x7000 828*e65e175bSOded Gabbay #define mmSRAM_Y3_X1_BANK_BASE 0x7FFC2C8000ull 829*e65e175bSOded Gabbay #define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4000 830*e65e175bSOded Gabbay #define SRAM_Y3_X1_BANK_SECTION 0x1000 831*e65e175bSOded Gabbay #define mmSRAM_Y3_X1_RTR_BASE 0x7FFC2C9000ull 832*e65e175bSOded Gabbay #define SRAM_Y3_X1_RTR_MAX_OFFSET 0x3340 833*e65e175bSOded Gabbay #define SRAM_Y3_X1_RTR_SECTION 0x7000 834*e65e175bSOded Gabbay #define mmSRAM_Y3_X2_BANK_BASE 0x7FFC2D0000ull 835*e65e175bSOded Gabbay #define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4000 836*e65e175bSOded Gabbay #define SRAM_Y3_X2_BANK_SECTION 0x1000 837*e65e175bSOded Gabbay #define mmSRAM_Y3_X2_RTR_BASE 0x7FFC2D1000ull 838*e65e175bSOded Gabbay #define SRAM_Y3_X2_RTR_MAX_OFFSET 0x3340 839*e65e175bSOded Gabbay #define SRAM_Y3_X2_RTR_SECTION 0x7000 840*e65e175bSOded Gabbay #define mmSRAM_Y3_X3_BANK_BASE 0x7FFC2D8000ull 841*e65e175bSOded Gabbay #define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4000 842*e65e175bSOded Gabbay #define SRAM_Y3_X3_BANK_SECTION 0x1000 843*e65e175bSOded Gabbay #define mmSRAM_Y3_X3_RTR_BASE 0x7FFC2D9000ull 844*e65e175bSOded Gabbay #define SRAM_Y3_X3_RTR_MAX_OFFSET 0x3340 845*e65e175bSOded Gabbay #define SRAM_Y3_X3_RTR_SECTION 0x7000 846*e65e175bSOded Gabbay #define mmSRAM_Y3_X4_BANK_BASE 0x7FFC2E0000ull 847*e65e175bSOded Gabbay #define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4000 848*e65e175bSOded Gabbay #define SRAM_Y3_X4_BANK_SECTION 0x1000 849*e65e175bSOded Gabbay #define mmSRAM_Y3_X4_RTR_BASE 0x7FFC2E1000ull 850*e65e175bSOded Gabbay #define SRAM_Y3_X4_RTR_MAX_OFFSET 0x3340 851*e65e175bSOded Gabbay #define SRAM_Y3_X4_RTR_SECTION 0x7000 852*e65e175bSOded Gabbay #define mmSRAM_Y3_X5_BANK_BASE 0x7FFC2E8000ull 853*e65e175bSOded Gabbay #define SRAM_Y3_X5_BANK_MAX_OFFSET 0x4000 854*e65e175bSOded Gabbay #define SRAM_Y3_X5_BANK_SECTION 0x1000 855*e65e175bSOded Gabbay #define mmSRAM_Y3_X5_RTR_BASE 0x7FFC2E9000ull 856*e65e175bSOded Gabbay #define SRAM_Y3_X5_RTR_MAX_OFFSET 0x3340 857*e65e175bSOded Gabbay #define SRAM_Y3_X5_RTR_SECTION 0x7000 858*e65e175bSOded Gabbay #define mmSRAM_Y3_X6_BANK_BASE 0x7FFC2F0000ull 859*e65e175bSOded Gabbay #define SRAM_Y3_X6_BANK_MAX_OFFSET 0x4000 860*e65e175bSOded Gabbay #define SRAM_Y3_X6_BANK_SECTION 0x1000 861*e65e175bSOded Gabbay #define mmSRAM_Y3_X6_RTR_BASE 0x7FFC2F1000ull 862*e65e175bSOded Gabbay #define SRAM_Y3_X6_RTR_MAX_OFFSET 0x3340 863*e65e175bSOded Gabbay #define SRAM_Y3_X6_RTR_SECTION 0x7000 864*e65e175bSOded Gabbay #define mmSRAM_Y3_X7_BANK_BASE 0x7FFC2F8000ull 865*e65e175bSOded Gabbay #define SRAM_Y3_X7_BANK_MAX_OFFSET 0x4000 866*e65e175bSOded Gabbay #define SRAM_Y3_X7_BANK_SECTION 0x1000 867*e65e175bSOded Gabbay #define mmSRAM_Y3_X7_RTR_BASE 0x7FFC2F9000ull 868*e65e175bSOded Gabbay #define SRAM_Y3_X7_RTR_MAX_OFFSET 0x3340 869*e65e175bSOded Gabbay #define SRAM_Y3_X7_RTR_SECTION 0x7000 870*e65e175bSOded Gabbay #define mmSIF_RTR_0_BASE 0x7FFC300000ull 871*e65e175bSOded Gabbay #define SIF_RTR_0_MAX_OFFSET 0x6500 872*e65e175bSOded Gabbay #define SIF_RTR_0_SECTION 0x6000 873*e65e175bSOded Gabbay #define mmSIF_RTR_CTRL_0_BASE 0x7FFC306000ull 874*e65e175bSOded Gabbay #define SIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 875*e65e175bSOded Gabbay #define SIF_RTR_CTRL_0_SECTION 0xA000 876*e65e175bSOded Gabbay #define mmSIF_RTR_1_BASE 0x7FFC310000ull 877*e65e175bSOded Gabbay #define SIF_RTR_1_MAX_OFFSET 0x6500 878*e65e175bSOded Gabbay #define SIF_RTR_1_SECTION 0x6000 879*e65e175bSOded Gabbay #define mmSIF_RTR_CTRL_1_BASE 0x7FFC316000ull 880*e65e175bSOded Gabbay #define SIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 881*e65e175bSOded Gabbay #define SIF_RTR_CTRL_1_SECTION 0xA000 882*e65e175bSOded Gabbay #define mmSIF_RTR_2_BASE 0x7FFC320000ull 883*e65e175bSOded Gabbay #define SIF_RTR_2_MAX_OFFSET 0x6500 884*e65e175bSOded Gabbay #define SIF_RTR_2_SECTION 0x6000 885*e65e175bSOded Gabbay #define mmSIF_RTR_CTRL_2_BASE 0x7FFC326000ull 886*e65e175bSOded Gabbay #define SIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 887*e65e175bSOded Gabbay #define SIF_RTR_CTRL_2_SECTION 0xA000 888*e65e175bSOded Gabbay #define mmSIF_RTR_3_BASE 0x7FFC330000ull 889*e65e175bSOded Gabbay #define SIF_RTR_3_MAX_OFFSET 0x6500 890*e65e175bSOded Gabbay #define SIF_RTR_3_SECTION 0x6000 891*e65e175bSOded Gabbay #define mmSIF_RTR_CTRL_3_BASE 0x7FFC336000ull 892*e65e175bSOded Gabbay #define SIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 893*e65e175bSOded Gabbay #define SIF_RTR_CTRL_3_SECTION 0xA000 894*e65e175bSOded Gabbay #define mmSIF_RTR_4_BASE 0x7FFC340000ull 895*e65e175bSOded Gabbay #define SIF_RTR_4_MAX_OFFSET 0x6500 896*e65e175bSOded Gabbay #define SIF_RTR_4_SECTION 0x6000 897*e65e175bSOded Gabbay #define mmSIF_RTR_CTRL_4_BASE 0x7FFC346000ull 898*e65e175bSOded Gabbay #define SIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 899*e65e175bSOded Gabbay #define SIF_RTR_CTRL_4_SECTION 0xA000 900*e65e175bSOded Gabbay #define mmSIF_RTR_5_BASE 0x7FFC350000ull 901*e65e175bSOded Gabbay #define SIF_RTR_5_MAX_OFFSET 0x6500 902*e65e175bSOded Gabbay #define SIF_RTR_5_SECTION 0x6000 903*e65e175bSOded Gabbay #define mmSIF_RTR_CTRL_5_BASE 0x7FFC356000ull 904*e65e175bSOded Gabbay #define SIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 905*e65e175bSOded Gabbay #define SIF_RTR_CTRL_5_SECTION 0xA000 906*e65e175bSOded Gabbay #define mmSIF_RTR_6_BASE 0x7FFC360000ull 907*e65e175bSOded Gabbay #define SIF_RTR_6_MAX_OFFSET 0x6500 908*e65e175bSOded Gabbay #define SIF_RTR_6_SECTION 0x6000 909*e65e175bSOded Gabbay #define mmSIF_RTR_CTRL_6_BASE 0x7FFC366000ull 910*e65e175bSOded Gabbay #define SIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 911*e65e175bSOded Gabbay #define SIF_RTR_CTRL_6_SECTION 0xA000 912*e65e175bSOded Gabbay #define mmSIF_RTR_7_BASE 0x7FFC370000ull 913*e65e175bSOded Gabbay #define SIF_RTR_7_MAX_OFFSET 0x6500 914*e65e175bSOded Gabbay #define SIF_RTR_7_SECTION 0x6000 915*e65e175bSOded Gabbay #define mmSIF_RTR_CTRL_7_BASE 0x7FFC376000ull 916*e65e175bSOded Gabbay #define SIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 917*e65e175bSOded Gabbay #define SIF_RTR_CTRL_7_SECTION 0xA000 918*e65e175bSOded Gabbay #define mmNIF_RTR_0_BASE 0x7FFC380000ull 919*e65e175bSOded Gabbay #define NIF_RTR_0_MAX_OFFSET 0x6500 920*e65e175bSOded Gabbay #define NIF_RTR_0_SECTION 0x6000 921*e65e175bSOded Gabbay #define mmNIF_RTR_CTRL_0_BASE 0x7FFC386000ull 922*e65e175bSOded Gabbay #define NIF_RTR_CTRL_0_MAX_OFFSET 0xCC00 923*e65e175bSOded Gabbay #define NIF_RTR_CTRL_0_SECTION 0xA000 924*e65e175bSOded Gabbay #define mmNIF_RTR_1_BASE 0x7FFC390000ull 925*e65e175bSOded Gabbay #define NIF_RTR_1_MAX_OFFSET 0x6500 926*e65e175bSOded Gabbay #define NIF_RTR_1_SECTION 0x6000 927*e65e175bSOded Gabbay #define mmNIF_RTR_CTRL_1_BASE 0x7FFC396000ull 928*e65e175bSOded Gabbay #define NIF_RTR_CTRL_1_MAX_OFFSET 0xCC00 929*e65e175bSOded Gabbay #define NIF_RTR_CTRL_1_SECTION 0xA000 930*e65e175bSOded Gabbay #define mmNIF_RTR_2_BASE 0x7FFC3A0000ull 931*e65e175bSOded Gabbay #define NIF_RTR_2_MAX_OFFSET 0x6500 932*e65e175bSOded Gabbay #define NIF_RTR_2_SECTION 0x6000 933*e65e175bSOded Gabbay #define mmNIF_RTR_CTRL_2_BASE 0x7FFC3A6000ull 934*e65e175bSOded Gabbay #define NIF_RTR_CTRL_2_MAX_OFFSET 0xCC00 935*e65e175bSOded Gabbay #define NIF_RTR_CTRL_2_SECTION 0xA000 936*e65e175bSOded Gabbay #define mmNIF_RTR_3_BASE 0x7FFC3B0000ull 937*e65e175bSOded Gabbay #define NIF_RTR_3_MAX_OFFSET 0x6500 938*e65e175bSOded Gabbay #define NIF_RTR_3_SECTION 0x6000 939*e65e175bSOded Gabbay #define mmNIF_RTR_CTRL_3_BASE 0x7FFC3B6000ull 940*e65e175bSOded Gabbay #define NIF_RTR_CTRL_3_MAX_OFFSET 0xCC00 941*e65e175bSOded Gabbay #define NIF_RTR_CTRL_3_SECTION 0xA000 942*e65e175bSOded Gabbay #define mmNIF_RTR_4_BASE 0x7FFC3C0000ull 943*e65e175bSOded Gabbay #define NIF_RTR_4_MAX_OFFSET 0x6500 944*e65e175bSOded Gabbay #define NIF_RTR_4_SECTION 0x6000 945*e65e175bSOded Gabbay #define mmNIF_RTR_CTRL_4_BASE 0x7FFC3C6000ull 946*e65e175bSOded Gabbay #define NIF_RTR_CTRL_4_MAX_OFFSET 0xCC00 947*e65e175bSOded Gabbay #define NIF_RTR_CTRL_4_SECTION 0xA000 948*e65e175bSOded Gabbay #define mmNIF_RTR_5_BASE 0x7FFC3D0000ull 949*e65e175bSOded Gabbay #define NIF_RTR_5_MAX_OFFSET 0x6500 950*e65e175bSOded Gabbay #define NIF_RTR_5_SECTION 0x6000 951*e65e175bSOded Gabbay #define mmNIF_RTR_CTRL_5_BASE 0x7FFC3D6000ull 952*e65e175bSOded Gabbay #define NIF_RTR_CTRL_5_MAX_OFFSET 0xCC00 953*e65e175bSOded Gabbay #define NIF_RTR_CTRL_5_SECTION 0xA000 954*e65e175bSOded Gabbay #define mmNIF_RTR_6_BASE 0x7FFC3E0000ull 955*e65e175bSOded Gabbay #define NIF_RTR_6_MAX_OFFSET 0x6500 956*e65e175bSOded Gabbay #define NIF_RTR_6_SECTION 0x6000 957*e65e175bSOded Gabbay #define mmNIF_RTR_CTRL_6_BASE 0x7FFC3E6000ull 958*e65e175bSOded Gabbay #define NIF_RTR_CTRL_6_MAX_OFFSET 0xCC00 959*e65e175bSOded Gabbay #define NIF_RTR_CTRL_6_SECTION 0xA000 960*e65e175bSOded Gabbay #define mmNIF_RTR_7_BASE 0x7FFC3F0000ull 961*e65e175bSOded Gabbay #define NIF_RTR_7_MAX_OFFSET 0x6500 962*e65e175bSOded Gabbay #define NIF_RTR_7_SECTION 0x6000 963*e65e175bSOded Gabbay #define mmNIF_RTR_CTRL_7_BASE 0x7FFC3F6000ull 964*e65e175bSOded Gabbay #define NIF_RTR_CTRL_7_MAX_OFFSET 0xCC00 965*e65e175bSOded Gabbay #define NIF_RTR_CTRL_7_SECTION 0x4B000 966*e65e175bSOded Gabbay #define mmCPU_CA53_CFG_BASE 0x7FFC441000ull 967*e65e175bSOded Gabbay #define CPU_CA53_CFG_MAX_OFFSET 0x2180 968*e65e175bSOded Gabbay #define CPU_CA53_CFG_SECTION 0x1000 969*e65e175bSOded Gabbay #define mmCPU_IF_BASE 0x7FFC442000ull 970*e65e175bSOded Gabbay #define CPU_IF_MAX_OFFSET 0x43C0 971*e65e175bSOded Gabbay #define CPU_IF_SECTION 0x2000 972*e65e175bSOded Gabbay #define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull 973*e65e175bSOded Gabbay #define CPU_TIMESTAMP_MAX_OFFSET 0x1000 974*e65e175bSOded Gabbay #define CPU_TIMESTAMP_SECTION 0x3C000 975*e65e175bSOded Gabbay #define mmDMA_IF_W_S_BASE 0x7FFC480000ull 976*e65e175bSOded Gabbay #define DMA_IF_W_S_MAX_OFFSET 0x8380 977*e65e175bSOded Gabbay #define DMA_IF_W_S_SECTION 0x1000 978*e65e175bSOded Gabbay #define mmDMA_IF_W_S_DOWN_CH0_BASE 0x7FFC481000ull 979*e65e175bSOded Gabbay #define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET 0xCC00 980*e65e175bSOded Gabbay #define DMA_IF_W_S_DOWN_CH0_SECTION 0x1000 981*e65e175bSOded Gabbay #define mmDMA_IF_W_S_DOWN_CH1_BASE 0x7FFC482000ull 982*e65e175bSOded Gabbay #define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET 0xCC00 983*e65e175bSOded Gabbay #define DMA_IF_W_S_DOWN_CH1_SECTION 0x5000 984*e65e175bSOded Gabbay #define mmDMA_W_PLL_BASE 0x7FFC487000ull 985*e65e175bSOded Gabbay #define DMA_W_PLL_MAX_OFFSET 0x5200 986*e65e175bSOded Gabbay #define DMA_W_PLL_SECTION 0x1000 987*e65e175bSOded Gabbay #define mmIF_W_PLL_BASE 0x7FFC488000ull 988*e65e175bSOded Gabbay #define IF_W_PLL_MAX_OFFSET 0x5200 989*e65e175bSOded Gabbay #define IF_W_PLL_SECTION 0x1000 990*e65e175bSOded Gabbay #define mmDMA_IF_W_S_DOWN_BASE 0x7FFC489000ull 991*e65e175bSOded Gabbay #define DMA_IF_W_S_DOWN_MAX_OFFSET 0x1500 992*e65e175bSOded Gabbay #define DMA_IF_W_S_DOWN_SECTION 0x7000 993*e65e175bSOded Gabbay #define mmSYNC_MNGR_GLBL_W_S_BASE 0x7FFC490000ull 994*e65e175bSOded Gabbay #define SYNC_MNGR_GLBL_W_S_MAX_OFFSET 0x6C00 995*e65e175bSOded Gabbay #define SYNC_MNGR_GLBL_W_S_SECTION 0x1000 996*e65e175bSOded Gabbay #define mmSYNC_MNGR_OBJS_W_S_BASE 0x7FFC491000ull 997*e65e175bSOded Gabbay #define SYNC_MNGR_OBJS_W_S_MAX_OFFSET 0x5C00 998*e65e175bSOded Gabbay #define SYNC_MNGR_OBJS_W_S_SECTION 0xF000 999*e65e175bSOded Gabbay #define mmDMA_IF_E_S_BASE 0x7FFC4A0000ull 1000*e65e175bSOded Gabbay #define DMA_IF_E_S_MAX_OFFSET 0x8380 1001*e65e175bSOded Gabbay #define DMA_IF_E_S_SECTION 0x1000 1002*e65e175bSOded Gabbay #define mmDMA_IF_E_S_DOWN_CH0_BASE 0x7FFC4A1000ull 1003*e65e175bSOded Gabbay #define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET 0xCC00 1004*e65e175bSOded Gabbay #define DMA_IF_E_S_DOWN_CH0_SECTION 0x1000 1005*e65e175bSOded Gabbay #define mmDMA_IF_E_S_DOWN_CH1_BASE 0x7FFC4A2000ull 1006*e65e175bSOded Gabbay #define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET 0xCC00 1007*e65e175bSOded Gabbay #define DMA_IF_E_S_DOWN_CH1_SECTION 0x5000 1008*e65e175bSOded Gabbay #define mmIF_E_PLL_BASE 0x7FFC4A7000ull 1009*e65e175bSOded Gabbay #define IF_E_PLL_MAX_OFFSET 0x5200 1010*e65e175bSOded Gabbay #define IF_E_PLL_SECTION 0x1000 1011*e65e175bSOded Gabbay #define mmDMA_E_PLL_BASE 0x7FFC4A8000ull 1012*e65e175bSOded Gabbay #define DMA_E_PLL_MAX_OFFSET 0x5200 1013*e65e175bSOded Gabbay #define DMA_E_PLL_SECTION 0x1000 1014*e65e175bSOded Gabbay #define mmDMA_IF_E_S_DOWN_BASE 0x7FFC4A9000ull 1015*e65e175bSOded Gabbay #define DMA_IF_E_S_DOWN_MAX_OFFSET 0x1500 1016*e65e175bSOded Gabbay #define DMA_IF_E_S_DOWN_SECTION 0x7000 1017*e65e175bSOded Gabbay #define mmSYNC_MNGR_GLBL_E_S_BASE 0x7FFC4B0000ull 1018*e65e175bSOded Gabbay #define SYNC_MNGR_GLBL_E_S_MAX_OFFSET 0x6C00 1019*e65e175bSOded Gabbay #define SYNC_MNGR_GLBL_E_S_SECTION 0x1000 1020*e65e175bSOded Gabbay #define mmSYNC_MNGR_OBJS_E_S_BASE 0x7FFC4B1000ull 1021*e65e175bSOded Gabbay #define SYNC_MNGR_OBJS_E_S_MAX_OFFSET 0x5C00 1022*e65e175bSOded Gabbay #define SYNC_MNGR_OBJS_E_S_SECTION 0xF000 1023*e65e175bSOded Gabbay #define mmDMA_IF_W_N_BASE 0x7FFC4C0000ull 1024*e65e175bSOded Gabbay #define DMA_IF_W_N_MAX_OFFSET 0x8380 1025*e65e175bSOded Gabbay #define DMA_IF_W_N_SECTION 0x1000 1026*e65e175bSOded Gabbay #define mmDMA_IF_W_N_DOWN_CH0_BASE 0x7FFC4C1000ull 1027*e65e175bSOded Gabbay #define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET 0xCC00 1028*e65e175bSOded Gabbay #define DMA_IF_W_N_DOWN_CH0_SECTION 0x1000 1029*e65e175bSOded Gabbay #define mmDMA_IF_W_N_DOWN_CH1_BASE 0x7FFC4C2000ull 1030*e65e175bSOded Gabbay #define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET 0xCC00 1031*e65e175bSOded Gabbay #define DMA_IF_W_N_DOWN_CH1_SECTION 0x5000 1032*e65e175bSOded Gabbay #define mmMESH_W_PLL_BASE 0x7FFC4C7000ull 1033*e65e175bSOded Gabbay #define MESH_W_PLL_MAX_OFFSET 0x5200 1034*e65e175bSOded Gabbay #define MESH_W_PLL_SECTION 0x1000 1035*e65e175bSOded Gabbay #define mmSRAM_W_PLL_BASE 0x7FFC4C8000ull 1036*e65e175bSOded Gabbay #define SRAM_W_PLL_MAX_OFFSET 0x5200 1037*e65e175bSOded Gabbay #define SRAM_W_PLL_SECTION 0x1000 1038*e65e175bSOded Gabbay #define mmDMA_IF_W_N_DOWN_BASE 0x7FFC4C9000ull 1039*e65e175bSOded Gabbay #define DMA_IF_W_N_DOWN_MAX_OFFSET 0x1500 1040*e65e175bSOded Gabbay #define DMA_IF_W_N_DOWN_SECTION 0x7000 1041*e65e175bSOded Gabbay #define mmSYNC_MNGR_GLBL_W_N_BASE 0x7FFC4D0000ull 1042*e65e175bSOded Gabbay #define SYNC_MNGR_GLBL_W_N_MAX_OFFSET 0x6C00 1043*e65e175bSOded Gabbay #define SYNC_MNGR_GLBL_W_N_SECTION 0x1000 1044*e65e175bSOded Gabbay #define mmSYNC_MNGR_OBJS_W_N_BASE 0x7FFC4D1000ull 1045*e65e175bSOded Gabbay #define SYNC_MNGR_OBJS_W_N_MAX_OFFSET 0x5C00 1046*e65e175bSOded Gabbay #define SYNC_MNGR_OBJS_W_N_SECTION 0xF000 1047*e65e175bSOded Gabbay #define mmDMA_IF_E_N_BASE 0x7FFC4E0000ull 1048*e65e175bSOded Gabbay #define DMA_IF_E_N_MAX_OFFSET 0x8380 1049*e65e175bSOded Gabbay #define DMA_IF_E_N_SECTION 0x1000 1050*e65e175bSOded Gabbay #define mmDMA_IF_E_N_DOWN_CH0_BASE 0x7FFC4E1000ull 1051*e65e175bSOded Gabbay #define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET 0xCC00 1052*e65e175bSOded Gabbay #define DMA_IF_E_N_DOWN_CH0_SECTION 0x1000 1053*e65e175bSOded Gabbay #define mmDMA_IF_E_N_DOWN_CH1_BASE 0x7FFC4E2000ull 1054*e65e175bSOded Gabbay #define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET 0xCC00 1055*e65e175bSOded Gabbay #define DMA_IF_E_N_DOWN_CH1_SECTION 0x5000 1056*e65e175bSOded Gabbay #define mmMESH_E_PLL_BASE 0x7FFC4E7000ull 1057*e65e175bSOded Gabbay #define MESH_E_PLL_MAX_OFFSET 0x5200 1058*e65e175bSOded Gabbay #define MESH_E_PLL_SECTION 0x1000 1059*e65e175bSOded Gabbay #define mmSRAM_E_PLL_BASE 0x7FFC4E8000ull 1060*e65e175bSOded Gabbay #define SRAM_E_PLL_MAX_OFFSET 0x5200 1061*e65e175bSOded Gabbay #define SRAM_E_PLL_SECTION 0x1000 1062*e65e175bSOded Gabbay #define mmDMA_IF_E_N_DOWN_BASE 0x7FFC4E9000ull 1063*e65e175bSOded Gabbay #define DMA_IF_E_N_DOWN_MAX_OFFSET 0x1500 1064*e65e175bSOded Gabbay #define DMA_IF_E_N_DOWN_SECTION 0x7000 1065*e65e175bSOded Gabbay #define mmSYNC_MNGR_GLBL_E_N_BASE 0x7FFC4F0000ull 1066*e65e175bSOded Gabbay #define SYNC_MNGR_GLBL_E_N_MAX_OFFSET 0x6C00 1067*e65e175bSOded Gabbay #define SYNC_MNGR_GLBL_E_N_SECTION 0x1000 1068*e65e175bSOded Gabbay #define mmSYNC_MNGR_OBJS_E_N_BASE 0x7FFC4F1000ull 1069*e65e175bSOded Gabbay #define SYNC_MNGR_OBJS_E_N_MAX_OFFSET 0x5C00 1070*e65e175bSOded Gabbay #define SYNC_MNGR_OBJS_E_N_SECTION 0xF000 1071*e65e175bSOded Gabbay #define mmDMA0_CORE_BASE 0x7FFC500000ull 1072*e65e175bSOded Gabbay #define DMA0_CORE_MAX_OFFSET 0x23C0 1073*e65e175bSOded Gabbay #define DMA0_CORE_SECTION 0x8000 1074*e65e175bSOded Gabbay #define mmDMA0_QM_BASE 0x7FFC508000ull 1075*e65e175bSOded Gabbay #define DMA0_QM_MAX_OFFSET 0xD040 1076*e65e175bSOded Gabbay #define DMA0_QM_SECTION 0x18000 1077*e65e175bSOded Gabbay #define mmDMA1_CORE_BASE 0x7FFC520000ull 1078*e65e175bSOded Gabbay #define DMA1_CORE_MAX_OFFSET 0x23C0 1079*e65e175bSOded Gabbay #define DMA1_CORE_SECTION 0x8000 1080*e65e175bSOded Gabbay #define mmDMA1_QM_BASE 0x7FFC528000ull 1081*e65e175bSOded Gabbay #define DMA1_QM_MAX_OFFSET 0xD040 1082*e65e175bSOded Gabbay #define DMA1_QM_SECTION 0x18000 1083*e65e175bSOded Gabbay #define mmDMA2_CORE_BASE 0x7FFC540000ull 1084*e65e175bSOded Gabbay #define DMA2_CORE_MAX_OFFSET 0x23C0 1085*e65e175bSOded Gabbay #define DMA2_CORE_SECTION 0x8000 1086*e65e175bSOded Gabbay #define mmDMA2_QM_BASE 0x7FFC548000ull 1087*e65e175bSOded Gabbay #define DMA2_QM_MAX_OFFSET 0xD040 1088*e65e175bSOded Gabbay #define DMA2_QM_SECTION 0x18000 1089*e65e175bSOded Gabbay #define mmDMA3_CORE_BASE 0x7FFC560000ull 1090*e65e175bSOded Gabbay #define DMA3_CORE_MAX_OFFSET 0x23C0 1091*e65e175bSOded Gabbay #define DMA3_CORE_SECTION 0x8000 1092*e65e175bSOded Gabbay #define mmDMA3_QM_BASE 0x7FFC568000ull 1093*e65e175bSOded Gabbay #define DMA3_QM_MAX_OFFSET 0xD040 1094*e65e175bSOded Gabbay #define DMA3_QM_SECTION 0x18000 1095*e65e175bSOded Gabbay #define mmDMA4_CORE_BASE 0x7FFC580000ull 1096*e65e175bSOded Gabbay #define DMA4_CORE_MAX_OFFSET 0x23C0 1097*e65e175bSOded Gabbay #define DMA4_CORE_SECTION 0x8000 1098*e65e175bSOded Gabbay #define mmDMA4_QM_BASE 0x7FFC588000ull 1099*e65e175bSOded Gabbay #define DMA4_QM_MAX_OFFSET 0xD040 1100*e65e175bSOded Gabbay #define DMA4_QM_SECTION 0x18000 1101*e65e175bSOded Gabbay #define mmDMA5_CORE_BASE 0x7FFC5A0000ull 1102*e65e175bSOded Gabbay #define DMA5_CORE_MAX_OFFSET 0x23C0 1103*e65e175bSOded Gabbay #define DMA5_CORE_SECTION 0x8000 1104*e65e175bSOded Gabbay #define mmDMA5_QM_BASE 0x7FFC5A8000ull 1105*e65e175bSOded Gabbay #define DMA5_QM_MAX_OFFSET 0xD040 1106*e65e175bSOded Gabbay #define DMA5_QM_SECTION 0x18000 1107*e65e175bSOded Gabbay #define mmDMA6_CORE_BASE 0x7FFC5C0000ull 1108*e65e175bSOded Gabbay #define DMA6_CORE_MAX_OFFSET 0x23C0 1109*e65e175bSOded Gabbay #define DMA6_CORE_SECTION 0x8000 1110*e65e175bSOded Gabbay #define mmDMA6_QM_BASE 0x7FFC5C8000ull 1111*e65e175bSOded Gabbay #define DMA6_QM_MAX_OFFSET 0xD040 1112*e65e175bSOded Gabbay #define DMA6_QM_SECTION 0x18000 1113*e65e175bSOded Gabbay #define mmDMA7_CORE_BASE 0x7FFC5E0000ull 1114*e65e175bSOded Gabbay #define DMA7_CORE_MAX_OFFSET 0x23C0 1115*e65e175bSOded Gabbay #define DMA7_CORE_SECTION 0x8000 1116*e65e175bSOded Gabbay #define mmDMA7_QM_BASE 0x7FFC5E8000ull 1117*e65e175bSOded Gabbay #define DMA7_QM_MAX_OFFSET 0xD040 1118*e65e175bSOded Gabbay #define DMA7_QM_SECTION 0x18000 1119*e65e175bSOded Gabbay #define mmHBM0_BASE 0x7FFC600000ull 1120*e65e175bSOded Gabbay #define HBM0_MAX_OFFSET 0x8F58 1121*e65e175bSOded Gabbay #define HBM0_SECTION 0x80000 1122*e65e175bSOded Gabbay #define mmHBM1_BASE 0x7FFC680000ull 1123*e65e175bSOded Gabbay #define HBM1_MAX_OFFSET 0x8F58 1124*e65e175bSOded Gabbay #define HBM1_SECTION 0x80000 1125*e65e175bSOded Gabbay #define mmHBM2_BASE 0x7FFC700000ull 1126*e65e175bSOded Gabbay #define HBM2_MAX_OFFSET 0x8F58 1127*e65e175bSOded Gabbay #define HBM2_SECTION 0x80000 1128*e65e175bSOded Gabbay #define mmHBM3_BASE 0x7FFC780000ull 1129*e65e175bSOded Gabbay #define HBM3_MAX_OFFSET 0x8F58 1130*e65e175bSOded Gabbay #define HBM3_SECTION 0x80000 1131*e65e175bSOded Gabbay #define mmGIC_BASE 0x7FFC800000ull 1132*e65e175bSOded Gabbay #define GIC_MAX_OFFSET 0x10000 1133*e65e175bSOded Gabbay #define GIC_SECTION 0x401000 1134*e65e175bSOded Gabbay #define mmPCIE_WRAP_BASE 0x7FFCC01000ull 1135*e65e175bSOded Gabbay #define PCIE_WRAP_MAX_OFFSET 0xDF00 1136*e65e175bSOded Gabbay #define PCIE_WRAP_SECTION 0x1000 1137*e65e175bSOded Gabbay #define mmPCIE_DBI_BASE 0x7FFCC02000ull 1138*e65e175bSOded Gabbay #define PCIE_DBI_MAX_OFFSET 0xC040 1139*e65e175bSOded Gabbay #define PCIE_DBI_SECTION 0x2000 1140*e65e175bSOded Gabbay #define mmPCIE_CORE_BASE 0x7FFCC04000ull 1141*e65e175bSOded Gabbay #define PCIE_CORE_MAX_OFFSET 0x9BC0 1142*e65e175bSOded Gabbay #define PCIE_CORE_SECTION 0x3000 1143*e65e175bSOded Gabbay #define mmPCIE_AUX_BASE 0x7FFCC07000ull 1144*e65e175bSOded Gabbay #define PCIE_AUX_MAX_OFFSET 0x9C40 1145*e65e175bSOded Gabbay #define PCIE_AUX_SECTION 0x9000 1146*e65e175bSOded Gabbay #define mmPCIE_PHY_BASE 0x7FFCC10000ull 1147*e65e175bSOded Gabbay #define PCIE_PHY_MAX_OFFSET 0x9640 1148*e65e175bSOded Gabbay #define PCIE_PHY_SECTION 0x1000 1149*e65e175bSOded Gabbay #define mmMMU_UP_BASE 0x7FFCC11000ull 1150*e65e175bSOded Gabbay #define MMU_UP_MAX_OFFSET 0x7000 1151*e65e175bSOded Gabbay #define MMU_UP_SECTION 0x1000 1152*e65e175bSOded Gabbay #define mmSTLB_BASE 0x7FFCC12000ull 1153*e65e175bSOded Gabbay #define STLB_MAX_OFFSET 0x8800 1154*e65e175bSOded Gabbay #define STLB_SECTION 0x1000 1155*e65e175bSOded Gabbay #define mmPCIE_MSI_BASE 0x7FFCC13000ull 1156*e65e175bSOded Gabbay #define PCIE_MSI_MAX_OFFSET 0x8000 1157*e65e175bSOded Gabbay #define PCIE_MSI_SECTION 0x2D000 1158*e65e175bSOded Gabbay #define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull 1159*e65e175bSOded Gabbay #define PSOC_I2C_M0_MAX_OFFSET 0x1000 1160*e65e175bSOded Gabbay #define PSOC_I2C_M0_SECTION 0x1000 1161*e65e175bSOded Gabbay #define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull 1162*e65e175bSOded Gabbay #define PSOC_I2C_M1_MAX_OFFSET 0x1000 1163*e65e175bSOded Gabbay #define PSOC_I2C_M1_SECTION 0x1000 1164*e65e175bSOded Gabbay #define mmPSOC_I2C_S_BASE 0x7FFCC42000ull 1165*e65e175bSOded Gabbay #define PSOC_I2C_S_MAX_OFFSET 0x1000 1166*e65e175bSOded Gabbay #define PSOC_I2C_S_SECTION 0x1000 1167*e65e175bSOded Gabbay #define mmPSOC_SPI_BASE 0x7FFCC43000ull 1168*e65e175bSOded Gabbay #define PSOC_SPI_MAX_OFFSET 0x1000 1169*e65e175bSOded Gabbay #define PSOC_SPI_SECTION 0x2000 1170*e65e175bSOded Gabbay #define mmPSOC_UART_0_BASE 0x7FFCC45000ull 1171*e65e175bSOded Gabbay #define PSOC_UART_0_MAX_OFFSET 0x1000 1172*e65e175bSOded Gabbay #define PSOC_UART_0_SECTION 0x1000 1173*e65e175bSOded Gabbay #define mmPSOC_UART_1_BASE 0x7FFCC46000ull 1174*e65e175bSOded Gabbay #define PSOC_UART_1_MAX_OFFSET 0x1000 1175*e65e175bSOded Gabbay #define PSOC_UART_1_SECTION 0x1000 1176*e65e175bSOded Gabbay #define mmPSOC_TIMER_BASE 0x7FFCC47000ull 1177*e65e175bSOded Gabbay #define PSOC_TIMER_MAX_OFFSET 0x1000 1178*e65e175bSOded Gabbay #define PSOC_TIMER_SECTION 0x1000 1179*e65e175bSOded Gabbay #define mmPSOC_WDOG_BASE 0x7FFCC48000ull 1180*e65e175bSOded Gabbay #define PSOC_WDOG_MAX_OFFSET 0x1000 1181*e65e175bSOded Gabbay #define PSOC_WDOG_SECTION 0x1000 1182*e65e175bSOded Gabbay #define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull 1183*e65e175bSOded Gabbay #define PSOC_TIMESTAMP_MAX_OFFSET 0x1000 1184*e65e175bSOded Gabbay #define PSOC_TIMESTAMP_SECTION 0x1000 1185*e65e175bSOded Gabbay #define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull 1186*e65e175bSOded Gabbay #define PSOC_EFUSE_MAX_OFFSET 0x3040 1187*e65e175bSOded Gabbay #define PSOC_EFUSE_SECTION 0x1000 1188*e65e175bSOded Gabbay #define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull 1189*e65e175bSOded Gabbay #define PSOC_GLOBAL_CONF_MAX_OFFSET 0xCD80 1190*e65e175bSOded Gabbay #define PSOC_GLOBAL_CONF_SECTION 0x1000 1191*e65e175bSOded Gabbay #define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull 1192*e65e175bSOded Gabbay #define PSOC_GPIO0_MAX_OFFSET 0x1000 1193*e65e175bSOded Gabbay #define PSOC_GPIO0_SECTION 0x1000 1194*e65e175bSOded Gabbay #define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull 1195*e65e175bSOded Gabbay #define PSOC_GPIO1_MAX_OFFSET 0x1000 1196*e65e175bSOded Gabbay #define PSOC_GPIO1_SECTION 0x1000 1197*e65e175bSOded Gabbay #define mmPSOC_BTL_BASE 0x7FFCC4E000ull 1198*e65e175bSOded Gabbay #define PSOC_BTL_MAX_OFFSET 0x1480 1199*e65e175bSOded Gabbay #define PSOC_BTL_SECTION 0x1000 1200*e65e175bSOded Gabbay #define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull 1201*e65e175bSOded Gabbay #define PSOC_CS_TRACE_MAX_OFFSET 0x1680 1202*e65e175bSOded Gabbay #define PSOC_CS_TRACE_SECTION 0x1000 1203*e65e175bSOded Gabbay #define mmPSOC_GPIO2_BASE 0x7FFCC50000ull 1204*e65e175bSOded Gabbay #define PSOC_GPIO2_MAX_OFFSET 0x1000 1205*e65e175bSOded Gabbay #define PSOC_GPIO2_SECTION 0x1000 1206*e65e175bSOded Gabbay #define mmPSOC_GPIO3_BASE 0x7FFCC51000ull 1207*e65e175bSOded Gabbay #define PSOC_GPIO3_MAX_OFFSET 0x1000 1208*e65e175bSOded Gabbay #define PSOC_GPIO3_SECTION 0x1000 1209*e65e175bSOded Gabbay #define mmPSOC_GPIO4_BASE 0x7FFCC52000ull 1210*e65e175bSOded Gabbay #define PSOC_GPIO4_MAX_OFFSET 0x1000 1211*e65e175bSOded Gabbay #define PSOC_GPIO4_SECTION 0x1000 1212*e65e175bSOded Gabbay #define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull 1213*e65e175bSOded Gabbay #define PSOC_DFT_EFUSE_MAX_OFFSET 0x3040 1214*e65e175bSOded Gabbay #define PSOC_DFT_EFUSE_SECTION 0x1000 1215*e65e175bSOded Gabbay #define mmPSOC_RPM_0_BASE 0x7FFCC54000ull 1216*e65e175bSOded Gabbay #define PSOC_RPM_0_MAX_OFFSET 0x8800 1217*e65e175bSOded Gabbay #define PSOC_RPM_0_SECTION 0x1000 1218*e65e175bSOded Gabbay #define mmPSOC_RPM_1_BASE 0x7FFCC55000ull 1219*e65e175bSOded Gabbay #define PSOC_RPM_1_MAX_OFFSET 0x8800 1220*e65e175bSOded Gabbay #define PSOC_RPM_1_SECTION 0x1000 1221*e65e175bSOded Gabbay #define mmPSOC_RPM_2_BASE 0x7FFCC56000ull 1222*e65e175bSOded Gabbay #define PSOC_RPM_2_MAX_OFFSET 0x8800 1223*e65e175bSOded Gabbay #define PSOC_RPM_2_SECTION 0x1000 1224*e65e175bSOded Gabbay #define mmPSOC_RPM_3_BASE 0x7FFCC57000ull 1225*e65e175bSOded Gabbay #define PSOC_RPM_3_MAX_OFFSET 0x8800 1226*e65e175bSOded Gabbay #define PSOC_RPM_3_SECTION 0x19000 1227*e65e175bSOded Gabbay #define mmPSOC_CPU_PLL_BASE 0x7FFCC70000ull 1228*e65e175bSOded Gabbay #define PSOC_CPU_PLL_MAX_OFFSET 0x5200 1229*e65e175bSOded Gabbay #define PSOC_CPU_PLL_SECTION 0x1000 1230*e65e175bSOded Gabbay #define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull 1231*e65e175bSOded Gabbay #define PSOC_MME_PLL_MAX_OFFSET 0x5200 1232*e65e175bSOded Gabbay #define PSOC_MME_PLL_SECTION 0x1000 1233*e65e175bSOded Gabbay #define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull 1234*e65e175bSOded Gabbay #define PSOC_PCI_PLL_MAX_OFFSET 0x5200 1235*e65e175bSOded Gabbay #define PSOC_PCI_PLL_SECTION 0x1000 1236*e65e175bSOded Gabbay #define mmPSOC_TPC_PLL_BASE 0x7FFCC73000ull 1237*e65e175bSOded Gabbay #define PSOC_TPC_PLL_MAX_OFFSET 0x5200 1238*e65e175bSOded Gabbay #define PSOC_TPC_PLL_SECTION 0x1000 1239*e65e175bSOded Gabbay #define mmPSOC_HBM_PLL_BASE 0x7FFCC74000ull 1240*e65e175bSOded Gabbay #define PSOC_HBM_PLL_MAX_OFFSET 0x5200 1241*e65e175bSOded Gabbay #define PSOC_HBM_PLL_SECTION 0x1000 1242*e65e175bSOded Gabbay #define mmPSOC_PM_BASE 0x7FFCC75000ull 1243*e65e175bSOded Gabbay #define PSOC_PM_MAX_OFFSET 0x1F00 1244*e65e175bSOded Gabbay #define PSOC_PM_SECTION 0x1000 1245*e65e175bSOded Gabbay #define mmPSOC_TS_BASE 0x7FFCC76000ull 1246*e65e175bSOded Gabbay #define PSOC_TS_MAX_OFFSET 0xE640 1247*e65e175bSOded Gabbay #define PSOC_TS_SECTION 0x2000 1248*e65e175bSOded Gabbay #define mmPSOC_PWM0_BASE 0x7FFCC78000ull 1249*e65e175bSOded Gabbay #define PSOC_PWM0_MAX_OFFSET 0x5800 1250*e65e175bSOded Gabbay #define PSOC_PWM0_SECTION 0x1000 1251*e65e175bSOded Gabbay #define mmPSOC_PWM1_BASE 0x7FFCC79000ull 1252*e65e175bSOded Gabbay #define PSOC_PWM1_MAX_OFFSET 0x5800 1253*e65e175bSOded Gabbay #define PSOC_PWM1_SECTION 0x1000 1254*e65e175bSOded Gabbay #define mmPSOC_PWM2_BASE 0x7FFCC7A000ull 1255*e65e175bSOded Gabbay #define PSOC_PWM2_MAX_OFFSET 0x5800 1256*e65e175bSOded Gabbay #define PSOC_PWM2_SECTION 0x1000 1257*e65e175bSOded Gabbay #define mmPSOC_PWM3_BASE 0x7FFCC7B000ull 1258*e65e175bSOded Gabbay #define PSOC_PWM3_MAX_OFFSET 0x5800 1259*e65e175bSOded Gabbay #define PSOC_PWM3_SECTION 0x1000 1260*e65e175bSOded Gabbay #define mmPSOC_GPIO5_BASE 0x7FFCC7C000ull 1261*e65e175bSOded Gabbay #define PSOC_GPIO5_MAX_OFFSET 0x1000 1262*e65e175bSOded Gabbay #define PSOC_GPIO5_SECTION 0x1000 1263*e65e175bSOded Gabbay #define mmPSOC_GPIO6_BASE 0x7FFCC7D000ull 1264*e65e175bSOded Gabbay #define PSOC_GPIO6_MAX_OFFSET 0x1000 1265*e65e175bSOded Gabbay #define PSOC_GPIO6_SECTION 0x3000 1266*e65e175bSOded Gabbay #define mmPCIE_PMA_0_BASE 0x7FFCC80000ull 1267*e65e175bSOded Gabbay #define PCIE_PMA_0_MAX_OFFSET 0x10003 1268*e65e175bSOded Gabbay #define PCIE_PMA_0_SECTION 0x10000 1269*e65e175bSOded Gabbay #define mmPCIE_PMA_1_BASE 0x7FFCC90000ull 1270*e65e175bSOded Gabbay #define PCIE_PMA_1_MAX_OFFSET 0x10003 1271*e65e175bSOded Gabbay #define PCIE_PMA_1_SECTION 0x10000 1272*e65e175bSOded Gabbay #define mmPCIE_PMA_2_BASE 0x7FFCCA0000ull 1273*e65e175bSOded Gabbay #define PCIE_PMA_2_MAX_OFFSET 0x10003 1274*e65e175bSOded Gabbay #define PCIE_PMA_2_SECTION 0x10000 1275*e65e175bSOded Gabbay #define mmPCIE_PMA_3_BASE 0x7FFCCB0000ull 1276*e65e175bSOded Gabbay #define PCIE_PMA_3_MAX_OFFSET 0x10003 1277*e65e175bSOded Gabbay #define PCIE_PMA_3_SECTION 0x10000 1278*e65e175bSOded Gabbay #define mmNIC0_MAC_CH0_BASE 0x7FFCCC0000ull 1279*e65e175bSOded Gabbay #define NIC0_MAC_CH0_MAX_OFFSET 0x8400 1280*e65e175bSOded Gabbay #define NIC0_MAC_CH0_SECTION 0x1000 1281*e65e175bSOded Gabbay #define mmNIC0_MAC_CH1_BASE 0x7FFCCC1000ull 1282*e65e175bSOded Gabbay #define NIC0_MAC_CH1_MAX_OFFSET 0x8400 1283*e65e175bSOded Gabbay #define NIC0_MAC_CH1_SECTION 0x1000 1284*e65e175bSOded Gabbay #define mmNIC0_MAC_CH2_BASE 0x7FFCCC2000ull 1285*e65e175bSOded Gabbay #define NIC0_MAC_CH2_MAX_OFFSET 0x8400 1286*e65e175bSOded Gabbay #define NIC0_MAC_CH2_SECTION 0x1000 1287*e65e175bSOded Gabbay #define mmNIC0_MAC_CH3_BASE 0x7FFCCC3000ull 1288*e65e175bSOded Gabbay #define NIC0_MAC_CH3_MAX_OFFSET 0x8400 1289*e65e175bSOded Gabbay #define NIC0_MAC_CH3_SECTION 0x1000 1290*e65e175bSOded Gabbay #define mmNIC0_STAT_BASE 0x7FFCCC4000ull 1291*e65e175bSOded Gabbay #define NIC0_STAT_MAX_OFFSET 0x4D00 1292*e65e175bSOded Gabbay #define NIC0_STAT_SECTION 0x1000 1293*e65e175bSOded Gabbay #define mmNIC0_MAC_XPCS91_BASE 0x7FFCCC5000ull 1294*e65e175bSOded Gabbay #define NIC0_MAC_XPCS91_MAX_OFFSET 0x2380 1295*e65e175bSOded Gabbay #define NIC0_MAC_XPCS91_SECTION 0x3000 1296*e65e175bSOded Gabbay #define mmNIC0_MAC_CORE_BASE 0x7FFCCC8000ull 1297*e65e175bSOded Gabbay #define NIC0_MAC_CORE_MAX_OFFSET 0x5400 1298*e65e175bSOded Gabbay #define NIC0_MAC_CORE_SECTION 0x1000 1299*e65e175bSOded Gabbay #define mmNIC0_MAC_AUX_BASE 0x7FFCCC9000ull 1300*e65e175bSOded Gabbay #define NIC0_MAC_AUX_MAX_OFFSET 0x3000 1301*e65e175bSOded Gabbay #define NIC0_MAC_AUX_SECTION 0xF000 1302*e65e175bSOded Gabbay #define mmNIC0_PHY_BASE 0x7FFCCD8000ull 1303*e65e175bSOded Gabbay #define NIC0_PHY_MAX_OFFSET 0x3400 1304*e65e175bSOded Gabbay #define NIC0_PHY_SECTION 0x8000 1305*e65e175bSOded Gabbay #define mmNIC0_QM0_BASE 0x7FFCCE0000ull 1306*e65e175bSOded Gabbay #define NIC0_QM0_MAX_OFFSET 0xD040 1307*e65e175bSOded Gabbay #define NIC0_QM0_SECTION 0x2000 1308*e65e175bSOded Gabbay #define mmNIC0_QM1_BASE 0x7FFCCE2000ull 1309*e65e175bSOded Gabbay #define NIC0_QM1_MAX_OFFSET 0xD040 1310*e65e175bSOded Gabbay #define NIC0_QM1_SECTION 0x2000 1311*e65e175bSOded Gabbay #define mmNIC0_QPC0_BASE 0x7FFCCE4000ull 1312*e65e175bSOded Gabbay #define NIC0_QPC0_MAX_OFFSET 0x7140 1313*e65e175bSOded Gabbay #define NIC0_QPC0_SECTION 0x1000 1314*e65e175bSOded Gabbay #define mmNIC0_QPC1_BASE 0x7FFCCE5000ull 1315*e65e175bSOded Gabbay #define NIC0_QPC1_MAX_OFFSET 0x7140 1316*e65e175bSOded Gabbay #define NIC0_QPC1_SECTION 0x3000 1317*e65e175bSOded Gabbay #define mmNIC0_RXB_BASE 0x7FFCCE8000ull 1318*e65e175bSOded Gabbay #define NIC0_RXB_MAX_OFFSET 0x6040 1319*e65e175bSOded Gabbay #define NIC0_RXB_SECTION 0x1000 1320*e65e175bSOded Gabbay #define mmNIC0_RXE0_BASE 0x7FFCCE9000ull 1321*e65e175bSOded Gabbay #define NIC0_RXE0_MAX_OFFSET 0x2FC0 1322*e65e175bSOded Gabbay #define NIC0_RXE0_SECTION 0x1000 1323*e65e175bSOded Gabbay #define mmNIC0_RXE1_BASE 0x7FFCCEA000ull 1324*e65e175bSOded Gabbay #define NIC0_RXE1_MAX_OFFSET 0x2FC0 1325*e65e175bSOded Gabbay #define NIC0_RXE1_SECTION 0x1000 1326*e65e175bSOded Gabbay #define mmNIC0_RX_GW_BASE 0x7FFCCEB000ull 1327*e65e175bSOded Gabbay #define NIC0_RX_GW_MAX_OFFSET 0x4540 1328*e65e175bSOded Gabbay #define NIC0_RX_GW_SECTION 0x5000 1329*e65e175bSOded Gabbay #define mmNIC0_TXS0_BASE 0x7FFCCF0000ull 1330*e65e175bSOded Gabbay #define NIC0_TXS0_MAX_OFFSET 0x19C0 1331*e65e175bSOded Gabbay #define NIC0_TXS0_SECTION 0x1000 1332*e65e175bSOded Gabbay #define mmNIC0_TXS1_BASE 0x7FFCCF1000ull 1333*e65e175bSOded Gabbay #define NIC0_TXS1_MAX_OFFSET 0x19C0 1334*e65e175bSOded Gabbay #define NIC0_TXS1_SECTION 0x1000 1335*e65e175bSOded Gabbay #define mmNIC0_TXE0_BASE 0x7FFCCF2000ull 1336*e65e175bSOded Gabbay #define NIC0_TXE0_MAX_OFFSET 0x2040 1337*e65e175bSOded Gabbay #define NIC0_TXE0_SECTION 0x1000 1338*e65e175bSOded Gabbay #define mmNIC0_TXE1_BASE 0x7FFCCF3000ull 1339*e65e175bSOded Gabbay #define NIC0_TXE1_MAX_OFFSET 0x2040 1340*e65e175bSOded Gabbay #define NIC0_TXE1_SECTION 0x1000 1341*e65e175bSOded Gabbay #define mmNIC0_TXB_BASE 0x7FFCCF4000ull 1342*e65e175bSOded Gabbay #define NIC0_TXB_MAX_OFFSET 0xD400 1343*e65e175bSOded Gabbay #define NIC0_TXB_SECTION 0x1000 1344*e65e175bSOded Gabbay #define mmNIC0_TMR_BASE 0x7FFCCF5000ull 1345*e65e175bSOded Gabbay #define NIC0_TMR_MAX_OFFSET 0x1600 1346*e65e175bSOded Gabbay #define NIC0_TMR_SECTION 0x1000 1347*e65e175bSOded Gabbay #define mmNIC0_TX_GW_BASE 0x7FFCCF6000ull 1348*e65e175bSOded Gabbay #define NIC0_TX_GW_MAX_OFFSET 0x1400 1349*e65e175bSOded Gabbay #define NIC0_TX_GW_SECTION 0x2000 1350*e65e175bSOded Gabbay #define mmNIC0_TS_BASE 0x7FFCCF8000ull 1351*e65e175bSOded Gabbay #define NIC0_TS_MAX_OFFSET 0xE640 1352*e65e175bSOded Gabbay #define NIC0_TS_SECTION 0x1000 1353*e65e175bSOded Gabbay #define mmNIC0_PLL_BASE 0x7FFCCF9000ull 1354*e65e175bSOded Gabbay #define NIC0_PLL_MAX_OFFSET 0x5200 1355*e65e175bSOded Gabbay #define NIC0_PLL_SECTION 0x1000 1356*e65e175bSOded Gabbay #define mmNIC0_PM_BASE 0x7FFCCFA000ull 1357*e65e175bSOded Gabbay #define NIC0_PM_MAX_OFFSET 0x1F00 1358*e65e175bSOded Gabbay #define NIC0_PM_SECTION 0x6000 1359*e65e175bSOded Gabbay #define mmNIC1_MAC_CH0_BASE 0x7FFCD00000ull 1360*e65e175bSOded Gabbay #define NIC1_MAC_CH0_MAX_OFFSET 0x8400 1361*e65e175bSOded Gabbay #define NIC1_MAC_CH0_SECTION 0x1000 1362*e65e175bSOded Gabbay #define mmNIC1_MAC_CH1_BASE 0x7FFCD01000ull 1363*e65e175bSOded Gabbay #define NIC1_MAC_CH1_MAX_OFFSET 0x8400 1364*e65e175bSOded Gabbay #define NIC1_MAC_CH1_SECTION 0x1000 1365*e65e175bSOded Gabbay #define mmNIC1_MAC_CH2_BASE 0x7FFCD02000ull 1366*e65e175bSOded Gabbay #define NIC1_MAC_CH2_MAX_OFFSET 0x8400 1367*e65e175bSOded Gabbay #define NIC1_MAC_CH2_SECTION 0x1000 1368*e65e175bSOded Gabbay #define mmNIC1_MAC_CH3_BASE 0x7FFCD03000ull 1369*e65e175bSOded Gabbay #define NIC1_MAC_CH3_MAX_OFFSET 0x8400 1370*e65e175bSOded Gabbay #define NIC1_MAC_CH3_SECTION 0x1000 1371*e65e175bSOded Gabbay #define mmNIC1_STAT_BASE 0x7FFCD04000ull 1372*e65e175bSOded Gabbay #define NIC1_STAT_MAX_OFFSET 0x4D00 1373*e65e175bSOded Gabbay #define NIC1_STAT_SECTION 0x1000 1374*e65e175bSOded Gabbay #define mmNIC1_MAC_XPCS91_BASE 0x7FFCD05000ull 1375*e65e175bSOded Gabbay #define NIC1_MAC_XPCS91_MAX_OFFSET 0x2380 1376*e65e175bSOded Gabbay #define NIC1_MAC_XPCS91_SECTION 0x3000 1377*e65e175bSOded Gabbay #define mmNIC1_MAC_CORE_BASE 0x7FFCD08000ull 1378*e65e175bSOded Gabbay #define NIC1_MAC_CORE_MAX_OFFSET 0x5400 1379*e65e175bSOded Gabbay #define NIC1_MAC_CORE_SECTION 0x1000 1380*e65e175bSOded Gabbay #define mmNIC1_MAC_AUX_BASE 0x7FFCD09000ull 1381*e65e175bSOded Gabbay #define NIC1_MAC_AUX_MAX_OFFSET 0x3000 1382*e65e175bSOded Gabbay #define NIC1_MAC_AUX_SECTION 0xF000 1383*e65e175bSOded Gabbay #define mmNIC1_PHY_BASE 0x7FFCD18000ull 1384*e65e175bSOded Gabbay #define NIC1_PHY_MAX_OFFSET 0x3400 1385*e65e175bSOded Gabbay #define NIC1_PHY_SECTION 0x8000 1386*e65e175bSOded Gabbay #define mmNIC1_QM0_BASE 0x7FFCD20000ull 1387*e65e175bSOded Gabbay #define NIC1_QM0_MAX_OFFSET 0xD040 1388*e65e175bSOded Gabbay #define NIC1_QM0_SECTION 0x2000 1389*e65e175bSOded Gabbay #define mmNIC1_QM1_BASE 0x7FFCD22000ull 1390*e65e175bSOded Gabbay #define NIC1_QM1_MAX_OFFSET 0xD040 1391*e65e175bSOded Gabbay #define NIC1_QM1_SECTION 0x2000 1392*e65e175bSOded Gabbay #define mmNIC1_QPC0_BASE 0x7FFCD24000ull 1393*e65e175bSOded Gabbay #define NIC1_QPC0_MAX_OFFSET 0x7140 1394*e65e175bSOded Gabbay #define NIC1_QPC0_SECTION 0x1000 1395*e65e175bSOded Gabbay #define mmNIC1_QPC1_BASE 0x7FFCD25000ull 1396*e65e175bSOded Gabbay #define NIC1_QPC1_MAX_OFFSET 0x7140 1397*e65e175bSOded Gabbay #define NIC1_QPC1_SECTION 0x3000 1398*e65e175bSOded Gabbay #define mmNIC1_RXB_BASE 0x7FFCD28000ull 1399*e65e175bSOded Gabbay #define NIC1_RXB_MAX_OFFSET 0x6040 1400*e65e175bSOded Gabbay #define NIC1_RXB_SECTION 0x1000 1401*e65e175bSOded Gabbay #define mmNIC1_RXE0_BASE 0x7FFCD29000ull 1402*e65e175bSOded Gabbay #define NIC1_RXE0_MAX_OFFSET 0x2FC0 1403*e65e175bSOded Gabbay #define NIC1_RXE0_SECTION 0x1000 1404*e65e175bSOded Gabbay #define mmNIC1_RXE1_BASE 0x7FFCD2A000ull 1405*e65e175bSOded Gabbay #define NIC1_RXE1_MAX_OFFSET 0x2FC0 1406*e65e175bSOded Gabbay #define NIC1_RXE1_SECTION 0x1000 1407*e65e175bSOded Gabbay #define mmNIC1_RX_GW_BASE 0x7FFCD2B000ull 1408*e65e175bSOded Gabbay #define NIC1_RX_GW_MAX_OFFSET 0x4540 1409*e65e175bSOded Gabbay #define NIC1_RX_GW_SECTION 0x5000 1410*e65e175bSOded Gabbay #define mmNIC1_TXS0_BASE 0x7FFCD30000ull 1411*e65e175bSOded Gabbay #define NIC1_TXS0_MAX_OFFSET 0x19C0 1412*e65e175bSOded Gabbay #define NIC1_TXS0_SECTION 0x1000 1413*e65e175bSOded Gabbay #define mmNIC1_TXS1_BASE 0x7FFCD31000ull 1414*e65e175bSOded Gabbay #define NIC1_TXS1_MAX_OFFSET 0x19C0 1415*e65e175bSOded Gabbay #define NIC1_TXS1_SECTION 0x1000 1416*e65e175bSOded Gabbay #define mmNIC1_TXE0_BASE 0x7FFCD32000ull 1417*e65e175bSOded Gabbay #define NIC1_TXE0_MAX_OFFSET 0x2040 1418*e65e175bSOded Gabbay #define NIC1_TXE0_SECTION 0x1000 1419*e65e175bSOded Gabbay #define mmNIC1_TXE1_BASE 0x7FFCD33000ull 1420*e65e175bSOded Gabbay #define NIC1_TXE1_MAX_OFFSET 0x2040 1421*e65e175bSOded Gabbay #define NIC1_TXE1_SECTION 0x1000 1422*e65e175bSOded Gabbay #define mmNIC1_TXB_BASE 0x7FFCD34000ull 1423*e65e175bSOded Gabbay #define NIC1_TXB_MAX_OFFSET 0xD400 1424*e65e175bSOded Gabbay #define NIC1_TXB_SECTION 0x1000 1425*e65e175bSOded Gabbay #define mmNIC1_TMR_BASE 0x7FFCD35000ull 1426*e65e175bSOded Gabbay #define NIC1_TMR_MAX_OFFSET 0x1600 1427*e65e175bSOded Gabbay #define NIC1_TMR_SECTION 0x1000 1428*e65e175bSOded Gabbay #define mmNIC1_TX_GW_BASE 0x7FFCD36000ull 1429*e65e175bSOded Gabbay #define NIC1_TX_GW_MAX_OFFSET 0x1400 1430*e65e175bSOded Gabbay #define NIC1_TX_GW_SECTION 0x2000 1431*e65e175bSOded Gabbay #define mmNIC1_TS_BASE 0x7FFCD38000ull 1432*e65e175bSOded Gabbay #define NIC1_TS_MAX_OFFSET 0xE640 1433*e65e175bSOded Gabbay #define NIC1_TS_SECTION 0x1000 1434*e65e175bSOded Gabbay #define mmNIC1_PLL_BASE 0x7FFCD39000ull 1435*e65e175bSOded Gabbay #define NIC1_PLL_MAX_OFFSET 0x5200 1436*e65e175bSOded Gabbay #define NIC1_PLL_SECTION 0x1000 1437*e65e175bSOded Gabbay #define mmNIC1_PM_BASE 0x7FFCD3A000ull 1438*e65e175bSOded Gabbay #define NIC1_PM_MAX_OFFSET 0x1F00 1439*e65e175bSOded Gabbay #define NIC1_PM_SECTION 0x6000 1440*e65e175bSOded Gabbay #define mmNIC2_MAC_CH0_BASE 0x7FFCD40000ull 1441*e65e175bSOded Gabbay #define NIC2_MAC_CH0_MAX_OFFSET 0x8400 1442*e65e175bSOded Gabbay #define NIC2_MAC_CH0_SECTION 0x1000 1443*e65e175bSOded Gabbay #define mmNIC2_MAC_CH1_BASE 0x7FFCD41000ull 1444*e65e175bSOded Gabbay #define NIC2_MAC_CH1_MAX_OFFSET 0x8400 1445*e65e175bSOded Gabbay #define NIC2_MAC_CH1_SECTION 0x1000 1446*e65e175bSOded Gabbay #define mmNIC2_MAC_CH2_BASE 0x7FFCD42000ull 1447*e65e175bSOded Gabbay #define NIC2_MAC_CH2_MAX_OFFSET 0x8400 1448*e65e175bSOded Gabbay #define NIC2_MAC_CH2_SECTION 0x1000 1449*e65e175bSOded Gabbay #define mmNIC2_MAC_CH3_BASE 0x7FFCD43000ull 1450*e65e175bSOded Gabbay #define NIC2_MAC_CH3_MAX_OFFSET 0x8400 1451*e65e175bSOded Gabbay #define NIC2_MAC_CH3_SECTION 0x1000 1452*e65e175bSOded Gabbay #define mmNIC2_STAT_BASE 0x7FFCD44000ull 1453*e65e175bSOded Gabbay #define NIC2_STAT_MAX_OFFSET 0x4D00 1454*e65e175bSOded Gabbay #define NIC2_STAT_SECTION 0x1000 1455*e65e175bSOded Gabbay #define mmNIC2_MAC_XPCS91_BASE 0x7FFCD45000ull 1456*e65e175bSOded Gabbay #define NIC2_MAC_XPCS91_MAX_OFFSET 0x2380 1457*e65e175bSOded Gabbay #define NIC2_MAC_XPCS91_SECTION 0x3000 1458*e65e175bSOded Gabbay #define mmNIC2_MAC_CORE_BASE 0x7FFCD48000ull 1459*e65e175bSOded Gabbay #define NIC2_MAC_CORE_MAX_OFFSET 0x5400 1460*e65e175bSOded Gabbay #define NIC2_MAC_CORE_SECTION 0x1000 1461*e65e175bSOded Gabbay #define mmNIC2_MAC_AUX_BASE 0x7FFCD49000ull 1462*e65e175bSOded Gabbay #define NIC2_MAC_AUX_MAX_OFFSET 0x3000 1463*e65e175bSOded Gabbay #define NIC2_MAC_AUX_SECTION 0xF000 1464*e65e175bSOded Gabbay #define mmNIC2_PHY_BASE 0x7FFCD58000ull 1465*e65e175bSOded Gabbay #define NIC2_PHY_MAX_OFFSET 0x3400 1466*e65e175bSOded Gabbay #define NIC2_PHY_SECTION 0x8000 1467*e65e175bSOded Gabbay #define mmNIC2_QM0_BASE 0x7FFCD60000ull 1468*e65e175bSOded Gabbay #define NIC2_QM0_MAX_OFFSET 0xD040 1469*e65e175bSOded Gabbay #define NIC2_QM0_SECTION 0x2000 1470*e65e175bSOded Gabbay #define mmNIC2_QM1_BASE 0x7FFCD62000ull 1471*e65e175bSOded Gabbay #define NIC2_QM1_MAX_OFFSET 0xD040 1472*e65e175bSOded Gabbay #define NIC2_QM1_SECTION 0x2000 1473*e65e175bSOded Gabbay #define mmNIC2_QPC0_BASE 0x7FFCD64000ull 1474*e65e175bSOded Gabbay #define NIC2_QPC0_MAX_OFFSET 0x7140 1475*e65e175bSOded Gabbay #define NIC2_QPC0_SECTION 0x1000 1476*e65e175bSOded Gabbay #define mmNIC2_QPC1_BASE 0x7FFCD65000ull 1477*e65e175bSOded Gabbay #define NIC2_QPC1_MAX_OFFSET 0x7140 1478*e65e175bSOded Gabbay #define NIC2_QPC1_SECTION 0x3000 1479*e65e175bSOded Gabbay #define mmNIC2_RXB_BASE 0x7FFCD68000ull 1480*e65e175bSOded Gabbay #define NIC2_RXB_MAX_OFFSET 0x6040 1481*e65e175bSOded Gabbay #define NIC2_RXB_SECTION 0x1000 1482*e65e175bSOded Gabbay #define mmNIC2_RXE0_BASE 0x7FFCD69000ull 1483*e65e175bSOded Gabbay #define NIC2_RXE0_MAX_OFFSET 0x2FC0 1484*e65e175bSOded Gabbay #define NIC2_RXE0_SECTION 0x1000 1485*e65e175bSOded Gabbay #define mmNIC2_RXE1_BASE 0x7FFCD6A000ull 1486*e65e175bSOded Gabbay #define NIC2_RXE1_MAX_OFFSET 0x2FC0 1487*e65e175bSOded Gabbay #define NIC2_RXE1_SECTION 0x1000 1488*e65e175bSOded Gabbay #define mmNIC2_RX_GW_BASE 0x7FFCD6B000ull 1489*e65e175bSOded Gabbay #define NIC2_RX_GW_MAX_OFFSET 0x4540 1490*e65e175bSOded Gabbay #define NIC2_RX_GW_SECTION 0x5000 1491*e65e175bSOded Gabbay #define mmNIC2_TXS0_BASE 0x7FFCD70000ull 1492*e65e175bSOded Gabbay #define NIC2_TXS0_MAX_OFFSET 0x19C0 1493*e65e175bSOded Gabbay #define NIC2_TXS0_SECTION 0x1000 1494*e65e175bSOded Gabbay #define mmNIC2_TXS1_BASE 0x7FFCD71000ull 1495*e65e175bSOded Gabbay #define NIC2_TXS1_MAX_OFFSET 0x19C0 1496*e65e175bSOded Gabbay #define NIC2_TXS1_SECTION 0x1000 1497*e65e175bSOded Gabbay #define mmNIC2_TXE0_BASE 0x7FFCD72000ull 1498*e65e175bSOded Gabbay #define NIC2_TXE0_MAX_OFFSET 0x2040 1499*e65e175bSOded Gabbay #define NIC2_TXE0_SECTION 0x1000 1500*e65e175bSOded Gabbay #define mmNIC2_TXE1_BASE 0x7FFCD73000ull 1501*e65e175bSOded Gabbay #define NIC2_TXE1_MAX_OFFSET 0x2040 1502*e65e175bSOded Gabbay #define NIC2_TXE1_SECTION 0x1000 1503*e65e175bSOded Gabbay #define mmNIC2_TXB_BASE 0x7FFCD74000ull 1504*e65e175bSOded Gabbay #define NIC2_TXB_MAX_OFFSET 0xD400 1505*e65e175bSOded Gabbay #define NIC2_TXB_SECTION 0x1000 1506*e65e175bSOded Gabbay #define mmNIC2_TMR_BASE 0x7FFCD75000ull 1507*e65e175bSOded Gabbay #define NIC2_TMR_MAX_OFFSET 0x1600 1508*e65e175bSOded Gabbay #define NIC2_TMR_SECTION 0x1000 1509*e65e175bSOded Gabbay #define mmNIC2_TX_GW_BASE 0x7FFCD76000ull 1510*e65e175bSOded Gabbay #define NIC2_TX_GW_MAX_OFFSET 0x1400 1511*e65e175bSOded Gabbay #define NIC2_TX_GW_SECTION 0x2000 1512*e65e175bSOded Gabbay #define mmNIC2_HBM_PLL_BASE 0x7FFCD78000ull 1513*e65e175bSOded Gabbay #define NIC2_HBM_PLL_MAX_OFFSET 0x5200 1514*e65e175bSOded Gabbay #define NIC2_HBM_PLL_SECTION 0x1000 1515*e65e175bSOded Gabbay #define mmNIC2_MME_PLL_BASE 0x7FFCD79000ull 1516*e65e175bSOded Gabbay #define NIC2_MME_PLL_MAX_OFFSET 0x5200 1517*e65e175bSOded Gabbay #define NIC2_MME_PLL_SECTION 0x1000 1518*e65e175bSOded Gabbay #define mmNIC2_TPC_PLL_BASE 0x7FFCD7A000ull 1519*e65e175bSOded Gabbay #define NIC2_TPC_PLL_MAX_OFFSET 0x5200 1520*e65e175bSOded Gabbay #define NIC2_TPC_PLL_SECTION 0x6000 1521*e65e175bSOded Gabbay #define mmNIC3_MAC_CH0_BASE 0x7FFCD80000ull 1522*e65e175bSOded Gabbay #define NIC3_MAC_CH0_MAX_OFFSET 0x8400 1523*e65e175bSOded Gabbay #define NIC3_MAC_CH0_SECTION 0x1000 1524*e65e175bSOded Gabbay #define mmNIC3_MAC_CH1_BASE 0x7FFCD81000ull 1525*e65e175bSOded Gabbay #define NIC3_MAC_CH1_MAX_OFFSET 0x8400 1526*e65e175bSOded Gabbay #define NIC3_MAC_CH1_SECTION 0x1000 1527*e65e175bSOded Gabbay #define mmNIC3_MAC_CH2_BASE 0x7FFCD82000ull 1528*e65e175bSOded Gabbay #define NIC3_MAC_CH2_MAX_OFFSET 0x8400 1529*e65e175bSOded Gabbay #define NIC3_MAC_CH2_SECTION 0x1000 1530*e65e175bSOded Gabbay #define mmNIC3_MAC_CH3_BASE 0x7FFCD83000ull 1531*e65e175bSOded Gabbay #define NIC3_MAC_CH3_MAX_OFFSET 0x8400 1532*e65e175bSOded Gabbay #define NIC3_MAC_CH3_SECTION 0x1000 1533*e65e175bSOded Gabbay #define mmNIC3_STAT_BASE 0x7FFCD84000ull 1534*e65e175bSOded Gabbay #define NIC3_STAT_MAX_OFFSET 0x4D00 1535*e65e175bSOded Gabbay #define NIC3_STAT_SECTION 0x1000 1536*e65e175bSOded Gabbay #define mmNIC3_MAC_XPCS91_BASE 0x7FFCD85000ull 1537*e65e175bSOded Gabbay #define NIC3_MAC_XPCS91_MAX_OFFSET 0x2380 1538*e65e175bSOded Gabbay #define NIC3_MAC_XPCS91_SECTION 0x3000 1539*e65e175bSOded Gabbay #define mmNIC3_MAC_CORE_BASE 0x7FFCD88000ull 1540*e65e175bSOded Gabbay #define NIC3_MAC_CORE_MAX_OFFSET 0x5400 1541*e65e175bSOded Gabbay #define NIC3_MAC_CORE_SECTION 0x1000 1542*e65e175bSOded Gabbay #define mmNIC3_MAC_AUX_BASE 0x7FFCD89000ull 1543*e65e175bSOded Gabbay #define NIC3_MAC_AUX_MAX_OFFSET 0x3000 1544*e65e175bSOded Gabbay #define NIC3_MAC_AUX_SECTION 0xF000 1545*e65e175bSOded Gabbay #define mmNIC3_PHY_BASE 0x7FFCD98000ull 1546*e65e175bSOded Gabbay #define NIC3_PHY_MAX_OFFSET 0x3400 1547*e65e175bSOded Gabbay #define NIC3_PHY_SECTION 0x8000 1548*e65e175bSOded Gabbay #define mmNIC3_QM0_BASE 0x7FFCDA0000ull 1549*e65e175bSOded Gabbay #define NIC3_QM0_MAX_OFFSET 0xD040 1550*e65e175bSOded Gabbay #define NIC3_QM0_SECTION 0x2000 1551*e65e175bSOded Gabbay #define mmNIC3_QM1_BASE 0x7FFCDA2000ull 1552*e65e175bSOded Gabbay #define NIC3_QM1_MAX_OFFSET 0xD040 1553*e65e175bSOded Gabbay #define NIC3_QM1_SECTION 0x2000 1554*e65e175bSOded Gabbay #define mmNIC3_QPC0_BASE 0x7FFCDA4000ull 1555*e65e175bSOded Gabbay #define NIC3_QPC0_MAX_OFFSET 0x7140 1556*e65e175bSOded Gabbay #define NIC3_QPC0_SECTION 0x1000 1557*e65e175bSOded Gabbay #define mmNIC3_QPC1_BASE 0x7FFCDA5000ull 1558*e65e175bSOded Gabbay #define NIC3_QPC1_MAX_OFFSET 0x7140 1559*e65e175bSOded Gabbay #define NIC3_QPC1_SECTION 0x3000 1560*e65e175bSOded Gabbay #define mmNIC3_RXB_BASE 0x7FFCDA8000ull 1561*e65e175bSOded Gabbay #define NIC3_RXB_MAX_OFFSET 0x6040 1562*e65e175bSOded Gabbay #define NIC3_RXB_SECTION 0x1000 1563*e65e175bSOded Gabbay #define mmNIC3_RXE0_BASE 0x7FFCDA9000ull 1564*e65e175bSOded Gabbay #define NIC3_RXE0_MAX_OFFSET 0x2FC0 1565*e65e175bSOded Gabbay #define NIC3_RXE0_SECTION 0x1000 1566*e65e175bSOded Gabbay #define mmNIC3_RXE1_BASE 0x7FFCDAA000ull 1567*e65e175bSOded Gabbay #define NIC3_RXE1_MAX_OFFSET 0x2FC0 1568*e65e175bSOded Gabbay #define NIC3_RXE1_SECTION 0x1000 1569*e65e175bSOded Gabbay #define mmNIC3_RX_GW_BASE 0x7FFCDAB000ull 1570*e65e175bSOded Gabbay #define NIC3_RX_GW_MAX_OFFSET 0x4540 1571*e65e175bSOded Gabbay #define NIC3_RX_GW_SECTION 0x5000 1572*e65e175bSOded Gabbay #define mmNIC3_TXS0_BASE 0x7FFCDB0000ull 1573*e65e175bSOded Gabbay #define NIC3_TXS0_MAX_OFFSET 0x19C0 1574*e65e175bSOded Gabbay #define NIC3_TXS0_SECTION 0x1000 1575*e65e175bSOded Gabbay #define mmNIC3_TXS1_BASE 0x7FFCDB1000ull 1576*e65e175bSOded Gabbay #define NIC3_TXS1_MAX_OFFSET 0x19C0 1577*e65e175bSOded Gabbay #define NIC3_TXS1_SECTION 0x1000 1578*e65e175bSOded Gabbay #define mmNIC3_TXE0_BASE 0x7FFCDB2000ull 1579*e65e175bSOded Gabbay #define NIC3_TXE0_MAX_OFFSET 0x2040 1580*e65e175bSOded Gabbay #define NIC3_TXE0_SECTION 0x1000 1581*e65e175bSOded Gabbay #define mmNIC3_TXE1_BASE 0x7FFCDB3000ull 1582*e65e175bSOded Gabbay #define NIC3_TXE1_MAX_OFFSET 0x2040 1583*e65e175bSOded Gabbay #define NIC3_TXE1_SECTION 0x1000 1584*e65e175bSOded Gabbay #define mmNIC3_TXB_BASE 0x7FFCDB4000ull 1585*e65e175bSOded Gabbay #define NIC3_TXB_MAX_OFFSET 0xD400 1586*e65e175bSOded Gabbay #define NIC3_TXB_SECTION 0x1000 1587*e65e175bSOded Gabbay #define mmNIC3_TMR_BASE 0x7FFCDB5000ull 1588*e65e175bSOded Gabbay #define NIC3_TMR_MAX_OFFSET 0x1600 1589*e65e175bSOded Gabbay #define NIC3_TMR_SECTION 0x1000 1590*e65e175bSOded Gabbay #define mmNIC3_TX_GW_BASE 0x7FFCDB6000ull 1591*e65e175bSOded Gabbay #define NIC3_TX_GW_MAX_OFFSET 0x1400 1592*e65e175bSOded Gabbay #define NIC3_TX_GW_SECTION 0x2000 1593*e65e175bSOded Gabbay #define mmNIC3_TS_BASE 0x7FFCDB8000ull 1594*e65e175bSOded Gabbay #define NIC3_TS_MAX_OFFSET 0xE640 1595*e65e175bSOded Gabbay #define NIC3_TS_SECTION 0x2000 1596*e65e175bSOded Gabbay #define mmNIC3_PM_BASE 0x7FFCDBA000ull 1597*e65e175bSOded Gabbay #define NIC3_PM_MAX_OFFSET 0x1F00 1598*e65e175bSOded Gabbay #define NIC3_PM_SECTION 0x6000 1599*e65e175bSOded Gabbay #define mmNIC4_MAC_CH0_BASE 0x7FFCDC0000ull 1600*e65e175bSOded Gabbay #define NIC4_MAC_CH0_MAX_OFFSET 0x8400 1601*e65e175bSOded Gabbay #define NIC4_MAC_CH0_SECTION 0x1000 1602*e65e175bSOded Gabbay #define mmNIC4_MAC_CH1_BASE 0x7FFCDC1000ull 1603*e65e175bSOded Gabbay #define NIC4_MAC_CH1_MAX_OFFSET 0x8400 1604*e65e175bSOded Gabbay #define NIC4_MAC_CH1_SECTION 0x1000 1605*e65e175bSOded Gabbay #define mmNIC4_MAC_CH2_BASE 0x7FFCDC2000ull 1606*e65e175bSOded Gabbay #define NIC4_MAC_CH2_MAX_OFFSET 0x8400 1607*e65e175bSOded Gabbay #define NIC4_MAC_CH2_SECTION 0x1000 1608*e65e175bSOded Gabbay #define mmNIC4_MAC_CH3_BASE 0x7FFCDC3000ull 1609*e65e175bSOded Gabbay #define NIC4_MAC_CH3_MAX_OFFSET 0x8400 1610*e65e175bSOded Gabbay #define NIC4_MAC_CH3_SECTION 0x1000 1611*e65e175bSOded Gabbay #define mmNIC4_STAT_BASE 0x7FFCDC4000ull 1612*e65e175bSOded Gabbay #define NIC4_STAT_MAX_OFFSET 0x4D00 1613*e65e175bSOded Gabbay #define NIC4_STAT_SECTION 0x1000 1614*e65e175bSOded Gabbay #define mmNIC4_MAC_XPCS91_BASE 0x7FFCDC5000ull 1615*e65e175bSOded Gabbay #define NIC4_MAC_XPCS91_MAX_OFFSET 0x2380 1616*e65e175bSOded Gabbay #define NIC4_MAC_XPCS91_SECTION 0x3000 1617*e65e175bSOded Gabbay #define mmNIC4_MAC_CORE_BASE 0x7FFCDC8000ull 1618*e65e175bSOded Gabbay #define NIC4_MAC_CORE_MAX_OFFSET 0x5400 1619*e65e175bSOded Gabbay #define NIC4_MAC_CORE_SECTION 0x1000 1620*e65e175bSOded Gabbay #define mmNIC4_MAC_AUX_BASE 0x7FFCDC9000ull 1621*e65e175bSOded Gabbay #define NIC4_MAC_AUX_MAX_OFFSET 0x3000 1622*e65e175bSOded Gabbay #define NIC4_MAC_AUX_SECTION 0xF000 1623*e65e175bSOded Gabbay #define mmNIC4_PHY_BASE 0x7FFCDD8000ull 1624*e65e175bSOded Gabbay #define NIC4_PHY_MAX_OFFSET 0x3400 1625*e65e175bSOded Gabbay #define NIC4_PHY_SECTION 0x8000 1626*e65e175bSOded Gabbay #define mmNIC4_QM0_BASE 0x7FFCDE0000ull 1627*e65e175bSOded Gabbay #define NIC4_QM0_MAX_OFFSET 0xD040 1628*e65e175bSOded Gabbay #define NIC4_QM0_SECTION 0x2000 1629*e65e175bSOded Gabbay #define mmNIC4_QM1_BASE 0x7FFCDE2000ull 1630*e65e175bSOded Gabbay #define NIC4_QM1_MAX_OFFSET 0xD040 1631*e65e175bSOded Gabbay #define NIC4_QM1_SECTION 0x2000 1632*e65e175bSOded Gabbay #define mmNIC4_QPC0_BASE 0x7FFCDE4000ull 1633*e65e175bSOded Gabbay #define NIC4_QPC0_MAX_OFFSET 0x7140 1634*e65e175bSOded Gabbay #define NIC4_QPC0_SECTION 0x1000 1635*e65e175bSOded Gabbay #define mmNIC4_QPC1_BASE 0x7FFCDE5000ull 1636*e65e175bSOded Gabbay #define NIC4_QPC1_MAX_OFFSET 0x7140 1637*e65e175bSOded Gabbay #define NIC4_QPC1_SECTION 0x3000 1638*e65e175bSOded Gabbay #define mmNIC4_RXB_BASE 0x7FFCDE8000ull 1639*e65e175bSOded Gabbay #define NIC4_RXB_MAX_OFFSET 0x6040 1640*e65e175bSOded Gabbay #define NIC4_RXB_SECTION 0x1000 1641*e65e175bSOded Gabbay #define mmNIC4_RXE0_BASE 0x7FFCDE9000ull 1642*e65e175bSOded Gabbay #define NIC4_RXE0_MAX_OFFSET 0x2FC0 1643*e65e175bSOded Gabbay #define NIC4_RXE0_SECTION 0x1000 1644*e65e175bSOded Gabbay #define mmNIC4_RXE1_BASE 0x7FFCDEA000ull 1645*e65e175bSOded Gabbay #define NIC4_RXE1_MAX_OFFSET 0x2FC0 1646*e65e175bSOded Gabbay #define NIC4_RXE1_SECTION 0x1000 1647*e65e175bSOded Gabbay #define mmNIC4_RX_GW_BASE 0x7FFCDEB000ull 1648*e65e175bSOded Gabbay #define NIC4_RX_GW_MAX_OFFSET 0x4540 1649*e65e175bSOded Gabbay #define NIC4_RX_GW_SECTION 0x5000 1650*e65e175bSOded Gabbay #define mmNIC4_TXS0_BASE 0x7FFCDF0000ull 1651*e65e175bSOded Gabbay #define NIC4_TXS0_MAX_OFFSET 0x19C0 1652*e65e175bSOded Gabbay #define NIC4_TXS0_SECTION 0x1000 1653*e65e175bSOded Gabbay #define mmNIC4_TXS1_BASE 0x7FFCDF1000ull 1654*e65e175bSOded Gabbay #define NIC4_TXS1_MAX_OFFSET 0x19C0 1655*e65e175bSOded Gabbay #define NIC4_TXS1_SECTION 0x1000 1656*e65e175bSOded Gabbay #define mmNIC4_TXE0_BASE 0x7FFCDF2000ull 1657*e65e175bSOded Gabbay #define NIC4_TXE0_MAX_OFFSET 0x2040 1658*e65e175bSOded Gabbay #define NIC4_TXE0_SECTION 0x1000 1659*e65e175bSOded Gabbay #define mmNIC4_TXE1_BASE 0x7FFCDF3000ull 1660*e65e175bSOded Gabbay #define NIC4_TXE1_MAX_OFFSET 0x2040 1661*e65e175bSOded Gabbay #define NIC4_TXE1_SECTION 0x1000 1662*e65e175bSOded Gabbay #define mmNIC4_TXB_BASE 0x7FFCDF4000ull 1663*e65e175bSOded Gabbay #define NIC4_TXB_MAX_OFFSET 0xD400 1664*e65e175bSOded Gabbay #define NIC4_TXB_SECTION 0x1000 1665*e65e175bSOded Gabbay #define mmNIC4_TMR_BASE 0x7FFCDF5000ull 1666*e65e175bSOded Gabbay #define NIC4_TMR_MAX_OFFSET 0x1600 1667*e65e175bSOded Gabbay #define NIC4_TMR_SECTION 0x1000 1668*e65e175bSOded Gabbay #define mmNIC4_TX_GW_BASE 0x7FFCDF6000ull 1669*e65e175bSOded Gabbay #define NIC4_TX_GW_MAX_OFFSET 0x1400 1670*e65e175bSOded Gabbay #define NIC4_TX_GW_SECTION 0x10000 1671*e65e175bSOded Gabbay #define mmTPC0_CFG_BASE 0x7FFCE06000ull 1672*e65e175bSOded Gabbay #define TPC0_CFG_MAX_OFFSET 0xE400 1673*e65e175bSOded Gabbay #define TPC0_CFG_SECTION 0x4000 1674*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06400ull 1675*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 1676*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC0_CFG_SECTION 0x3800 1677*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06438ull 1678*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 1679*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC0_CFG_SECTION 0x3800 1680*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06470ull 1681*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 1682*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC0_CFG_SECTION 0x3800 1683*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC0_CFG_BASE 0x7FFCE064A8ull 1684*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 1685*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC0_CFG_SECTION 0x3800 1686*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC0_CFG_BASE 0x7FFCE064E0ull 1687*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 1688*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC0_CFG_SECTION 0x3800 1689*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06518ull 1690*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 1691*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC0_CFG_SECTION 0x3800 1692*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06550ull 1693*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 1694*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC0_CFG_SECTION 0x3800 1695*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06588ull 1696*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 1697*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC0_CFG_SECTION 0x3800 1698*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC0_CFG_BASE 0x7FFCE065C0ull 1699*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 1700*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC0_CFG_SECTION 0x3800 1701*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC0_CFG_BASE 0x7FFCE065F8ull 1702*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 1703*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC0_CFG_SECTION 0x3800 1704*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06630ull 1705*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 1706*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC0_CFG_SECTION 0x3800 1707*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06668ull 1708*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 1709*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC0_CFG_SECTION 0x3800 1710*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC0_CFG_BASE 0x7FFCE066A0ull 1711*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 1712*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC0_CFG_SECTION 0x3800 1713*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC0_CFG_BASE 0x7FFCE066D8ull 1714*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 1715*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC0_CFG_SECTION 0x3800 1716*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06710ull 1717*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 1718*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC0_CFG_SECTION 0x3800 1719*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06748ull 1720*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 1721*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC0_CFG_SECTION 0x3800 1722*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06780ull 1723*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 1724*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 1725*e65e175bSOded Gabbay #define mmKERNEL_TPC0_CFG_BASE 0x7FFCE06788ull 1726*e65e175bSOded Gabbay #define KERNEL_TPC0_CFG_MAX_OFFSET 0xB800 1727*e65e175bSOded Gabbay #define KERNEL_TPC0_CFG_SECTION 0x2780 1728*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06A00ull 1729*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800 1730*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC0_CFG_SECTION 0x3800 1731*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06A38ull 1732*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800 1733*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC0_CFG_SECTION 0x3800 1734*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06A70ull 1735*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800 1736*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC0_CFG_SECTION 0x3800 1737*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC0_CFG_BASE 0x7FFCE06AA8ull 1738*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800 1739*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC0_CFG_SECTION 0x3800 1740*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC0_CFG_BASE 0x7FFCE06AE0ull 1741*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800 1742*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC0_CFG_SECTION 0x3800 1743*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06B18ull 1744*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800 1745*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC0_CFG_SECTION 0x3800 1746*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06B50ull 1747*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800 1748*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC0_CFG_SECTION 0x3800 1749*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06B88ull 1750*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800 1751*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC0_CFG_SECTION 0x3800 1752*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC0_CFG_BASE 0x7FFCE06BC0ull 1753*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800 1754*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC0_CFG_SECTION 0x3800 1755*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC0_CFG_BASE 0x7FFCE06BF8ull 1756*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800 1757*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC0_CFG_SECTION 0x3800 1758*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06C30ull 1759*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800 1760*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC0_CFG_SECTION 0x3800 1761*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06C68ull 1762*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800 1763*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC0_CFG_SECTION 0x3800 1764*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC0_CFG_BASE 0x7FFCE06CA0ull 1765*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800 1766*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC0_CFG_SECTION 0x3800 1767*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC0_CFG_BASE 0x7FFCE06CD8ull 1768*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800 1769*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC0_CFG_SECTION 0x3800 1770*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06D10ull 1771*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800 1772*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC0_CFG_SECTION 0x3800 1773*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06D48ull 1774*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800 1775*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC0_CFG_SECTION 0x3800 1776*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06D80ull 1777*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000 1778*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000 1779*e65e175bSOded Gabbay #define mmQM_TPC0_CFG_BASE 0x7FFCE06D88ull 1780*e65e175bSOded Gabbay #define QM_TPC0_CFG_MAX_OFFSET 0xB800 1781*e65e175bSOded Gabbay #define QM_TPC0_CFG_SECTION 0x2780 1782*e65e175bSOded Gabbay #define mmTPC0_E2E_CRED_BASE 0x7FFCE07000ull 1783*e65e175bSOded Gabbay #define TPC0_E2E_CRED_MAX_OFFSET 0x1680 1784*e65e175bSOded Gabbay #define TPC0_E2E_CRED_SECTION 0x1000 1785*e65e175bSOded Gabbay #define mmTPC0_QM_BASE 0x7FFCE08000ull 1786*e65e175bSOded Gabbay #define TPC0_QM_MAX_OFFSET 0xD040 1787*e65e175bSOded Gabbay #define TPC0_QM_SECTION 0x3E000 1788*e65e175bSOded Gabbay #define mmTPC1_CFG_BASE 0x7FFCE46000ull 1789*e65e175bSOded Gabbay #define TPC1_CFG_MAX_OFFSET 0xE400 1790*e65e175bSOded Gabbay #define TPC1_CFG_SECTION 0x4000 1791*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46400ull 1792*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 1793*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC1_CFG_SECTION 0x3800 1794*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46438ull 1795*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 1796*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC1_CFG_SECTION 0x3800 1797*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46470ull 1798*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 1799*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC1_CFG_SECTION 0x3800 1800*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC1_CFG_BASE 0x7FFCE464A8ull 1801*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 1802*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC1_CFG_SECTION 0x3800 1803*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC1_CFG_BASE 0x7FFCE464E0ull 1804*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 1805*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC1_CFG_SECTION 0x3800 1806*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46518ull 1807*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 1808*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC1_CFG_SECTION 0x3800 1809*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46550ull 1810*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 1811*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC1_CFG_SECTION 0x3800 1812*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46588ull 1813*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 1814*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC1_CFG_SECTION 0x3800 1815*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC1_CFG_BASE 0x7FFCE465C0ull 1816*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 1817*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC1_CFG_SECTION 0x3800 1818*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC1_CFG_BASE 0x7FFCE465F8ull 1819*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 1820*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC1_CFG_SECTION 0x3800 1821*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46630ull 1822*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 1823*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC1_CFG_SECTION 0x3800 1824*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46668ull 1825*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 1826*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC1_CFG_SECTION 0x3800 1827*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC1_CFG_BASE 0x7FFCE466A0ull 1828*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 1829*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC1_CFG_SECTION 0x3800 1830*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC1_CFG_BASE 0x7FFCE466D8ull 1831*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 1832*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC1_CFG_SECTION 0x3800 1833*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46710ull 1834*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 1835*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC1_CFG_SECTION 0x3800 1836*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46748ull 1837*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 1838*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC1_CFG_SECTION 0x3800 1839*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46780ull 1840*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 1841*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 1842*e65e175bSOded Gabbay #define mmKERNEL_TPC1_CFG_BASE 0x7FFCE46788ull 1843*e65e175bSOded Gabbay #define KERNEL_TPC1_CFG_MAX_OFFSET 0xB800 1844*e65e175bSOded Gabbay #define KERNEL_TPC1_CFG_SECTION 0x2780 1845*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46A00ull 1846*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800 1847*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC1_CFG_SECTION 0x3800 1848*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46A38ull 1849*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800 1850*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC1_CFG_SECTION 0x3800 1851*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46A70ull 1852*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800 1853*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC1_CFG_SECTION 0x3800 1854*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC1_CFG_BASE 0x7FFCE46AA8ull 1855*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800 1856*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC1_CFG_SECTION 0x3800 1857*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC1_CFG_BASE 0x7FFCE46AE0ull 1858*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800 1859*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC1_CFG_SECTION 0x3800 1860*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46B18ull 1861*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800 1862*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC1_CFG_SECTION 0x3800 1863*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46B50ull 1864*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800 1865*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC1_CFG_SECTION 0x3800 1866*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46B88ull 1867*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800 1868*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC1_CFG_SECTION 0x3800 1869*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC1_CFG_BASE 0x7FFCE46BC0ull 1870*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800 1871*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC1_CFG_SECTION 0x3800 1872*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC1_CFG_BASE 0x7FFCE46BF8ull 1873*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800 1874*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC1_CFG_SECTION 0x3800 1875*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46C30ull 1876*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800 1877*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC1_CFG_SECTION 0x3800 1878*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46C68ull 1879*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800 1880*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC1_CFG_SECTION 0x3800 1881*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC1_CFG_BASE 0x7FFCE46CA0ull 1882*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800 1883*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC1_CFG_SECTION 0x3800 1884*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC1_CFG_BASE 0x7FFCE46CD8ull 1885*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800 1886*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC1_CFG_SECTION 0x3800 1887*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46D10ull 1888*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800 1889*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC1_CFG_SECTION 0x3800 1890*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46D48ull 1891*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800 1892*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC1_CFG_SECTION 0x3800 1893*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46D80ull 1894*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000 1895*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000 1896*e65e175bSOded Gabbay #define mmQM_TPC1_CFG_BASE 0x7FFCE46D88ull 1897*e65e175bSOded Gabbay #define QM_TPC1_CFG_MAX_OFFSET 0xB800 1898*e65e175bSOded Gabbay #define QM_TPC1_CFG_SECTION 0x2780 1899*e65e175bSOded Gabbay #define mmTPC1_E2E_CRED_BASE 0x7FFCE47000ull 1900*e65e175bSOded Gabbay #define TPC1_E2E_CRED_MAX_OFFSET 0x1680 1901*e65e175bSOded Gabbay #define TPC1_E2E_CRED_SECTION 0x1000 1902*e65e175bSOded Gabbay #define mmTPC1_QM_BASE 0x7FFCE48000ull 1903*e65e175bSOded Gabbay #define TPC1_QM_MAX_OFFSET 0xD040 1904*e65e175bSOded Gabbay #define TPC1_QM_SECTION 0x3E000 1905*e65e175bSOded Gabbay #define mmTPC2_CFG_BASE 0x7FFCE86000ull 1906*e65e175bSOded Gabbay #define TPC2_CFG_MAX_OFFSET 0xE400 1907*e65e175bSOded Gabbay #define TPC2_CFG_SECTION 0x4000 1908*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86400ull 1909*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 1910*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC2_CFG_SECTION 0x3800 1911*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86438ull 1912*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 1913*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC2_CFG_SECTION 0x3800 1914*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86470ull 1915*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 1916*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC2_CFG_SECTION 0x3800 1917*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC2_CFG_BASE 0x7FFCE864A8ull 1918*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 1919*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC2_CFG_SECTION 0x3800 1920*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC2_CFG_BASE 0x7FFCE864E0ull 1921*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 1922*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC2_CFG_SECTION 0x3800 1923*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86518ull 1924*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 1925*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC2_CFG_SECTION 0x3800 1926*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86550ull 1927*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 1928*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC2_CFG_SECTION 0x3800 1929*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86588ull 1930*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 1931*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC2_CFG_SECTION 0x3800 1932*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC2_CFG_BASE 0x7FFCE865C0ull 1933*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 1934*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC2_CFG_SECTION 0x3800 1935*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC2_CFG_BASE 0x7FFCE865F8ull 1936*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 1937*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC2_CFG_SECTION 0x3800 1938*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86630ull 1939*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 1940*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC2_CFG_SECTION 0x3800 1941*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86668ull 1942*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 1943*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC2_CFG_SECTION 0x3800 1944*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC2_CFG_BASE 0x7FFCE866A0ull 1945*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 1946*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC2_CFG_SECTION 0x3800 1947*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC2_CFG_BASE 0x7FFCE866D8ull 1948*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 1949*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC2_CFG_SECTION 0x3800 1950*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86710ull 1951*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 1952*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC2_CFG_SECTION 0x3800 1953*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86748ull 1954*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 1955*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC2_CFG_SECTION 0x3800 1956*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86780ull 1957*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 1958*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 1959*e65e175bSOded Gabbay #define mmKERNEL_TPC2_CFG_BASE 0x7FFCE86788ull 1960*e65e175bSOded Gabbay #define KERNEL_TPC2_CFG_MAX_OFFSET 0xB800 1961*e65e175bSOded Gabbay #define KERNEL_TPC2_CFG_SECTION 0x2780 1962*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86A00ull 1963*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800 1964*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC2_CFG_SECTION 0x3800 1965*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86A38ull 1966*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800 1967*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC2_CFG_SECTION 0x3800 1968*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86A70ull 1969*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800 1970*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC2_CFG_SECTION 0x3800 1971*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC2_CFG_BASE 0x7FFCE86AA8ull 1972*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800 1973*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC2_CFG_SECTION 0x3800 1974*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC2_CFG_BASE 0x7FFCE86AE0ull 1975*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800 1976*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC2_CFG_SECTION 0x3800 1977*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86B18ull 1978*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800 1979*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC2_CFG_SECTION 0x3800 1980*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86B50ull 1981*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800 1982*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC2_CFG_SECTION 0x3800 1983*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86B88ull 1984*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800 1985*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC2_CFG_SECTION 0x3800 1986*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC2_CFG_BASE 0x7FFCE86BC0ull 1987*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800 1988*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC2_CFG_SECTION 0x3800 1989*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC2_CFG_BASE 0x7FFCE86BF8ull 1990*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800 1991*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC2_CFG_SECTION 0x3800 1992*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86C30ull 1993*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800 1994*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC2_CFG_SECTION 0x3800 1995*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86C68ull 1996*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800 1997*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC2_CFG_SECTION 0x3800 1998*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC2_CFG_BASE 0x7FFCE86CA0ull 1999*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800 2000*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC2_CFG_SECTION 0x3800 2001*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC2_CFG_BASE 0x7FFCE86CD8ull 2002*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800 2003*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC2_CFG_SECTION 0x3800 2004*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86D10ull 2005*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800 2006*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC2_CFG_SECTION 0x3800 2007*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86D48ull 2008*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800 2009*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC2_CFG_SECTION 0x3800 2010*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86D80ull 2011*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000 2012*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000 2013*e65e175bSOded Gabbay #define mmQM_TPC2_CFG_BASE 0x7FFCE86D88ull 2014*e65e175bSOded Gabbay #define QM_TPC2_CFG_MAX_OFFSET 0xB800 2015*e65e175bSOded Gabbay #define QM_TPC2_CFG_SECTION 0x2780 2016*e65e175bSOded Gabbay #define mmTPC2_E2E_CRED_BASE 0x7FFCE87000ull 2017*e65e175bSOded Gabbay #define TPC2_E2E_CRED_MAX_OFFSET 0x1680 2018*e65e175bSOded Gabbay #define TPC2_E2E_CRED_SECTION 0x1000 2019*e65e175bSOded Gabbay #define mmTPC2_QM_BASE 0x7FFCE88000ull 2020*e65e175bSOded Gabbay #define TPC2_QM_MAX_OFFSET 0xD040 2021*e65e175bSOded Gabbay #define TPC2_QM_SECTION 0x3E000 2022*e65e175bSOded Gabbay #define mmTPC3_CFG_BASE 0x7FFCEC6000ull 2023*e65e175bSOded Gabbay #define TPC3_CFG_MAX_OFFSET 0xE400 2024*e65e175bSOded Gabbay #define TPC3_CFG_SECTION 0x4000 2025*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6400ull 2026*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 2027*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC3_CFG_SECTION 0x3800 2028*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6438ull 2029*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 2030*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC3_CFG_SECTION 0x3800 2031*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6470ull 2032*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 2033*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC3_CFG_SECTION 0x3800 2034*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC64A8ull 2035*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 2036*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC3_CFG_SECTION 0x3800 2037*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC64E0ull 2038*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 2039*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC3_CFG_SECTION 0x3800 2040*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6518ull 2041*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 2042*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC3_CFG_SECTION 0x3800 2043*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6550ull 2044*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 2045*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC3_CFG_SECTION 0x3800 2046*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6588ull 2047*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 2048*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC3_CFG_SECTION 0x3800 2049*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC65C0ull 2050*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 2051*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC3_CFG_SECTION 0x3800 2052*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC65F8ull 2053*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 2054*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC3_CFG_SECTION 0x3800 2055*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6630ull 2056*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 2057*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC3_CFG_SECTION 0x3800 2058*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6668ull 2059*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 2060*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC3_CFG_SECTION 0x3800 2061*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC66A0ull 2062*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 2063*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC3_CFG_SECTION 0x3800 2064*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC66D8ull 2065*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 2066*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC3_CFG_SECTION 0x3800 2067*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6710ull 2068*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 2069*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC3_CFG_SECTION 0x3800 2070*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6748ull 2071*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 2072*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC3_CFG_SECTION 0x3800 2073*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6780ull 2074*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 2075*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 2076*e65e175bSOded Gabbay #define mmKERNEL_TPC3_CFG_BASE 0x7FFCEC6788ull 2077*e65e175bSOded Gabbay #define KERNEL_TPC3_CFG_MAX_OFFSET 0xB800 2078*e65e175bSOded Gabbay #define KERNEL_TPC3_CFG_SECTION 0x2780 2079*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6A00ull 2080*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800 2081*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC3_CFG_SECTION 0x3800 2082*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6A38ull 2083*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800 2084*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC3_CFG_SECTION 0x3800 2085*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6A70ull 2086*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800 2087*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC3_CFG_SECTION 0x3800 2088*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC6AA8ull 2089*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800 2090*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC3_CFG_SECTION 0x3800 2091*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC6AE0ull 2092*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800 2093*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC3_CFG_SECTION 0x3800 2094*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6B18ull 2095*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800 2096*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC3_CFG_SECTION 0x3800 2097*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6B50ull 2098*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800 2099*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC3_CFG_SECTION 0x3800 2100*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6B88ull 2101*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800 2102*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC3_CFG_SECTION 0x3800 2103*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC6BC0ull 2104*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800 2105*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC3_CFG_SECTION 0x3800 2106*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC6BF8ull 2107*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800 2108*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC3_CFG_SECTION 0x3800 2109*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6C30ull 2110*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800 2111*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC3_CFG_SECTION 0x3800 2112*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6C68ull 2113*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800 2114*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC3_CFG_SECTION 0x3800 2115*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC6CA0ull 2116*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800 2117*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC3_CFG_SECTION 0x3800 2118*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC6CD8ull 2119*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800 2120*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC3_CFG_SECTION 0x3800 2121*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6D10ull 2122*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800 2123*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC3_CFG_SECTION 0x3800 2124*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6D48ull 2125*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800 2126*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC3_CFG_SECTION 0x3800 2127*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6D80ull 2128*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000 2129*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000 2130*e65e175bSOded Gabbay #define mmQM_TPC3_CFG_BASE 0x7FFCEC6D88ull 2131*e65e175bSOded Gabbay #define QM_TPC3_CFG_MAX_OFFSET 0xB800 2132*e65e175bSOded Gabbay #define QM_TPC3_CFG_SECTION 0x2780 2133*e65e175bSOded Gabbay #define mmTPC3_E2E_CRED_BASE 0x7FFCEC7000ull 2134*e65e175bSOded Gabbay #define TPC3_E2E_CRED_MAX_OFFSET 0x1680 2135*e65e175bSOded Gabbay #define TPC3_E2E_CRED_SECTION 0x1000 2136*e65e175bSOded Gabbay #define mmTPC3_QM_BASE 0x7FFCEC8000ull 2137*e65e175bSOded Gabbay #define TPC3_QM_MAX_OFFSET 0xD040 2138*e65e175bSOded Gabbay #define TPC3_QM_SECTION 0x3E000 2139*e65e175bSOded Gabbay #define mmTPC4_CFG_BASE 0x7FFCF06000ull 2140*e65e175bSOded Gabbay #define TPC4_CFG_MAX_OFFSET 0xE400 2141*e65e175bSOded Gabbay #define TPC4_CFG_SECTION 0x4000 2142*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06400ull 2143*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 2144*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC4_CFG_SECTION 0x3800 2145*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06438ull 2146*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 2147*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC4_CFG_SECTION 0x3800 2148*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06470ull 2149*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 2150*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC4_CFG_SECTION 0x3800 2151*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC4_CFG_BASE 0x7FFCF064A8ull 2152*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 2153*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC4_CFG_SECTION 0x3800 2154*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC4_CFG_BASE 0x7FFCF064E0ull 2155*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 2156*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC4_CFG_SECTION 0x3800 2157*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06518ull 2158*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 2159*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC4_CFG_SECTION 0x3800 2160*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06550ull 2161*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 2162*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC4_CFG_SECTION 0x3800 2163*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06588ull 2164*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 2165*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC4_CFG_SECTION 0x3800 2166*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC4_CFG_BASE 0x7FFCF065C0ull 2167*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 2168*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC4_CFG_SECTION 0x3800 2169*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC4_CFG_BASE 0x7FFCF065F8ull 2170*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 2171*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC4_CFG_SECTION 0x3800 2172*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06630ull 2173*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 2174*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC4_CFG_SECTION 0x3800 2175*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06668ull 2176*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 2177*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC4_CFG_SECTION 0x3800 2178*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC4_CFG_BASE 0x7FFCF066A0ull 2179*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 2180*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC4_CFG_SECTION 0x3800 2181*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC4_CFG_BASE 0x7FFCF066D8ull 2182*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 2183*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC4_CFG_SECTION 0x3800 2184*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06710ull 2185*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 2186*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC4_CFG_SECTION 0x3800 2187*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06748ull 2188*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 2189*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC4_CFG_SECTION 0x3800 2190*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06780ull 2191*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 2192*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 2193*e65e175bSOded Gabbay #define mmKERNEL_TPC4_CFG_BASE 0x7FFCF06788ull 2194*e65e175bSOded Gabbay #define KERNEL_TPC4_CFG_MAX_OFFSET 0xB800 2195*e65e175bSOded Gabbay #define KERNEL_TPC4_CFG_SECTION 0x2780 2196*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06A00ull 2197*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800 2198*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC4_CFG_SECTION 0x3800 2199*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06A38ull 2200*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800 2201*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC4_CFG_SECTION 0x3800 2202*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06A70ull 2203*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800 2204*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC4_CFG_SECTION 0x3800 2205*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC4_CFG_BASE 0x7FFCF06AA8ull 2206*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800 2207*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC4_CFG_SECTION 0x3800 2208*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC4_CFG_BASE 0x7FFCF06AE0ull 2209*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800 2210*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC4_CFG_SECTION 0x3800 2211*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06B18ull 2212*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800 2213*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC4_CFG_SECTION 0x3800 2214*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06B50ull 2215*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800 2216*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC4_CFG_SECTION 0x3800 2217*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06B88ull 2218*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800 2219*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC4_CFG_SECTION 0x3800 2220*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC4_CFG_BASE 0x7FFCF06BC0ull 2221*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800 2222*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC4_CFG_SECTION 0x3800 2223*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC4_CFG_BASE 0x7FFCF06BF8ull 2224*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800 2225*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC4_CFG_SECTION 0x3800 2226*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06C30ull 2227*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800 2228*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC4_CFG_SECTION 0x3800 2229*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06C68ull 2230*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800 2231*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC4_CFG_SECTION 0x3800 2232*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC4_CFG_BASE 0x7FFCF06CA0ull 2233*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800 2234*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC4_CFG_SECTION 0x3800 2235*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC4_CFG_BASE 0x7FFCF06CD8ull 2236*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800 2237*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC4_CFG_SECTION 0x3800 2238*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06D10ull 2239*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800 2240*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC4_CFG_SECTION 0x3800 2241*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06D48ull 2242*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800 2243*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC4_CFG_SECTION 0x3800 2244*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06D80ull 2245*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000 2246*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000 2247*e65e175bSOded Gabbay #define mmQM_TPC4_CFG_BASE 0x7FFCF06D88ull 2248*e65e175bSOded Gabbay #define QM_TPC4_CFG_MAX_OFFSET 0xB800 2249*e65e175bSOded Gabbay #define QM_TPC4_CFG_SECTION 0x2780 2250*e65e175bSOded Gabbay #define mmTPC4_E2E_CRED_BASE 0x7FFCF07000ull 2251*e65e175bSOded Gabbay #define TPC4_E2E_CRED_MAX_OFFSET 0x1680 2252*e65e175bSOded Gabbay #define TPC4_E2E_CRED_SECTION 0x1000 2253*e65e175bSOded Gabbay #define mmTPC4_QM_BASE 0x7FFCF08000ull 2254*e65e175bSOded Gabbay #define TPC4_QM_MAX_OFFSET 0xD040 2255*e65e175bSOded Gabbay #define TPC4_QM_SECTION 0x3E000 2256*e65e175bSOded Gabbay #define mmTPC5_CFG_BASE 0x7FFCF46000ull 2257*e65e175bSOded Gabbay #define TPC5_CFG_MAX_OFFSET 0xE400 2258*e65e175bSOded Gabbay #define TPC5_CFG_SECTION 0x4000 2259*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46400ull 2260*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 2261*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC5_CFG_SECTION 0x3800 2262*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46438ull 2263*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 2264*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC5_CFG_SECTION 0x3800 2265*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46470ull 2266*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 2267*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC5_CFG_SECTION 0x3800 2268*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC5_CFG_BASE 0x7FFCF464A8ull 2269*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 2270*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC5_CFG_SECTION 0x3800 2271*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC5_CFG_BASE 0x7FFCF464E0ull 2272*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 2273*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC5_CFG_SECTION 0x3800 2274*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46518ull 2275*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 2276*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC5_CFG_SECTION 0x3800 2277*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46550ull 2278*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 2279*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC5_CFG_SECTION 0x3800 2280*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46588ull 2281*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 2282*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC5_CFG_SECTION 0x3800 2283*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC5_CFG_BASE 0x7FFCF465C0ull 2284*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 2285*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC5_CFG_SECTION 0x3800 2286*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC5_CFG_BASE 0x7FFCF465F8ull 2287*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 2288*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC5_CFG_SECTION 0x3800 2289*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46630ull 2290*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 2291*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC5_CFG_SECTION 0x3800 2292*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46668ull 2293*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 2294*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC5_CFG_SECTION 0x3800 2295*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC5_CFG_BASE 0x7FFCF466A0ull 2296*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 2297*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC5_CFG_SECTION 0x3800 2298*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC5_CFG_BASE 0x7FFCF466D8ull 2299*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 2300*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC5_CFG_SECTION 0x3800 2301*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46710ull 2302*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 2303*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC5_CFG_SECTION 0x3800 2304*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46748ull 2305*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 2306*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC5_CFG_SECTION 0x3800 2307*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46780ull 2308*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 2309*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 2310*e65e175bSOded Gabbay #define mmKERNEL_TPC5_CFG_BASE 0x7FFCF46788ull 2311*e65e175bSOded Gabbay #define KERNEL_TPC5_CFG_MAX_OFFSET 0xB800 2312*e65e175bSOded Gabbay #define KERNEL_TPC5_CFG_SECTION 0x2780 2313*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46A00ull 2314*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800 2315*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC5_CFG_SECTION 0x3800 2316*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46A38ull 2317*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800 2318*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC5_CFG_SECTION 0x3800 2319*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46A70ull 2320*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800 2321*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC5_CFG_SECTION 0x3800 2322*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC5_CFG_BASE 0x7FFCF46AA8ull 2323*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800 2324*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC5_CFG_SECTION 0x3800 2325*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC5_CFG_BASE 0x7FFCF46AE0ull 2326*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800 2327*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC5_CFG_SECTION 0x3800 2328*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46B18ull 2329*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800 2330*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC5_CFG_SECTION 0x3800 2331*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46B50ull 2332*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800 2333*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC5_CFG_SECTION 0x3800 2334*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46B88ull 2335*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800 2336*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC5_CFG_SECTION 0x3800 2337*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC5_CFG_BASE 0x7FFCF46BC0ull 2338*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800 2339*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC5_CFG_SECTION 0x3800 2340*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC5_CFG_BASE 0x7FFCF46BF8ull 2341*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800 2342*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC5_CFG_SECTION 0x3800 2343*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46C30ull 2344*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800 2345*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC5_CFG_SECTION 0x3800 2346*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46C68ull 2347*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800 2348*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC5_CFG_SECTION 0x3800 2349*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC5_CFG_BASE 0x7FFCF46CA0ull 2350*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800 2351*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC5_CFG_SECTION 0x3800 2352*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC5_CFG_BASE 0x7FFCF46CD8ull 2353*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800 2354*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC5_CFG_SECTION 0x3800 2355*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46D10ull 2356*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800 2357*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC5_CFG_SECTION 0x3800 2358*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46D48ull 2359*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800 2360*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC5_CFG_SECTION 0x3800 2361*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46D80ull 2362*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000 2363*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000 2364*e65e175bSOded Gabbay #define mmQM_TPC5_CFG_BASE 0x7FFCF46D88ull 2365*e65e175bSOded Gabbay #define QM_TPC5_CFG_MAX_OFFSET 0xB800 2366*e65e175bSOded Gabbay #define QM_TPC5_CFG_SECTION 0x2780 2367*e65e175bSOded Gabbay #define mmTPC5_E2E_CRED_BASE 0x7FFCF47000ull 2368*e65e175bSOded Gabbay #define TPC5_E2E_CRED_MAX_OFFSET 0x1680 2369*e65e175bSOded Gabbay #define TPC5_E2E_CRED_SECTION 0x1000 2370*e65e175bSOded Gabbay #define mmTPC5_QM_BASE 0x7FFCF48000ull 2371*e65e175bSOded Gabbay #define TPC5_QM_MAX_OFFSET 0xD040 2372*e65e175bSOded Gabbay #define TPC5_QM_SECTION 0x3E000 2373*e65e175bSOded Gabbay #define mmTPC6_CFG_BASE 0x7FFCF86000ull 2374*e65e175bSOded Gabbay #define TPC6_CFG_MAX_OFFSET 0xE400 2375*e65e175bSOded Gabbay #define TPC6_CFG_SECTION 0x4000 2376*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86400ull 2377*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 2378*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC6_CFG_SECTION 0x3800 2379*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86438ull 2380*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 2381*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC6_CFG_SECTION 0x3800 2382*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86470ull 2383*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 2384*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC6_CFG_SECTION 0x3800 2385*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC6_CFG_BASE 0x7FFCF864A8ull 2386*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 2387*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC6_CFG_SECTION 0x3800 2388*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC6_CFG_BASE 0x7FFCF864E0ull 2389*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 2390*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC6_CFG_SECTION 0x3800 2391*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86518ull 2392*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 2393*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC6_CFG_SECTION 0x3800 2394*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86550ull 2395*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 2396*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC6_CFG_SECTION 0x3800 2397*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86588ull 2398*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 2399*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC6_CFG_SECTION 0x3800 2400*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC6_CFG_BASE 0x7FFCF865C0ull 2401*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 2402*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC6_CFG_SECTION 0x3800 2403*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC6_CFG_BASE 0x7FFCF865F8ull 2404*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 2405*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC6_CFG_SECTION 0x3800 2406*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86630ull 2407*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 2408*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC6_CFG_SECTION 0x3800 2409*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86668ull 2410*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 2411*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC6_CFG_SECTION 0x3800 2412*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC6_CFG_BASE 0x7FFCF866A0ull 2413*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 2414*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC6_CFG_SECTION 0x3800 2415*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC6_CFG_BASE 0x7FFCF866D8ull 2416*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 2417*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC6_CFG_SECTION 0x3800 2418*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86710ull 2419*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 2420*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC6_CFG_SECTION 0x3800 2421*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86748ull 2422*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 2423*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC6_CFG_SECTION 0x3800 2424*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86780ull 2425*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 2426*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 2427*e65e175bSOded Gabbay #define mmKERNEL_TPC6_CFG_BASE 0x7FFCF86788ull 2428*e65e175bSOded Gabbay #define KERNEL_TPC6_CFG_MAX_OFFSET 0xB800 2429*e65e175bSOded Gabbay #define KERNEL_TPC6_CFG_SECTION 0x2780 2430*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86A00ull 2431*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800 2432*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC6_CFG_SECTION 0x3800 2433*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86A38ull 2434*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800 2435*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC6_CFG_SECTION 0x3800 2436*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86A70ull 2437*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800 2438*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC6_CFG_SECTION 0x3800 2439*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC6_CFG_BASE 0x7FFCF86AA8ull 2440*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800 2441*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC6_CFG_SECTION 0x3800 2442*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC6_CFG_BASE 0x7FFCF86AE0ull 2443*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800 2444*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC6_CFG_SECTION 0x3800 2445*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86B18ull 2446*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800 2447*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC6_CFG_SECTION 0x3800 2448*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86B50ull 2449*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800 2450*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC6_CFG_SECTION 0x3800 2451*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86B88ull 2452*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800 2453*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC6_CFG_SECTION 0x3800 2454*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC6_CFG_BASE 0x7FFCF86BC0ull 2455*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800 2456*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC6_CFG_SECTION 0x3800 2457*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC6_CFG_BASE 0x7FFCF86BF8ull 2458*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800 2459*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC6_CFG_SECTION 0x3800 2460*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86C30ull 2461*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800 2462*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC6_CFG_SECTION 0x3800 2463*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86C68ull 2464*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800 2465*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC6_CFG_SECTION 0x3800 2466*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC6_CFG_BASE 0x7FFCF86CA0ull 2467*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800 2468*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC6_CFG_SECTION 0x3800 2469*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC6_CFG_BASE 0x7FFCF86CD8ull 2470*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800 2471*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC6_CFG_SECTION 0x3800 2472*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86D10ull 2473*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800 2474*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC6_CFG_SECTION 0x3800 2475*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86D48ull 2476*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800 2477*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC6_CFG_SECTION 0x3800 2478*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86D80ull 2479*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000 2480*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000 2481*e65e175bSOded Gabbay #define mmQM_TPC6_CFG_BASE 0x7FFCF86D88ull 2482*e65e175bSOded Gabbay #define QM_TPC6_CFG_MAX_OFFSET 0xB800 2483*e65e175bSOded Gabbay #define QM_TPC6_CFG_SECTION 0x2780 2484*e65e175bSOded Gabbay #define mmTPC6_E2E_CRED_BASE 0x7FFCF87000ull 2485*e65e175bSOded Gabbay #define TPC6_E2E_CRED_MAX_OFFSET 0x1680 2486*e65e175bSOded Gabbay #define TPC6_E2E_CRED_SECTION 0x1000 2487*e65e175bSOded Gabbay #define mmTPC6_QM_BASE 0x7FFCF88000ull 2488*e65e175bSOded Gabbay #define TPC6_QM_MAX_OFFSET 0xD040 2489*e65e175bSOded Gabbay #define TPC6_QM_SECTION 0x3E000 2490*e65e175bSOded Gabbay #define mmTPC7_CFG_BASE 0x7FFCFC6000ull 2491*e65e175bSOded Gabbay #define TPC7_CFG_MAX_OFFSET 0xE400 2492*e65e175bSOded Gabbay #define TPC7_CFG_SECTION 0x4000 2493*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6400ull 2494*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 2495*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC7_CFG_SECTION 0x3800 2496*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6438ull 2497*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 2498*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC7_CFG_SECTION 0x3800 2499*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6470ull 2500*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 2501*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC7_CFG_SECTION 0x3800 2502*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC64A8ull 2503*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 2504*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC7_CFG_SECTION 0x3800 2505*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC64E0ull 2506*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 2507*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC7_CFG_SECTION 0x3800 2508*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6518ull 2509*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 2510*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC7_CFG_SECTION 0x3800 2511*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6550ull 2512*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 2513*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC7_CFG_SECTION 0x3800 2514*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6588ull 2515*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 2516*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC7_CFG_SECTION 0x3800 2517*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC65C0ull 2518*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 2519*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC7_CFG_SECTION 0x3800 2520*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC65F8ull 2521*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 2522*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC7_CFG_SECTION 0x3800 2523*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6630ull 2524*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 2525*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC7_CFG_SECTION 0x3800 2526*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6668ull 2527*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 2528*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC7_CFG_SECTION 0x3800 2529*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC66A0ull 2530*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 2531*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC7_CFG_SECTION 0x3800 2532*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC66D8ull 2533*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 2534*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC7_CFG_SECTION 0x3800 2535*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6710ull 2536*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 2537*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC7_CFG_SECTION 0x3800 2538*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6748ull 2539*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 2540*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC7_CFG_SECTION 0x3800 2541*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6780ull 2542*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 2543*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 2544*e65e175bSOded Gabbay #define mmKERNEL_TPC7_CFG_BASE 0x7FFCFC6788ull 2545*e65e175bSOded Gabbay #define KERNEL_TPC7_CFG_MAX_OFFSET 0xB800 2546*e65e175bSOded Gabbay #define KERNEL_TPC7_CFG_SECTION 0x2780 2547*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6A00ull 2548*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800 2549*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC7_CFG_SECTION 0x3800 2550*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6A38ull 2551*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800 2552*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC7_CFG_SECTION 0x3800 2553*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6A70ull 2554*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800 2555*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC7_CFG_SECTION 0x3800 2556*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC6AA8ull 2557*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800 2558*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC7_CFG_SECTION 0x3800 2559*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC6AE0ull 2560*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800 2561*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC7_CFG_SECTION 0x3800 2562*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6B18ull 2563*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800 2564*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC7_CFG_SECTION 0x3800 2565*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6B50ull 2566*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800 2567*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC7_CFG_SECTION 0x3800 2568*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6B88ull 2569*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800 2570*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC7_CFG_SECTION 0x3800 2571*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC6BC0ull 2572*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800 2573*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC7_CFG_SECTION 0x3800 2574*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC6BF8ull 2575*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800 2576*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC7_CFG_SECTION 0x3800 2577*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6C30ull 2578*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800 2579*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC7_CFG_SECTION 0x3800 2580*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6C68ull 2581*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800 2582*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC7_CFG_SECTION 0x3800 2583*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC6CA0ull 2584*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800 2585*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC7_CFG_SECTION 0x3800 2586*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC6CD8ull 2587*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800 2588*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC7_CFG_SECTION 0x3800 2589*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6D10ull 2590*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800 2591*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC7_CFG_SECTION 0x3800 2592*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6D48ull 2593*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800 2594*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC7_CFG_SECTION 0x3800 2595*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6D80ull 2596*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000 2597*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000 2598*e65e175bSOded Gabbay #define mmQM_TPC7_CFG_BASE 0x7FFCFC6D88ull 2599*e65e175bSOded Gabbay #define QM_TPC7_CFG_MAX_OFFSET 0xB800 2600*e65e175bSOded Gabbay #define QM_TPC7_CFG_SECTION 0x2780 2601*e65e175bSOded Gabbay #define mmTPC7_E2E_CRED_BASE 0x7FFCFC7000ull 2602*e65e175bSOded Gabbay #define TPC7_E2E_CRED_MAX_OFFSET 0x1680 2603*e65e175bSOded Gabbay #define TPC7_E2E_CRED_SECTION 0x1000 2604*e65e175bSOded Gabbay #define mmTPC7_QM_BASE 0x7FFCFC8000ull 2605*e65e175bSOded Gabbay #define TPC7_QM_MAX_OFFSET 0xD040 2606*e65e175bSOded Gabbay #define TPC7_QM_SECTION 0x1038000 2607*e65e175bSOded Gabbay #define mmMME_S_ROM_TABLE_BASE 0x7FFE000000ull 2608*e65e175bSOded Gabbay #define MME_S_ROM_TABLE_MAX_OFFSET 0x1000 2609*e65e175bSOded Gabbay #define MME_S_ROM_TABLE_SECTION 0x21000 2610*e65e175bSOded Gabbay #define mmMME0_ACC_STM_BASE 0x7FFE021000ull 2611*e65e175bSOded Gabbay #define MME0_ACC_STM_MAX_OFFSET 0x1000 2612*e65e175bSOded Gabbay #define MME0_ACC_STM_SECTION 0x1000 2613*e65e175bSOded Gabbay #define mmMME0_ACC_CTI_BASE 0x7FFE022000ull 2614*e65e175bSOded Gabbay #define MME0_ACC_CTI_MAX_OFFSET 0x1000 2615*e65e175bSOded Gabbay #define MME0_ACC_CTI_SECTION 0x1000 2616*e65e175bSOded Gabbay #define mmMME0_ACC_ETF_BASE 0x7FFE023000ull 2617*e65e175bSOded Gabbay #define MME0_ACC_ETF_MAX_OFFSET 0x1000 2618*e65e175bSOded Gabbay #define MME0_ACC_ETF_SECTION 0x1000 2619*e65e175bSOded Gabbay #define mmMME0_ACC_SPMU_BASE 0x7FFE024000ull 2620*e65e175bSOded Gabbay #define MME0_ACC_SPMU_MAX_OFFSET 0x1000 2621*e65e175bSOded Gabbay #define MME0_ACC_SPMU_SECTION 0x1000 2622*e65e175bSOded Gabbay #define mmMME0_ACC_CTI0_BASE 0x7FFE025000ull 2623*e65e175bSOded Gabbay #define MME0_ACC_CTI0_MAX_OFFSET 0x1000 2624*e65e175bSOded Gabbay #define MME0_ACC_CTI0_SECTION 0x1000 2625*e65e175bSOded Gabbay #define mmMME0_ACC_CTI1_BASE 0x7FFE026000ull 2626*e65e175bSOded Gabbay #define MME0_ACC_CTI1_MAX_OFFSET 0x1000 2627*e65e175bSOded Gabbay #define MME0_ACC_CTI1_SECTION 0x1000 2628*e65e175bSOded Gabbay #define mmMME0_ACC_BMON0_BASE 0x7FFE027000ull 2629*e65e175bSOded Gabbay #define MME0_ACC_BMON0_MAX_OFFSET 0x1000 2630*e65e175bSOded Gabbay #define MME0_ACC_BMON0_SECTION 0x9000 2631*e65e175bSOded Gabbay #define mmMME0_ACC_FUNNEL_BASE 0x7FFE030000ull 2632*e65e175bSOded Gabbay #define MME0_ACC_FUNNEL_MAX_OFFSET 0x1000 2633*e65e175bSOded Gabbay #define MME0_ACC_FUNNEL_SECTION 0x11000 2634*e65e175bSOded Gabbay #define mmMME0_SBAB_STM_BASE 0x7FFE041000ull 2635*e65e175bSOded Gabbay #define MME0_SBAB_STM_MAX_OFFSET 0x1000 2636*e65e175bSOded Gabbay #define MME0_SBAB_STM_SECTION 0x1000 2637*e65e175bSOded Gabbay #define mmMME0_SBAB_CTI_BASE 0x7FFE042000ull 2638*e65e175bSOded Gabbay #define MME0_SBAB_CTI_MAX_OFFSET 0x1000 2639*e65e175bSOded Gabbay #define MME0_SBAB_CTI_SECTION 0x1000 2640*e65e175bSOded Gabbay #define mmMME0_SBAB_ETF_BASE 0x7FFE043000ull 2641*e65e175bSOded Gabbay #define MME0_SBAB_ETF_MAX_OFFSET 0x1000 2642*e65e175bSOded Gabbay #define MME0_SBAB_ETF_SECTION 0x1000 2643*e65e175bSOded Gabbay #define mmMME0_SBAB_SPMU_BASE 0x7FFE044000ull 2644*e65e175bSOded Gabbay #define MME0_SBAB_SPMU_MAX_OFFSET 0x1000 2645*e65e175bSOded Gabbay #define MME0_SBAB_SPMU_SECTION 0x1000 2646*e65e175bSOded Gabbay #define mmMME0_SBAB_CTI0_BASE 0x7FFE045000ull 2647*e65e175bSOded Gabbay #define MME0_SBAB_CTI0_MAX_OFFSET 0x1000 2648*e65e175bSOded Gabbay #define MME0_SBAB_CTI0_SECTION 0x1000 2649*e65e175bSOded Gabbay #define mmMME0_SBAB_CTI1_BASE 0x7FFE046000ull 2650*e65e175bSOded Gabbay #define MME0_SBAB_CTI1_MAX_OFFSET 0x1000 2651*e65e175bSOded Gabbay #define MME0_SBAB_CTI1_SECTION 0x1000 2652*e65e175bSOded Gabbay #define mmMME0_SBAB_BMON0_BASE 0x7FFE047000ull 2653*e65e175bSOded Gabbay #define MME0_SBAB_BMON0_MAX_OFFSET 0x1000 2654*e65e175bSOded Gabbay #define MME0_SBAB_BMON0_SECTION 0x1000 2655*e65e175bSOded Gabbay #define mmMME0_SBAB_BMON1_BASE 0x7FFE048000ull 2656*e65e175bSOded Gabbay #define MME0_SBAB_BMON1_MAX_OFFSET 0x1000 2657*e65e175bSOded Gabbay #define MME0_SBAB_BMON1_SECTION 0x19000 2658*e65e175bSOded Gabbay #define mmMME0_CTRL_STM_BASE 0x7FFE061000ull 2659*e65e175bSOded Gabbay #define MME0_CTRL_STM_MAX_OFFSET 0x1000 2660*e65e175bSOded Gabbay #define MME0_CTRL_STM_SECTION 0x1000 2661*e65e175bSOded Gabbay #define mmMME0_CTRL_CTI_BASE 0x7FFE062000ull 2662*e65e175bSOded Gabbay #define MME0_CTRL_CTI_MAX_OFFSET 0x1000 2663*e65e175bSOded Gabbay #define MME0_CTRL_CTI_SECTION 0x1000 2664*e65e175bSOded Gabbay #define mmMME0_CTRL_ETF_BASE 0x7FFE063000ull 2665*e65e175bSOded Gabbay #define MME0_CTRL_ETF_MAX_OFFSET 0x1000 2666*e65e175bSOded Gabbay #define MME0_CTRL_ETF_SECTION 0x1000 2667*e65e175bSOded Gabbay #define mmMME0_CTRL_SPMU_BASE 0x7FFE064000ull 2668*e65e175bSOded Gabbay #define MME0_CTRL_SPMU_MAX_OFFSET 0x1000 2669*e65e175bSOded Gabbay #define MME0_CTRL_SPMU_SECTION 0x1000 2670*e65e175bSOded Gabbay #define mmMME0_CTRL_CTI0_BASE 0x7FFE065000ull 2671*e65e175bSOded Gabbay #define MME0_CTRL_CTI0_MAX_OFFSET 0x1000 2672*e65e175bSOded Gabbay #define MME0_CTRL_CTI0_SECTION 0x1000 2673*e65e175bSOded Gabbay #define mmMME0_CTRL_CTI1_BASE 0x7FFE066000ull 2674*e65e175bSOded Gabbay #define MME0_CTRL_CTI1_MAX_OFFSET 0x1000 2675*e65e175bSOded Gabbay #define MME0_CTRL_CTI1_SECTION 0x1000 2676*e65e175bSOded Gabbay #define mmMME0_CTRL_BMON0_BASE 0x7FFE067000ull 2677*e65e175bSOded Gabbay #define MME0_CTRL_BMON0_MAX_OFFSET 0x1000 2678*e65e175bSOded Gabbay #define MME0_CTRL_BMON0_SECTION 0x1000 2679*e65e175bSOded Gabbay #define mmMME0_CTRL_BMON1_BASE 0x7FFE068000ull 2680*e65e175bSOded Gabbay #define MME0_CTRL_BMON1_MAX_OFFSET 0x1000 2681*e65e175bSOded Gabbay #define MME0_CTRL_BMON1_SECTION 0x39000 2682*e65e175bSOded Gabbay #define mmMME1_ACC_STM_BASE 0x7FFE0A1000ull 2683*e65e175bSOded Gabbay #define MME1_ACC_STM_MAX_OFFSET 0x1000 2684*e65e175bSOded Gabbay #define MME1_ACC_STM_SECTION 0x1000 2685*e65e175bSOded Gabbay #define mmMME1_ACC_CTI_BASE 0x7FFE0A2000ull 2686*e65e175bSOded Gabbay #define MME1_ACC_CTI_MAX_OFFSET 0x1000 2687*e65e175bSOded Gabbay #define MME1_ACC_CTI_SECTION 0x1000 2688*e65e175bSOded Gabbay #define mmMME1_ACC_ETF_BASE 0x7FFE0A3000ull 2689*e65e175bSOded Gabbay #define MME1_ACC_ETF_MAX_OFFSET 0x1000 2690*e65e175bSOded Gabbay #define MME1_ACC_ETF_SECTION 0x1000 2691*e65e175bSOded Gabbay #define mmMME1_ACC_SPMU_BASE 0x7FFE0A4000ull 2692*e65e175bSOded Gabbay #define MME1_ACC_SPMU_MAX_OFFSET 0x1000 2693*e65e175bSOded Gabbay #define MME1_ACC_SPMU_SECTION 0x1000 2694*e65e175bSOded Gabbay #define mmMME1_ACC_CTI0_BASE 0x7FFE0A5000ull 2695*e65e175bSOded Gabbay #define MME1_ACC_CTI0_MAX_OFFSET 0x1000 2696*e65e175bSOded Gabbay #define MME1_ACC_CTI0_SECTION 0x1000 2697*e65e175bSOded Gabbay #define mmMME1_ACC_CTI1_BASE 0x7FFE0A6000ull 2698*e65e175bSOded Gabbay #define MME1_ACC_CTI1_MAX_OFFSET 0x1000 2699*e65e175bSOded Gabbay #define MME1_ACC_CTI1_SECTION 0x1000 2700*e65e175bSOded Gabbay #define mmMME1_ACC_BMON0_BASE 0x7FFE0A7000ull 2701*e65e175bSOded Gabbay #define MME1_ACC_BMON0_MAX_OFFSET 0x1000 2702*e65e175bSOded Gabbay #define MME1_ACC_BMON0_SECTION 0x9000 2703*e65e175bSOded Gabbay #define mmMME1_ACC_FUNNEL_BASE 0x7FFE0B0000ull 2704*e65e175bSOded Gabbay #define MME1_ACC_FUNNEL_MAX_OFFSET 0x1000 2705*e65e175bSOded Gabbay #define MME1_ACC_FUNNEL_SECTION 0x11000 2706*e65e175bSOded Gabbay #define mmMME1_SBAB_STM_BASE 0x7FFE0C1000ull 2707*e65e175bSOded Gabbay #define MME1_SBAB_STM_MAX_OFFSET 0x1000 2708*e65e175bSOded Gabbay #define MME1_SBAB_STM_SECTION 0x1000 2709*e65e175bSOded Gabbay #define mmMME1_SBAB_CTI_BASE 0x7FFE0C2000ull 2710*e65e175bSOded Gabbay #define MME1_SBAB_CTI_MAX_OFFSET 0x1000 2711*e65e175bSOded Gabbay #define MME1_SBAB_CTI_SECTION 0x1000 2712*e65e175bSOded Gabbay #define mmMME1_SBAB_ETF_BASE 0x7FFE0C3000ull 2713*e65e175bSOded Gabbay #define MME1_SBAB_ETF_MAX_OFFSET 0x1000 2714*e65e175bSOded Gabbay #define MME1_SBAB_ETF_SECTION 0x1000 2715*e65e175bSOded Gabbay #define mmMME1_SBAB_SPMU_BASE 0x7FFE0C4000ull 2716*e65e175bSOded Gabbay #define MME1_SBAB_SPMU_MAX_OFFSET 0x1000 2717*e65e175bSOded Gabbay #define MME1_SBAB_SPMU_SECTION 0x1000 2718*e65e175bSOded Gabbay #define mmMME1_SBAB_CTI0_BASE 0x7FFE0C5000ull 2719*e65e175bSOded Gabbay #define MME1_SBAB_CTI0_MAX_OFFSET 0x1000 2720*e65e175bSOded Gabbay #define MME1_SBAB_CTI0_SECTION 0x1000 2721*e65e175bSOded Gabbay #define mmMME1_SBAB_CTI1_BASE 0x7FFE0C6000ull 2722*e65e175bSOded Gabbay #define MME1_SBAB_CTI1_MAX_OFFSET 0x1000 2723*e65e175bSOded Gabbay #define MME1_SBAB_CTI1_SECTION 0x1000 2724*e65e175bSOded Gabbay #define mmMME1_SBAB_BMON0_BASE 0x7FFE0C7000ull 2725*e65e175bSOded Gabbay #define MME1_SBAB_BMON0_MAX_OFFSET 0x1000 2726*e65e175bSOded Gabbay #define MME1_SBAB_BMON0_SECTION 0x1000 2727*e65e175bSOded Gabbay #define mmMME1_SBAB_BMON1_BASE 0x7FFE0C8000ull 2728*e65e175bSOded Gabbay #define MME1_SBAB_BMON1_MAX_OFFSET 0x1000 2729*e65e175bSOded Gabbay #define MME1_SBAB_BMON1_SECTION 0x19000 2730*e65e175bSOded Gabbay #define mmMME1_CTRL_STM_BASE 0x7FFE0E1000ull 2731*e65e175bSOded Gabbay #define MME1_CTRL_STM_MAX_OFFSET 0x1000 2732*e65e175bSOded Gabbay #define MME1_CTRL_STM_SECTION 0x1000 2733*e65e175bSOded Gabbay #define mmMME1_CTRL_CTI_BASE 0x7FFE0E2000ull 2734*e65e175bSOded Gabbay #define MME1_CTRL_CTI_MAX_OFFSET 0x1000 2735*e65e175bSOded Gabbay #define MME1_CTRL_CTI_SECTION 0x1000 2736*e65e175bSOded Gabbay #define mmMME1_CTRL_ETF_BASE 0x7FFE0E3000ull 2737*e65e175bSOded Gabbay #define MME1_CTRL_ETF_MAX_OFFSET 0x1000 2738*e65e175bSOded Gabbay #define MME1_CTRL_ETF_SECTION 0x1000 2739*e65e175bSOded Gabbay #define mmMME1_CTRL_SPMU_BASE 0x7FFE0E4000ull 2740*e65e175bSOded Gabbay #define MME1_CTRL_SPMU_MAX_OFFSET 0x1000 2741*e65e175bSOded Gabbay #define MME1_CTRL_SPMU_SECTION 0x1000 2742*e65e175bSOded Gabbay #define mmMME1_CTRL_CTI0_BASE 0x7FFE0E5000ull 2743*e65e175bSOded Gabbay #define MME1_CTRL_CTI0_MAX_OFFSET 0x1000 2744*e65e175bSOded Gabbay #define MME1_CTRL_CTI0_SECTION 0x1000 2745*e65e175bSOded Gabbay #define mmMME1_CTRL_CTI1_BASE 0x7FFE0E6000ull 2746*e65e175bSOded Gabbay #define MME1_CTRL_CTI1_MAX_OFFSET 0x1000 2747*e65e175bSOded Gabbay #define MME1_CTRL_CTI1_SECTION 0x1000 2748*e65e175bSOded Gabbay #define mmMME1_CTRL_BMON0_BASE 0x7FFE0E7000ull 2749*e65e175bSOded Gabbay #define MME1_CTRL_BMON0_MAX_OFFSET 0x1000 2750*e65e175bSOded Gabbay #define MME1_CTRL_BMON0_SECTION 0x1000 2751*e65e175bSOded Gabbay #define mmMME1_CTRL_BMON1_BASE 0x7FFE0E8000ull 2752*e65e175bSOded Gabbay #define MME1_CTRL_BMON1_MAX_OFFSET 0x1000 2753*e65e175bSOded Gabbay #define MME1_CTRL_BMON1_SECTION 0x18000 2754*e65e175bSOded Gabbay #define mmMME_N_ROM_TABLE_BASE 0x7FFE100000ull 2755*e65e175bSOded Gabbay #define MME_N_ROM_TABLE_MAX_OFFSET 0x1000 2756*e65e175bSOded Gabbay #define MME_N_ROM_TABLE_SECTION 0x21000 2757*e65e175bSOded Gabbay #define mmMME2_ACC_STM_BASE 0x7FFE121000ull 2758*e65e175bSOded Gabbay #define MME2_ACC_STM_MAX_OFFSET 0x1000 2759*e65e175bSOded Gabbay #define MME2_ACC_STM_SECTION 0x1000 2760*e65e175bSOded Gabbay #define mmMME2_ACC_CTI_BASE 0x7FFE122000ull 2761*e65e175bSOded Gabbay #define MME2_ACC_CTI_MAX_OFFSET 0x1000 2762*e65e175bSOded Gabbay #define MME2_ACC_CTI_SECTION 0x1000 2763*e65e175bSOded Gabbay #define mmMME2_MME2_ACC_ETF_BASE 0x7FFE123000ull 2764*e65e175bSOded Gabbay #define MME2_MME2_ACC_ETF_MAX_OFFSET 0x1000 2765*e65e175bSOded Gabbay #define MME2_MME2_ACC_ETF_SECTION 0x1000 2766*e65e175bSOded Gabbay #define mmMME2_ACC_SPMU_BASE 0x7FFE124000ull 2767*e65e175bSOded Gabbay #define MME2_ACC_SPMU_MAX_OFFSET 0x1000 2768*e65e175bSOded Gabbay #define MME2_ACC_SPMU_SECTION 0x1000 2769*e65e175bSOded Gabbay #define mmMME2_ACC_CTI0_BASE 0x7FFE125000ull 2770*e65e175bSOded Gabbay #define MME2_ACC_CTI0_MAX_OFFSET 0x1000 2771*e65e175bSOded Gabbay #define MME2_ACC_CTI0_SECTION 0x1000 2772*e65e175bSOded Gabbay #define mmMME2_ACC_CTI1_BASE 0x7FFE126000ull 2773*e65e175bSOded Gabbay #define MME2_ACC_CTI1_MAX_OFFSET 0x1000 2774*e65e175bSOded Gabbay #define MME2_ACC_CTI1_SECTION 0x1000 2775*e65e175bSOded Gabbay #define mmMME2_ACC_BMON0_BASE 0x7FFE127000ull 2776*e65e175bSOded Gabbay #define MME2_ACC_BMON0_MAX_OFFSET 0x1000 2777*e65e175bSOded Gabbay #define MME2_ACC_BMON0_SECTION 0x9000 2778*e65e175bSOded Gabbay #define mmMME2_ACC_FUNNEL_BASE 0x7FFE130000ull 2779*e65e175bSOded Gabbay #define MME2_ACC_FUNNEL_MAX_OFFSET 0x1000 2780*e65e175bSOded Gabbay #define MME2_ACC_FUNNEL_SECTION 0x11000 2781*e65e175bSOded Gabbay #define mmMME2_SBAB_STM_BASE 0x7FFE141000ull 2782*e65e175bSOded Gabbay #define MME2_SBAB_STM_MAX_OFFSET 0x1000 2783*e65e175bSOded Gabbay #define MME2_SBAB_STM_SECTION 0x1000 2784*e65e175bSOded Gabbay #define mmMME2_SBAB_CTI_BASE 0x7FFE142000ull 2785*e65e175bSOded Gabbay #define MME2_SBAB_CTI_MAX_OFFSET 0x1000 2786*e65e175bSOded Gabbay #define MME2_SBAB_CTI_SECTION 0x1000 2787*e65e175bSOded Gabbay #define mmMME2_SBAB_ETF_BASE 0x7FFE143000ull 2788*e65e175bSOded Gabbay #define MME2_SBAB_ETF_MAX_OFFSET 0x1000 2789*e65e175bSOded Gabbay #define MME2_SBAB_ETF_SECTION 0x1000 2790*e65e175bSOded Gabbay #define mmMME2_SBAB_SPMU_BASE 0x7FFE144000ull 2791*e65e175bSOded Gabbay #define MME2_SBAB_SPMU_MAX_OFFSET 0x1000 2792*e65e175bSOded Gabbay #define MME2_SBAB_SPMU_SECTION 0x1000 2793*e65e175bSOded Gabbay #define mmMME2_SBAB_CTI0_BASE 0x7FFE145000ull 2794*e65e175bSOded Gabbay #define MME2_SBAB_CTI0_MAX_OFFSET 0x1000 2795*e65e175bSOded Gabbay #define MME2_SBAB_CTI0_SECTION 0x1000 2796*e65e175bSOded Gabbay #define mmMME2_SBAB_CTI1_BASE 0x7FFE146000ull 2797*e65e175bSOded Gabbay #define MME2_SBAB_CTI1_MAX_OFFSET 0x1000 2798*e65e175bSOded Gabbay #define MME2_SBAB_CTI1_SECTION 0x1000 2799*e65e175bSOded Gabbay #define mmMME2_SBAB_BMON0_BASE 0x7FFE147000ull 2800*e65e175bSOded Gabbay #define MME2_SBAB_BMON0_MAX_OFFSET 0x1000 2801*e65e175bSOded Gabbay #define MME2_SBAB_BMON0_SECTION 0x1000 2802*e65e175bSOded Gabbay #define mmMME2_SBAB_BMON1_BASE 0x7FFE148000ull 2803*e65e175bSOded Gabbay #define MME2_SBAB_BMON1_MAX_OFFSET 0x1000 2804*e65e175bSOded Gabbay #define MME2_SBAB_BMON1_SECTION 0x19000 2805*e65e175bSOded Gabbay #define mmMME2_CTRL_STM_BASE 0x7FFE161000ull 2806*e65e175bSOded Gabbay #define MME2_CTRL_STM_MAX_OFFSET 0x1000 2807*e65e175bSOded Gabbay #define MME2_CTRL_STM_SECTION 0x1000 2808*e65e175bSOded Gabbay #define mmMME2_CTRL_CTI_BASE 0x7FFE162000ull 2809*e65e175bSOded Gabbay #define MME2_CTRL_CTI_MAX_OFFSET 0x1000 2810*e65e175bSOded Gabbay #define MME2_CTRL_CTI_SECTION 0x1000 2811*e65e175bSOded Gabbay #define mmMME2_CTRL_ETF_BASE 0x7FFE163000ull 2812*e65e175bSOded Gabbay #define MME2_CTRL_ETF_MAX_OFFSET 0x1000 2813*e65e175bSOded Gabbay #define MME2_CTRL_ETF_SECTION 0x1000 2814*e65e175bSOded Gabbay #define mmMME2_CTRL_SPMU_BASE 0x7FFE164000ull 2815*e65e175bSOded Gabbay #define MME2_CTRL_SPMU_MAX_OFFSET 0x1000 2816*e65e175bSOded Gabbay #define MME2_CTRL_SPMU_SECTION 0x1000 2817*e65e175bSOded Gabbay #define mmMME2_CTRL_CTI0_BASE 0x7FFE165000ull 2818*e65e175bSOded Gabbay #define MME2_CTRL_CTI0_MAX_OFFSET 0x1000 2819*e65e175bSOded Gabbay #define MME2_CTRL_CTI0_SECTION 0x1000 2820*e65e175bSOded Gabbay #define mmMME2_CTRL_CTI1_BASE 0x7FFE166000ull 2821*e65e175bSOded Gabbay #define MME2_CTRL_CTI1_MAX_OFFSET 0x1000 2822*e65e175bSOded Gabbay #define MME2_CTRL_CTI1_SECTION 0x1000 2823*e65e175bSOded Gabbay #define mmMME2_CTRL_BMON0_BASE 0x7FFE167000ull 2824*e65e175bSOded Gabbay #define MME2_CTRL_BMON0_MAX_OFFSET 0x1000 2825*e65e175bSOded Gabbay #define MME2_CTRL_BMON0_SECTION 0x1000 2826*e65e175bSOded Gabbay #define mmMME2_CTRL_BMON1_BASE 0x7FFE168000ull 2827*e65e175bSOded Gabbay #define MME2_CTRL_BMON1_MAX_OFFSET 0x1000 2828*e65e175bSOded Gabbay #define MME2_CTRL_BMON1_SECTION 0x39000 2829*e65e175bSOded Gabbay #define mmMME3_ACC_STM_BASE 0x7FFE1A1000ull 2830*e65e175bSOded Gabbay #define MME3_ACC_STM_MAX_OFFSET 0x1000 2831*e65e175bSOded Gabbay #define MME3_ACC_STM_SECTION 0x1000 2832*e65e175bSOded Gabbay #define mmMME3_ACC_CTI_BASE 0x7FFE1A2000ull 2833*e65e175bSOded Gabbay #define MME3_ACC_CTI_MAX_OFFSET 0x1000 2834*e65e175bSOded Gabbay #define MME3_ACC_CTI_SECTION 0x1000 2835*e65e175bSOded Gabbay #define mmMME3_ACC_ETF_BASE 0x7FFE1A3000ull 2836*e65e175bSOded Gabbay #define MME3_ACC_ETF_MAX_OFFSET 0x1000 2837*e65e175bSOded Gabbay #define MME3_ACC_ETF_SECTION 0x1000 2838*e65e175bSOded Gabbay #define mmMME3_ACC_SPMU_BASE 0x7FFE1A4000ull 2839*e65e175bSOded Gabbay #define MME3_ACC_SPMU_MAX_OFFSET 0x1000 2840*e65e175bSOded Gabbay #define MME3_ACC_SPMU_SECTION 0x1000 2841*e65e175bSOded Gabbay #define mmMME3_ACC_CTI0_BASE 0x7FFE1A5000ull 2842*e65e175bSOded Gabbay #define MME3_ACC_CTI0_MAX_OFFSET 0x1000 2843*e65e175bSOded Gabbay #define MME3_ACC_CTI0_SECTION 0x1000 2844*e65e175bSOded Gabbay #define mmMME3_ACC_CTI1_BASE 0x7FFE1A6000ull 2845*e65e175bSOded Gabbay #define MME3_ACC_CTI1_MAX_OFFSET 0x1000 2846*e65e175bSOded Gabbay #define MME3_ACC_CTI1_SECTION 0x1000 2847*e65e175bSOded Gabbay #define mmMME3_ACC_BMON0_BASE 0x7FFE1A7000ull 2848*e65e175bSOded Gabbay #define MME3_ACC_BMON0_MAX_OFFSET 0x1000 2849*e65e175bSOded Gabbay #define MME3_ACC_BMON0_SECTION 0x9000 2850*e65e175bSOded Gabbay #define mmMME3_ACC_FUNNEL_BASE 0x7FFE1B0000ull 2851*e65e175bSOded Gabbay #define MME3_ACC_FUNNEL_MAX_OFFSET 0x1000 2852*e65e175bSOded Gabbay #define MME3_ACC_FUNNEL_SECTION 0x11000 2853*e65e175bSOded Gabbay #define mmMME3_SBAB_STM_BASE 0x7FFE1C1000ull 2854*e65e175bSOded Gabbay #define MME3_SBAB_STM_MAX_OFFSET 0x1000 2855*e65e175bSOded Gabbay #define MME3_SBAB_STM_SECTION 0x1000 2856*e65e175bSOded Gabbay #define mmMME3_SBAB_CTI_BASE 0x7FFE1C2000ull 2857*e65e175bSOded Gabbay #define MME3_SBAB_CTI_MAX_OFFSET 0x1000 2858*e65e175bSOded Gabbay #define MME3_SBAB_CTI_SECTION 0x1000 2859*e65e175bSOded Gabbay #define mmMME3_SBAB_ETF_BASE 0x7FFE1C3000ull 2860*e65e175bSOded Gabbay #define MME3_SBAB_ETF_MAX_OFFSET 0x1000 2861*e65e175bSOded Gabbay #define MME3_SBAB_ETF_SECTION 0x1000 2862*e65e175bSOded Gabbay #define mmMME3_SBAB_SPMU_BASE 0x7FFE1C4000ull 2863*e65e175bSOded Gabbay #define MME3_SBAB_SPMU_MAX_OFFSET 0x1000 2864*e65e175bSOded Gabbay #define MME3_SBAB_SPMU_SECTION 0x1000 2865*e65e175bSOded Gabbay #define mmMME3_SBAB_CTI0_BASE 0x7FFE1C5000ull 2866*e65e175bSOded Gabbay #define MME3_SBAB_CTI0_MAX_OFFSET 0x1000 2867*e65e175bSOded Gabbay #define MME3_SBAB_CTI0_SECTION 0x1000 2868*e65e175bSOded Gabbay #define mmMME3_SBAB_CTI1_BASE 0x7FFE1C6000ull 2869*e65e175bSOded Gabbay #define MME3_SBAB_CTI1_MAX_OFFSET 0x1000 2870*e65e175bSOded Gabbay #define MME3_SBAB_CTI1_SECTION 0x1000 2871*e65e175bSOded Gabbay #define mmMME3_SBAB_BMON0_BASE 0x7FFE1C7000ull 2872*e65e175bSOded Gabbay #define MME3_SBAB_BMON0_MAX_OFFSET 0x1000 2873*e65e175bSOded Gabbay #define MME3_SBAB_BMON0_SECTION 0x1000 2874*e65e175bSOded Gabbay #define mmMME3_SBAB_BMON1_BASE 0x7FFE1C8000ull 2875*e65e175bSOded Gabbay #define MME3_SBAB_BMON1_MAX_OFFSET 0x1000 2876*e65e175bSOded Gabbay #define MME3_SBAB_BMON1_SECTION 0x19000 2877*e65e175bSOded Gabbay #define mmMME3_CTRL_STM_BASE 0x7FFE1E1000ull 2878*e65e175bSOded Gabbay #define MME3_CTRL_STM_MAX_OFFSET 0x1000 2879*e65e175bSOded Gabbay #define MME3_CTRL_STM_SECTION 0x1000 2880*e65e175bSOded Gabbay #define mmMME3_CTRL_CTI_BASE 0x7FFE1E2000ull 2881*e65e175bSOded Gabbay #define MME3_CTRL_CTI_MAX_OFFSET 0x1000 2882*e65e175bSOded Gabbay #define MME3_CTRL_CTI_SECTION 0x1000 2883*e65e175bSOded Gabbay #define mmMME3_CTRL_ETF_BASE 0x7FFE1E3000ull 2884*e65e175bSOded Gabbay #define MME3_CTRL_ETF_MAX_OFFSET 0x1000 2885*e65e175bSOded Gabbay #define MME3_CTRL_ETF_SECTION 0x1000 2886*e65e175bSOded Gabbay #define mmMME3_CTRL_SPMU_BASE 0x7FFE1E4000ull 2887*e65e175bSOded Gabbay #define MME3_CTRL_SPMU_MAX_OFFSET 0x1000 2888*e65e175bSOded Gabbay #define MME3_CTRL_SPMU_SECTION 0x1000 2889*e65e175bSOded Gabbay #define mmMME3_CTRL_CTI0_BASE 0x7FFE1E5000ull 2890*e65e175bSOded Gabbay #define MME3_CTRL_CTI0_MAX_OFFSET 0x1000 2891*e65e175bSOded Gabbay #define MME3_CTRL_CTI0_SECTION 0x1000 2892*e65e175bSOded Gabbay #define mmMME3_CTRL_CTI1_BASE 0x7FFE1E6000ull 2893*e65e175bSOded Gabbay #define MME3_CTRL_CTI1_MAX_OFFSET 0x1000 2894*e65e175bSOded Gabbay #define MME3_CTRL_CTI1_SECTION 0x1000 2895*e65e175bSOded Gabbay #define mmMME3_CTRL_BMON0_BASE 0x7FFE1E7000ull 2896*e65e175bSOded Gabbay #define MME3_CTRL_BMON0_MAX_OFFSET 0x1000 2897*e65e175bSOded Gabbay #define MME3_CTRL_BMON0_SECTION 0x1000 2898*e65e175bSOded Gabbay #define mmMME3_CTRL_BMON1_BASE 0x7FFE1E8000ull 2899*e65e175bSOded Gabbay #define MME3_CTRL_BMON1_MAX_OFFSET 0x1000 2900*e65e175bSOded Gabbay #define MME3_CTRL_BMON1_SECTION 0x18000 2901*e65e175bSOded Gabbay #define mmIC_ROM_TABLE_BASE 0x7FFE200000ull 2902*e65e175bSOded Gabbay #define IC_ROM_TABLE_MAX_OFFSET 0x1000 2903*e65e175bSOded Gabbay #define IC_ROM_TABLE_SECTION 0x1000 2904*e65e175bSOded Gabbay #define mmSRAM_Y0_X0_FUNNEL_BASE 0x7FFE201000ull 2905*e65e175bSOded Gabbay #define SRAM_Y0_X0_FUNNEL_MAX_OFFSET 0x1000 2906*e65e175bSOded Gabbay #define SRAM_Y0_X0_FUNNEL_SECTION 0x8000 2907*e65e175bSOded Gabbay #define mmSRAM_Y0_X1_FUNNEL_BASE 0x7FFE209000ull 2908*e65e175bSOded Gabbay #define SRAM_Y0_X1_FUNNEL_MAX_OFFSET 0x1000 2909*e65e175bSOded Gabbay #define SRAM_Y0_X1_FUNNEL_SECTION 0x8000 2910*e65e175bSOded Gabbay #define mmSRAM_Y0_X2_FUNNEL_BASE 0x7FFE211000ull 2911*e65e175bSOded Gabbay #define SRAM_Y0_X2_FUNNEL_MAX_OFFSET 0x1000 2912*e65e175bSOded Gabbay #define SRAM_Y0_X2_FUNNEL_SECTION 0x8000 2913*e65e175bSOded Gabbay #define mmSRAM_Y0_X3_FUNNEL_BASE 0x7FFE219000ull 2914*e65e175bSOded Gabbay #define SRAM_Y0_X3_FUNNEL_MAX_OFFSET 0x1000 2915*e65e175bSOded Gabbay #define SRAM_Y0_X3_FUNNEL_SECTION 0x8000 2916*e65e175bSOded Gabbay #define mmSRAM_Y0_X4_FUNNEL_BASE 0x7FFE221000ull 2917*e65e175bSOded Gabbay #define SRAM_Y0_X4_FUNNEL_MAX_OFFSET 0x1000 2918*e65e175bSOded Gabbay #define SRAM_Y0_X4_FUNNEL_SECTION 0x8000 2919*e65e175bSOded Gabbay #define mmSRAM_Y0_X5_FUNNEL_BASE 0x7FFE229000ull 2920*e65e175bSOded Gabbay #define SRAM_Y0_X5_FUNNEL_MAX_OFFSET 0x1000 2921*e65e175bSOded Gabbay #define SRAM_Y0_X5_FUNNEL_SECTION 0x8000 2922*e65e175bSOded Gabbay #define mmSRAM_Y0_X6_FUNNEL_BASE 0x7FFE231000ull 2923*e65e175bSOded Gabbay #define SRAM_Y0_X6_FUNNEL_MAX_OFFSET 0x1000 2924*e65e175bSOded Gabbay #define SRAM_Y0_X6_FUNNEL_SECTION 0x8000 2925*e65e175bSOded Gabbay #define mmSRAM_Y0_X7_FUNNEL_BASE 0x7FFE239000ull 2926*e65e175bSOded Gabbay #define SRAM_Y0_X7_FUNNEL_MAX_OFFSET 0x1000 2927*e65e175bSOded Gabbay #define SRAM_Y0_X7_FUNNEL_SECTION 0x8000 2928*e65e175bSOded Gabbay #define mmSRAM_Y1_X0_FUNNEL_BASE 0x7FFE241000ull 2929*e65e175bSOded Gabbay #define SRAM_Y1_X0_FUNNEL_MAX_OFFSET 0x1000 2930*e65e175bSOded Gabbay #define SRAM_Y1_X0_FUNNEL_SECTION 0x8000 2931*e65e175bSOded Gabbay #define mmSRAM_Y1_X1_FUNNEL_BASE 0x7FFE249000ull 2932*e65e175bSOded Gabbay #define SRAM_Y1_X1_FUNNEL_MAX_OFFSET 0x1000 2933*e65e175bSOded Gabbay #define SRAM_Y1_X1_FUNNEL_SECTION 0x8000 2934*e65e175bSOded Gabbay #define mmSRAM_Y1_X2_FUNNEL_BASE 0x7FFE251000ull 2935*e65e175bSOded Gabbay #define SRAM_Y1_X2_FUNNEL_MAX_OFFSET 0x1000 2936*e65e175bSOded Gabbay #define SRAM_Y1_X2_FUNNEL_SECTION 0x8000 2937*e65e175bSOded Gabbay #define mmSRAM_Y1_X3_FUNNEL_BASE 0x7FFE259000ull 2938*e65e175bSOded Gabbay #define SRAM_Y1_X3_FUNNEL_MAX_OFFSET 0x1000 2939*e65e175bSOded Gabbay #define SRAM_Y1_X3_FUNNEL_SECTION 0x8000 2940*e65e175bSOded Gabbay #define mmSRAM_Y1_X4_FUNNEL_BASE 0x7FFE261000ull 2941*e65e175bSOded Gabbay #define SRAM_Y1_X4_FUNNEL_MAX_OFFSET 0x1000 2942*e65e175bSOded Gabbay #define SRAM_Y1_X4_FUNNEL_SECTION 0x8000 2943*e65e175bSOded Gabbay #define mmSRAM_Y1_X5_FUNNEL_BASE 0x7FFE269000ull 2944*e65e175bSOded Gabbay #define SRAM_Y1_X5_FUNNEL_MAX_OFFSET 0x1000 2945*e65e175bSOded Gabbay #define SRAM_Y1_X5_FUNNEL_SECTION 0x8000 2946*e65e175bSOded Gabbay #define mmSRAM_Y1_X6_FUNNEL_BASE 0x7FFE271000ull 2947*e65e175bSOded Gabbay #define SRAM_Y1_X6_FUNNEL_MAX_OFFSET 0x1000 2948*e65e175bSOded Gabbay #define SRAM_Y1_X6_FUNNEL_SECTION 0x8000 2949*e65e175bSOded Gabbay #define mmSRAM_Y1_X7_FUNNEL_BASE 0x7FFE279000ull 2950*e65e175bSOded Gabbay #define SRAM_Y1_X7_FUNNEL_MAX_OFFSET 0x1000 2951*e65e175bSOded Gabbay #define SRAM_Y1_X7_FUNNEL_SECTION 0x8000 2952*e65e175bSOded Gabbay #define mmSRAM_Y2_X0_FUNNEL_BASE 0x7FFE281000ull 2953*e65e175bSOded Gabbay #define SRAM_Y2_X0_FUNNEL_MAX_OFFSET 0x1000 2954*e65e175bSOded Gabbay #define SRAM_Y2_X0_FUNNEL_SECTION 0x8000 2955*e65e175bSOded Gabbay #define mmSRAM_Y2_X1_FUNNEL_BASE 0x7FFE289000ull 2956*e65e175bSOded Gabbay #define SRAM_Y2_X1_FUNNEL_MAX_OFFSET 0x1000 2957*e65e175bSOded Gabbay #define SRAM_Y2_X1_FUNNEL_SECTION 0x8000 2958*e65e175bSOded Gabbay #define mmSRAM_Y2_X2_FUNNEL_BASE 0x7FFE291000ull 2959*e65e175bSOded Gabbay #define SRAM_Y2_X2_FUNNEL_MAX_OFFSET 0x1000 2960*e65e175bSOded Gabbay #define SRAM_Y2_X2_FUNNEL_SECTION 0x8000 2961*e65e175bSOded Gabbay #define mmSRAM_Y2_X3_FUNNEL_BASE 0x7FFE299000ull 2962*e65e175bSOded Gabbay #define SRAM_Y2_X3_FUNNEL_MAX_OFFSET 0x1000 2963*e65e175bSOded Gabbay #define SRAM_Y2_X3_FUNNEL_SECTION 0x8000 2964*e65e175bSOded Gabbay #define mmSRAM_Y2_X4_FUNNEL_BASE 0x7FFE2A1000ull 2965*e65e175bSOded Gabbay #define SRAM_Y2_X4_FUNNEL_MAX_OFFSET 0x1000 2966*e65e175bSOded Gabbay #define SRAM_Y2_X4_FUNNEL_SECTION 0x8000 2967*e65e175bSOded Gabbay #define mmSRAM_Y2_X5_FUNNEL_BASE 0x7FFE2A9000ull 2968*e65e175bSOded Gabbay #define SRAM_Y2_X5_FUNNEL_MAX_OFFSET 0x1000 2969*e65e175bSOded Gabbay #define SRAM_Y2_X5_FUNNEL_SECTION 0x8000 2970*e65e175bSOded Gabbay #define mmSRAM_Y2_X6_FUNNEL_BASE 0x7FFE2B1000ull 2971*e65e175bSOded Gabbay #define SRAM_Y2_X6_FUNNEL_MAX_OFFSET 0x1000 2972*e65e175bSOded Gabbay #define SRAM_Y2_X6_FUNNEL_SECTION 0x8000 2973*e65e175bSOded Gabbay #define mmSRAM_Y2_X7_FUNNEL_BASE 0x7FFE2B9000ull 2974*e65e175bSOded Gabbay #define SRAM_Y2_X7_FUNNEL_MAX_OFFSET 0x1000 2975*e65e175bSOded Gabbay #define SRAM_Y2_X7_FUNNEL_SECTION 0x8000 2976*e65e175bSOded Gabbay #define mmSRAM_Y3_X0_FUNNEL_BASE 0x7FFE2C1000ull 2977*e65e175bSOded Gabbay #define SRAM_Y3_X0_FUNNEL_MAX_OFFSET 0x1000 2978*e65e175bSOded Gabbay #define SRAM_Y3_X0_FUNNEL_SECTION 0x8000 2979*e65e175bSOded Gabbay #define mmSRAM_Y3_X1_FUNNEL_BASE 0x7FFE2C9000ull 2980*e65e175bSOded Gabbay #define SRAM_Y3_X1_FUNNEL_MAX_OFFSET 0x1000 2981*e65e175bSOded Gabbay #define SRAM_Y3_X1_FUNNEL_SECTION 0x8000 2982*e65e175bSOded Gabbay #define mmSRAM_Y3_X2_FUNNEL_BASE 0x7FFE2D1000ull 2983*e65e175bSOded Gabbay #define SRAM_Y3_X2_FUNNEL_MAX_OFFSET 0x1000 2984*e65e175bSOded Gabbay #define SRAM_Y3_X2_FUNNEL_SECTION 0x8000 2985*e65e175bSOded Gabbay #define mmSRAM_Y3_X4_FUNNEL_BASE 0x7FFE2D9000ull 2986*e65e175bSOded Gabbay #define SRAM_Y3_X4_FUNNEL_MAX_OFFSET 0x1000 2987*e65e175bSOded Gabbay #define SRAM_Y3_X4_FUNNEL_SECTION 0x8000 2988*e65e175bSOded Gabbay #define mmSRAM_Y3_X3_FUNNEL_BASE 0x7FFE2E1000ull 2989*e65e175bSOded Gabbay #define SRAM_Y3_X3_FUNNEL_MAX_OFFSET 0x1000 2990*e65e175bSOded Gabbay #define SRAM_Y3_X3_FUNNEL_SECTION 0x8000 2991*e65e175bSOded Gabbay #define mmSRAM_Y3_X5_FUNNEL_BASE 0x7FFE2E9000ull 2992*e65e175bSOded Gabbay #define SRAM_Y3_X5_FUNNEL_MAX_OFFSET 0x1000 2993*e65e175bSOded Gabbay #define SRAM_Y3_X5_FUNNEL_SECTION 0x8000 2994*e65e175bSOded Gabbay #define mmSRAM_Y3_X6_FUNNEL_BASE 0x7FFE2F1000ull 2995*e65e175bSOded Gabbay #define SRAM_Y3_X6_FUNNEL_MAX_OFFSET 0x1000 2996*e65e175bSOded Gabbay #define SRAM_Y3_X6_FUNNEL_SECTION 0x8000 2997*e65e175bSOded Gabbay #define mmSRAM_Y3_X7_FUNNEL_BASE 0x7FFE2F9000ull 2998*e65e175bSOded Gabbay #define SRAM_Y3_X7_FUNNEL_MAX_OFFSET 0x1000 2999*e65e175bSOded Gabbay #define SRAM_Y3_X7_FUNNEL_SECTION 0x7000 3000*e65e175bSOded Gabbay #define mmIF_ROM_TABLE_BASE 0x7FFE300000ull 3001*e65e175bSOded Gabbay #define IF_ROM_TABLE_MAX_OFFSET 0x1000 3002*e65e175bSOded Gabbay #define IF_ROM_TABLE_SECTION 0x1000 3003*e65e175bSOded Gabbay #define mmSIF_FUNNEL_0_BASE 0x7FFE301000ull 3004*e65e175bSOded Gabbay #define SIF_FUNNEL_0_MAX_OFFSET 0x1000 3005*e65e175bSOded Gabbay #define SIF_FUNNEL_0_SECTION 0x10000 3006*e65e175bSOded Gabbay #define mmSIF_FUNNEL_1_BASE 0x7FFE311000ull 3007*e65e175bSOded Gabbay #define SIF_FUNNEL_1_MAX_OFFSET 0x1000 3008*e65e175bSOded Gabbay #define SIF_FUNNEL_1_SECTION 0x10000 3009*e65e175bSOded Gabbay #define mmSIF_FUNNEL_2_BASE 0x7FFE321000ull 3010*e65e175bSOded Gabbay #define SIF_FUNNEL_2_MAX_OFFSET 0x1000 3011*e65e175bSOded Gabbay #define SIF_FUNNEL_2_SECTION 0x10000 3012*e65e175bSOded Gabbay #define mmSIF_FUNNEL_3_BASE 0x7FFE331000ull 3013*e65e175bSOded Gabbay #define SIF_FUNNEL_3_MAX_OFFSET 0x1000 3014*e65e175bSOded Gabbay #define SIF_FUNNEL_3_SECTION 0x10000 3015*e65e175bSOded Gabbay #define mmSIF_FUNNEL_4_BASE 0x7FFE341000ull 3016*e65e175bSOded Gabbay #define SIF_FUNNEL_4_MAX_OFFSET 0x1000 3017*e65e175bSOded Gabbay #define SIF_FUNNEL_4_SECTION 0x10000 3018*e65e175bSOded Gabbay #define mmSIF_FUNNEL_5_BASE 0x7FFE351000ull 3019*e65e175bSOded Gabbay #define SIF_FUNNEL_5_MAX_OFFSET 0x1000 3020*e65e175bSOded Gabbay #define SIF_FUNNEL_5_SECTION 0x10000 3021*e65e175bSOded Gabbay #define mmSIF_FUNNEL_6_BASE 0x7FFE361000ull 3022*e65e175bSOded Gabbay #define SIF_FUNNEL_6_MAX_OFFSET 0x1000 3023*e65e175bSOded Gabbay #define SIF_FUNNEL_6_SECTION 0x10000 3024*e65e175bSOded Gabbay #define mmSIF_FUNNEL_7_BASE 0x7FFE371000ull 3025*e65e175bSOded Gabbay #define SIF_FUNNEL_7_MAX_OFFSET 0x1000 3026*e65e175bSOded Gabbay #define SIF_FUNNEL_7_SECTION 0x10000 3027*e65e175bSOded Gabbay #define mmNIF_FUNNEL_0_BASE 0x7FFE381000ull 3028*e65e175bSOded Gabbay #define NIF_FUNNEL_0_MAX_OFFSET 0x1000 3029*e65e175bSOded Gabbay #define NIF_FUNNEL_0_SECTION 0x10000 3030*e65e175bSOded Gabbay #define mmNIF_FUNNEL_1_BASE 0x7FFE391000ull 3031*e65e175bSOded Gabbay #define NIF_FUNNEL_1_MAX_OFFSET 0x1000 3032*e65e175bSOded Gabbay #define NIF_FUNNEL_1_SECTION 0x10000 3033*e65e175bSOded Gabbay #define mmNIF_FUNNEL_2_BASE 0x7FFE3A1000ull 3034*e65e175bSOded Gabbay #define NIF_FUNNEL_2_MAX_OFFSET 0x1000 3035*e65e175bSOded Gabbay #define NIF_FUNNEL_2_SECTION 0x10000 3036*e65e175bSOded Gabbay #define mmNIF_FUNNEL_3_BASE 0x7FFE3B1000ull 3037*e65e175bSOded Gabbay #define NIF_FUNNEL_3_MAX_OFFSET 0x1000 3038*e65e175bSOded Gabbay #define NIF_FUNNEL_3_SECTION 0x10000 3039*e65e175bSOded Gabbay #define mmNIF_FUNNEL_4_BASE 0x7FFE3C1000ull 3040*e65e175bSOded Gabbay #define NIF_FUNNEL_4_MAX_OFFSET 0x1000 3041*e65e175bSOded Gabbay #define NIF_FUNNEL_4_SECTION 0x10000 3042*e65e175bSOded Gabbay #define mmNIF_FUNNEL_5_BASE 0x7FFE3D1000ull 3043*e65e175bSOded Gabbay #define NIF_FUNNEL_5_MAX_OFFSET 0x1000 3044*e65e175bSOded Gabbay #define NIF_FUNNEL_5_SECTION 0x10000 3045*e65e175bSOded Gabbay #define mmNIF_FUNNEL_6_BASE 0x7FFE3E1000ull 3046*e65e175bSOded Gabbay #define NIF_FUNNEL_6_MAX_OFFSET 0x1000 3047*e65e175bSOded Gabbay #define NIF_FUNNEL_6_SECTION 0x10000 3048*e65e175bSOded Gabbay #define mmNIF_FUNNEL_7_BASE 0x7FFE3F1000ull 3049*e65e175bSOded Gabbay #define NIF_FUNNEL_7_MAX_OFFSET 0x1000 3050*e65e175bSOded Gabbay #define NIF_FUNNEL_7_SECTION 0xF000 3051*e65e175bSOded Gabbay #define mmDMA_IF_ROM_TABLE_BASE 0x7FFE400000ull 3052*e65e175bSOded Gabbay #define DMA_IF_ROM_TABLE_MAX_OFFSET 0x1000 3053*e65e175bSOded Gabbay #define DMA_IF_ROM_TABLE_SECTION 0x1000 3054*e65e175bSOded Gabbay #define mmDMA_IF_W_S_STM_BASE 0x7FFE401000ull 3055*e65e175bSOded Gabbay #define DMA_IF_W_S_STM_MAX_OFFSET 0x1000 3056*e65e175bSOded Gabbay #define DMA_IF_W_S_STM_SECTION 0x1000 3057*e65e175bSOded Gabbay #define mmDMA_IF_W_S_CTI_BASE 0x7FFE402000ull 3058*e65e175bSOded Gabbay #define DMA_IF_W_S_CTI_MAX_OFFSET 0x1000 3059*e65e175bSOded Gabbay #define DMA_IF_W_S_CTI_SECTION 0x1000 3060*e65e175bSOded Gabbay #define mmDMA_IF_W_S_ETF_BASE 0x7FFE403000ull 3061*e65e175bSOded Gabbay #define DMA_IF_W_S_ETF_MAX_OFFSET 0x1000 3062*e65e175bSOded Gabbay #define DMA_IF_W_S_ETF_SECTION 0x2000 3063*e65e175bSOded Gabbay #define mmDMA_IF_W_S_BMON0_CTI_BASE 0x7FFE405000ull 3064*e65e175bSOded Gabbay #define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET 0x1000 3065*e65e175bSOded Gabbay #define DMA_IF_W_S_BMON0_CTI_SECTION 0x1000 3066*e65e175bSOded Gabbay #define mmDMA_IF_W_S_BMON1_CTI_BASE 0x7FFE406000ull 3067*e65e175bSOded Gabbay #define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET 0x1000 3068*e65e175bSOded Gabbay #define DMA_IF_W_S_BMON1_CTI_SECTION 0x1000 3069*e65e175bSOded Gabbay #define mmDMA_IF_W_S_HBM0_WR_BMON_BASE 0x7FFE407000ull 3070*e65e175bSOded Gabbay #define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 3071*e65e175bSOded Gabbay #define DMA_IF_W_S_HBM0_WR_BMON_SECTION 0x1000 3072*e65e175bSOded Gabbay #define mmDMA_IF_W_S_HBM0_RD_BMON_BASE 0x7FFE408000ull 3073*e65e175bSOded Gabbay #define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 3074*e65e175bSOded Gabbay #define DMA_IF_W_S_HBM0_RD_BMON_SECTION 0x1000 3075*e65e175bSOded Gabbay #define mmDMA_IF_W_S_HBM1_WR_BMON_BASE 0x7FFE409000ull 3076*e65e175bSOded Gabbay #define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 3077*e65e175bSOded Gabbay #define DMA_IF_W_S_HBM1_WR_BMON_SECTION 0x1000 3078*e65e175bSOded Gabbay #define mmDMA_IF_W_S_HBM1_RD_BMON_BASE 0x7FFE40A000ull 3079*e65e175bSOded Gabbay #define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 3080*e65e175bSOded Gabbay #define DMA_IF_W_S_HBM1_RD_BMON_SECTION 0x1000 3081*e65e175bSOded Gabbay #define mmDMA_IF_W_S_SOB_WR_BMON_BASE 0x7FFE40B000ull 3082*e65e175bSOded Gabbay #define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET 0x1000 3083*e65e175bSOded Gabbay #define DMA_IF_W_S_SOB_WR_BMON_SECTION 0x4000 3084*e65e175bSOded Gabbay #define mmDMA_IF_W_S_FUNNEL_BASE 0x7FFE40F000ull 3085*e65e175bSOded Gabbay #define DMA_IF_W_S_FUNNEL_MAX_OFFSET 0x1000 3086*e65e175bSOded Gabbay #define DMA_IF_W_S_FUNNEL_SECTION 0x12000 3087*e65e175bSOded Gabbay #define mmDMA_IF_E_S_STM_BASE 0x7FFE421000ull 3088*e65e175bSOded Gabbay #define DMA_IF_E_S_STM_MAX_OFFSET 0x1000 3089*e65e175bSOded Gabbay #define DMA_IF_E_S_STM_SECTION 0x1000 3090*e65e175bSOded Gabbay #define mmDMA_IF_E_S_CTI_BASE 0x7FFE422000ull 3091*e65e175bSOded Gabbay #define DMA_IF_E_S_CTI_MAX_OFFSET 0x1000 3092*e65e175bSOded Gabbay #define DMA_IF_E_S_CTI_SECTION 0x1000 3093*e65e175bSOded Gabbay #define mmDMA_IF_E_S_ETF_BASE 0x7FFE423000ull 3094*e65e175bSOded Gabbay #define DMA_IF_E_S_ETF_MAX_OFFSET 0x1000 3095*e65e175bSOded Gabbay #define DMA_IF_E_S_ETF_SECTION 0x2000 3096*e65e175bSOded Gabbay #define mmDMA_IF_E_S_BMON0_CTI_BASE 0x7FFE425000ull 3097*e65e175bSOded Gabbay #define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET 0x1000 3098*e65e175bSOded Gabbay #define DMA_IF_E_S_BMON0_CTI_SECTION 0x1000 3099*e65e175bSOded Gabbay #define mmDMA_IF_E_S_BMON1_CTI_BASE 0x7FFE426000ull 3100*e65e175bSOded Gabbay #define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET 0x1000 3101*e65e175bSOded Gabbay #define DMA_IF_E_S_BMON1_CTI_SECTION 0x1000 3102*e65e175bSOded Gabbay #define mmDMA_IF_E_S_HBM0_WR_BMON_BASE 0x7FFE427000ull 3103*e65e175bSOded Gabbay #define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET 0x1000 3104*e65e175bSOded Gabbay #define DMA_IF_E_S_HBM0_WR_BMON_SECTION 0x1000 3105*e65e175bSOded Gabbay #define mmDMA_IF_E_S_HBM0_RD_BMON_BASE 0x7FFE428000ull 3106*e65e175bSOded Gabbay #define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET 0x1000 3107*e65e175bSOded Gabbay #define DMA_IF_E_S_HBM0_RD_BMON_SECTION 0x1000 3108*e65e175bSOded Gabbay #define mmDMA_IF_E_S_HBM1_WR_BMON_BASE 0x7FFE429000ull 3109*e65e175bSOded Gabbay #define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET 0x1000 3110*e65e175bSOded Gabbay #define DMA_IF_E_S_HBM1_WR_BMON_SECTION 0x1000 3111*e65e175bSOded Gabbay #define mmDMA_IF_E_S_HBM1_RD_BMON_BASE 0x7FFE42A000ull 3112*e65e175bSOded Gabbay #define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET 0x1000 3113*e65e175bSOded Gabbay #define DMA_IF_E_S_HBM1_RD_BMON_SECTION 0x1000 3114*e65e175bSOded Gabbay #define mmDMA_IF_E_S_SOB_WR_BMON_BASE 0x7FFE42B000ull 3115*e65e175bSOded Gabbay #define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET 0x1000 3116*e65e175bSOded Gabbay #define DMA_IF_E_S_SOB_WR_BMON_SECTION 0x4000 3117*e65e175bSOded Gabbay #define mmDMA_IF_E_S_FUNNEL_BASE 0x7FFE42F000ull 3118*e65e175bSOded Gabbay #define DMA_IF_E_S_FUNNEL_MAX_OFFSET 0x1000 3119*e65e175bSOded Gabbay #define DMA_IF_E_S_FUNNEL_SECTION 0x12000 3120*e65e175bSOded Gabbay #define mmDMA_IF_W_N_STM_BASE 0x7FFE441000ull 3121*e65e175bSOded Gabbay #define DMA_IF_W_N_STM_MAX_OFFSET 0x1000 3122*e65e175bSOded Gabbay #define DMA_IF_W_N_STM_SECTION 0x1000 3123*e65e175bSOded Gabbay #define mmDMA_IF_W_N_CTI_BASE 0x7FFE442000ull 3124*e65e175bSOded Gabbay #define DMA_IF_W_N_CTI_MAX_OFFSET 0x1000 3125*e65e175bSOded Gabbay #define DMA_IF_W_N_CTI_SECTION 0x1000 3126*e65e175bSOded Gabbay #define mmDMA_IF_W_N_ETF_BASE 0x7FFE443000ull 3127*e65e175bSOded Gabbay #define DMA_IF_W_N_ETF_MAX_OFFSET 0x1000 3128*e65e175bSOded Gabbay #define DMA_IF_W_N_ETF_SECTION 0x2000 3129*e65e175bSOded Gabbay #define mmDMA_IF_W_N_BMON0_CTI_BASE 0x7FFE445000ull 3130*e65e175bSOded Gabbay #define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET 0x1000 3131*e65e175bSOded Gabbay #define DMA_IF_W_N_BMON0_CTI_SECTION 0x1000 3132*e65e175bSOded Gabbay #define mmDMA_IF_W_N_BMON1_CTI_BASE 0x7FFE446000ull 3133*e65e175bSOded Gabbay #define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET 0x1000 3134*e65e175bSOded Gabbay #define DMA_IF_W_N_BMON1_CTI_SECTION 0x1000 3135*e65e175bSOded Gabbay #define mmDMA_IF_W_N_HBM0_WR_BMON_BASE 0x7FFE447000ull 3136*e65e175bSOded Gabbay #define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 3137*e65e175bSOded Gabbay #define DMA_IF_W_N_HBM0_WR_BMON_SECTION 0x1000 3138*e65e175bSOded Gabbay #define mmDMA_IF_W_N_HBM0_RD_BMON_BASE 0x7FFE448000ull 3139*e65e175bSOded Gabbay #define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 3140*e65e175bSOded Gabbay #define DMA_IF_W_N_HBM0_RD_BMON_SECTION 0x1000 3141*e65e175bSOded Gabbay #define mmDMA_IF_W_N_HBM1_WR_BMON_BASE 0x7FFE449000ull 3142*e65e175bSOded Gabbay #define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 3143*e65e175bSOded Gabbay #define DMA_IF_W_N_HBM1_WR_BMON_SECTION 0x1000 3144*e65e175bSOded Gabbay #define mmDMA_IF_W_N_HBM1_RD_BMON_BASE 0x7FFE44A000ull 3145*e65e175bSOded Gabbay #define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 3146*e65e175bSOded Gabbay #define DMA_IF_W_N_HBM1_RD_BMON_SECTION 0x1000 3147*e65e175bSOded Gabbay #define mmDMA_IF_W_N_SOB_WR_BMON_BASE 0x7FFE44B000ull 3148*e65e175bSOded Gabbay #define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET 0x1000 3149*e65e175bSOded Gabbay #define DMA_IF_W_N_SOB_WR_BMON_SECTION 0x4000 3150*e65e175bSOded Gabbay #define mmDMA_IF_W_N_FUNNEL_BASE 0x7FFE44F000ull 3151*e65e175bSOded Gabbay #define DMA_IF_W_N_FUNNEL_MAX_OFFSET 0x1000 3152*e65e175bSOded Gabbay #define DMA_IF_W_N_FUNNEL_SECTION 0x12000 3153*e65e175bSOded Gabbay #define mmDMA_IF_E_N_STM_BASE 0x7FFE461000ull 3154*e65e175bSOded Gabbay #define DMA_IF_E_N_STM_MAX_OFFSET 0x1000 3155*e65e175bSOded Gabbay #define DMA_IF_E_N_STM_SECTION 0x1000 3156*e65e175bSOded Gabbay #define mmDMA_IF_E_N_CTI_BASE 0x7FFE462000ull 3157*e65e175bSOded Gabbay #define DMA_IF_E_N_CTI_MAX_OFFSET 0x1000 3158*e65e175bSOded Gabbay #define DMA_IF_E_N_CTI_SECTION 0x1000 3159*e65e175bSOded Gabbay #define mmDMA_IF_E_N_ETF_BASE 0x7FFE463000ull 3160*e65e175bSOded Gabbay #define DMA_IF_E_N_ETF_MAX_OFFSET 0x1000 3161*e65e175bSOded Gabbay #define DMA_IF_E_N_ETF_SECTION 0x2000 3162*e65e175bSOded Gabbay #define mmDMA_IF_E_N_BMON0_CTI_BASE 0x7FFE465000ull 3163*e65e175bSOded Gabbay #define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET 0x1000 3164*e65e175bSOded Gabbay #define DMA_IF_E_N_BMON0_CTI_SECTION 0x1000 3165*e65e175bSOded Gabbay #define mmDMA_IF_E_N_BMON1_CTI_BASE 0x7FFE466000ull 3166*e65e175bSOded Gabbay #define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET 0x1000 3167*e65e175bSOded Gabbay #define DMA_IF_E_N_BMON1_CTI_SECTION 0x1000 3168*e65e175bSOded Gabbay #define mmDMA_IF_E_N_HBM0_WR_BMON_BASE 0x7FFE467000ull 3169*e65e175bSOded Gabbay #define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET 0x1000 3170*e65e175bSOded Gabbay #define DMA_IF_E_N_HBM0_WR_BMON_SECTION 0x1000 3171*e65e175bSOded Gabbay #define mmDMA_IF_E_N_HBM0_RD_BMON_BASE 0x7FFE468000ull 3172*e65e175bSOded Gabbay #define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET 0x1000 3173*e65e175bSOded Gabbay #define DMA_IF_E_N_HBM0_RD_BMON_SECTION 0x1000 3174*e65e175bSOded Gabbay #define mmDMA_IF_E_N_HBM1_WR_BMON_BASE 0x7FFE469000ull 3175*e65e175bSOded Gabbay #define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET 0x1000 3176*e65e175bSOded Gabbay #define DMA_IF_E_N_HBM1_WR_BMON_SECTION 0x1000 3177*e65e175bSOded Gabbay #define mmDMA_IF_E_N_HBM1_RD_BMON_BASE 0x7FFE46A000ull 3178*e65e175bSOded Gabbay #define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET 0x1000 3179*e65e175bSOded Gabbay #define DMA_IF_E_N_HBM1_RD_BMON_SECTION 0x1000 3180*e65e175bSOded Gabbay #define mmDMA_IF_E_N_SOB_WR_BMON_BASE 0x7FFE46B000ull 3181*e65e175bSOded Gabbay #define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET 0x1000 3182*e65e175bSOded Gabbay #define DMA_IF_E_N_SOB_WR_BMON_SECTION 0x4000 3183*e65e175bSOded Gabbay #define mmDMA_IF_E_N_FUNNEL_BASE 0x7FFE46F000ull 3184*e65e175bSOded Gabbay #define DMA_IF_E_N_FUNNEL_MAX_OFFSET 0x1000 3185*e65e175bSOded Gabbay #define DMA_IF_E_N_FUNNEL_SECTION 0x11000 3186*e65e175bSOded Gabbay #define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull 3187*e65e175bSOded Gabbay #define CPU_ROM_TABLE_MAX_OFFSET 0x1000 3188*e65e175bSOded Gabbay #define CPU_ROM_TABLE_SECTION 0x1000 3189*e65e175bSOded Gabbay #define mmCPU_ETF_0_BASE 0x7FFE481000ull 3190*e65e175bSOded Gabbay #define CPU_ETF_0_MAX_OFFSET 0x1000 3191*e65e175bSOded Gabbay #define CPU_ETF_0_SECTION 0x1000 3192*e65e175bSOded Gabbay #define mmCPU_ETF_1_BASE 0x7FFE482000ull 3193*e65e175bSOded Gabbay #define CPU_ETF_1_MAX_OFFSET 0x1000 3194*e65e175bSOded Gabbay #define CPU_ETF_1_SECTION 0x2000 3195*e65e175bSOded Gabbay #define mmCPU_CTI_BASE 0x7FFE484000ull 3196*e65e175bSOded Gabbay #define CPU_CTI_MAX_OFFSET 0x1000 3197*e65e175bSOded Gabbay #define CPU_CTI_SECTION 0x1000 3198*e65e175bSOded Gabbay #define mmCPU_FUNNEL_BASE 0x7FFE485000ull 3199*e65e175bSOded Gabbay #define CPU_FUNNEL_MAX_OFFSET 0x1000 3200*e65e175bSOded Gabbay #define CPU_FUNNEL_SECTION 0x1000 3201*e65e175bSOded Gabbay #define mmCPU_STM_BASE 0x7FFE486000ull 3202*e65e175bSOded Gabbay #define CPU_STM_MAX_OFFSET 0x1000 3203*e65e175bSOded Gabbay #define CPU_STM_SECTION 0x1000 3204*e65e175bSOded Gabbay #define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull 3205*e65e175bSOded Gabbay #define CPU_CTI_TRACE_MAX_OFFSET 0x1000 3206*e65e175bSOded Gabbay #define CPU_CTI_TRACE_SECTION 0x1000 3207*e65e175bSOded Gabbay #define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull 3208*e65e175bSOded Gabbay #define CPU_ETF_TRACE_MAX_OFFSET 0x1000 3209*e65e175bSOded Gabbay #define CPU_ETF_TRACE_SECTION 0x1000 3210*e65e175bSOded Gabbay #define mmCPU_WR_BMON_BASE 0x7FFE489000ull 3211*e65e175bSOded Gabbay #define CPU_WR_BMON_MAX_OFFSET 0x1000 3212*e65e175bSOded Gabbay #define CPU_WR_BMON_SECTION 0x1000 3213*e65e175bSOded Gabbay #define mmCPU_RD_BMON_BASE 0x7FFE48A000ull 3214*e65e175bSOded Gabbay #define CPU_RD_BMON_MAX_OFFSET 0x1000 3215*e65e175bSOded Gabbay #define CPU_RD_BMON_SECTION 0x76000 3216*e65e175bSOded Gabbay #define mmDMA_ROM_TABLE_BASE 0x7FFE500000ull 3217*e65e175bSOded Gabbay #define DMA_ROM_TABLE_MAX_OFFSET 0x1000 3218*e65e175bSOded Gabbay #define DMA_ROM_TABLE_SECTION 0x1000 3219*e65e175bSOded Gabbay #define mmDMA_CH_0_CS_STM_BASE 0x7FFE501000ull 3220*e65e175bSOded Gabbay #define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000 3221*e65e175bSOded Gabbay #define DMA_CH_0_CS_STM_SECTION 0x1000 3222*e65e175bSOded Gabbay #define mmDMA_CH_0_CS_CTI_BASE 0x7FFE502000ull 3223*e65e175bSOded Gabbay #define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000 3224*e65e175bSOded Gabbay #define DMA_CH_0_CS_CTI_SECTION 0x1000 3225*e65e175bSOded Gabbay #define mmDMA_CH_0_CS_ETF_BASE 0x7FFE503000ull 3226*e65e175bSOded Gabbay #define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000 3227*e65e175bSOded Gabbay #define DMA_CH_0_CS_ETF_SECTION 0x1000 3228*e65e175bSOded Gabbay #define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE504000ull 3229*e65e175bSOded Gabbay #define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000 3230*e65e175bSOded Gabbay #define DMA_CH_0_CS_SPMU_SECTION 0x1000 3231*e65e175bSOded Gabbay #define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE505000ull 3232*e65e175bSOded Gabbay #define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000 3233*e65e175bSOded Gabbay #define DMA_CH_0_BMON_CTI_SECTION 0x1000 3234*e65e175bSOded Gabbay #define mmDMA_CH_0_USER_CTI_BASE 0x7FFE506000ull 3235*e65e175bSOded Gabbay #define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000 3236*e65e175bSOded Gabbay #define DMA_CH_0_USER_CTI_SECTION 0x1000 3237*e65e175bSOded Gabbay #define mmDMA_CH_0_BMON_0_BASE 0x7FFE507000ull 3238*e65e175bSOded Gabbay #define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000 3239*e65e175bSOded Gabbay #define DMA_CH_0_BMON_0_SECTION 0x1000 3240*e65e175bSOded Gabbay #define mmDMA_CH_0_BMON_1_BASE 0x7FFE508000ull 3241*e65e175bSOded Gabbay #define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000 3242*e65e175bSOded Gabbay #define DMA_CH_0_BMON_1_SECTION 0x19000 3243*e65e175bSOded Gabbay #define mmDMA_CH_1_CS_STM_BASE 0x7FFE521000ull 3244*e65e175bSOded Gabbay #define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000 3245*e65e175bSOded Gabbay #define DMA_CH_1_CS_STM_SECTION 0x1000 3246*e65e175bSOded Gabbay #define mmDMA_CH_1_CS_CTI_BASE 0x7FFE522000ull 3247*e65e175bSOded Gabbay #define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000 3248*e65e175bSOded Gabbay #define DMA_CH_1_CS_CTI_SECTION 0x1000 3249*e65e175bSOded Gabbay #define mmDMA_CH_1_CS_ETF_BASE 0x7FFE523000ull 3250*e65e175bSOded Gabbay #define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000 3251*e65e175bSOded Gabbay #define DMA_CH_1_CS_ETF_SECTION 0x1000 3252*e65e175bSOded Gabbay #define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE524000ull 3253*e65e175bSOded Gabbay #define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000 3254*e65e175bSOded Gabbay #define DMA_CH_1_CS_SPMU_SECTION 0x1000 3255*e65e175bSOded Gabbay #define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE525000ull 3256*e65e175bSOded Gabbay #define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000 3257*e65e175bSOded Gabbay #define DMA_CH_1_BMON_CTI_SECTION 0x1000 3258*e65e175bSOded Gabbay #define mmDMA_CH_1_USER_CTI_BASE 0x7FFE526000ull 3259*e65e175bSOded Gabbay #define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000 3260*e65e175bSOded Gabbay #define DMA_CH_1_USER_CTI_SECTION 0x1000 3261*e65e175bSOded Gabbay #define mmDMA_CH_1_BMON_0_BASE 0x7FFE527000ull 3262*e65e175bSOded Gabbay #define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000 3263*e65e175bSOded Gabbay #define DMA_CH_1_BMON_0_SECTION 0x1000 3264*e65e175bSOded Gabbay #define mmDMA_CH_1_BMON_1_BASE 0x7FFE528000ull 3265*e65e175bSOded Gabbay #define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000 3266*e65e175bSOded Gabbay #define DMA_CH_1_BMON_1_SECTION 0x19000 3267*e65e175bSOded Gabbay #define mmDMA_CH_2_CS_STM_BASE 0x7FFE541000ull 3268*e65e175bSOded Gabbay #define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000 3269*e65e175bSOded Gabbay #define DMA_CH_2_CS_STM_SECTION 0x1000 3270*e65e175bSOded Gabbay #define mmDMA_CH_2_CS_CTI_BASE 0x7FFE542000ull 3271*e65e175bSOded Gabbay #define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000 3272*e65e175bSOded Gabbay #define DMA_CH_2_CS_CTI_SECTION 0x1000 3273*e65e175bSOded Gabbay #define mmDMA_CH_2_CS_ETF_BASE 0x7FFE543000ull 3274*e65e175bSOded Gabbay #define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000 3275*e65e175bSOded Gabbay #define DMA_CH_2_CS_ETF_SECTION 0x1000 3276*e65e175bSOded Gabbay #define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE544000ull 3277*e65e175bSOded Gabbay #define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000 3278*e65e175bSOded Gabbay #define DMA_CH_2_CS_SPMU_SECTION 0x1000 3279*e65e175bSOded Gabbay #define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE545000ull 3280*e65e175bSOded Gabbay #define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000 3281*e65e175bSOded Gabbay #define DMA_CH_2_BMON_CTI_SECTION 0x1000 3282*e65e175bSOded Gabbay #define mmDMA_CH_2_USER_CTI_BASE 0x7FFE546000ull 3283*e65e175bSOded Gabbay #define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000 3284*e65e175bSOded Gabbay #define DMA_CH_2_USER_CTI_SECTION 0x1000 3285*e65e175bSOded Gabbay #define mmDMA_CH_2_BMON_0_BASE 0x7FFE547000ull 3286*e65e175bSOded Gabbay #define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000 3287*e65e175bSOded Gabbay #define DMA_CH_2_BMON_0_SECTION 0x1000 3288*e65e175bSOded Gabbay #define mmDMA_CH_2_BMON_1_BASE 0x7FFE548000ull 3289*e65e175bSOded Gabbay #define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000 3290*e65e175bSOded Gabbay #define DMA_CH_2_BMON_1_SECTION 0x19000 3291*e65e175bSOded Gabbay #define mmDMA_CH_3_CS_STM_BASE 0x7FFE561000ull 3292*e65e175bSOded Gabbay #define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000 3293*e65e175bSOded Gabbay #define DMA_CH_3_CS_STM_SECTION 0x1000 3294*e65e175bSOded Gabbay #define mmDMA_CH_3_CS_CTI_BASE 0x7FFE562000ull 3295*e65e175bSOded Gabbay #define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000 3296*e65e175bSOded Gabbay #define DMA_CH_3_CS_CTI_SECTION 0x1000 3297*e65e175bSOded Gabbay #define mmDMA_CH_3_CS_ETF_BASE 0x7FFE563000ull 3298*e65e175bSOded Gabbay #define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000 3299*e65e175bSOded Gabbay #define DMA_CH_3_CS_ETF_SECTION 0x1000 3300*e65e175bSOded Gabbay #define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE564000ull 3301*e65e175bSOded Gabbay #define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000 3302*e65e175bSOded Gabbay #define DMA_CH_3_CS_SPMU_SECTION 0x1000 3303*e65e175bSOded Gabbay #define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE565000ull 3304*e65e175bSOded Gabbay #define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000 3305*e65e175bSOded Gabbay #define DMA_CH_3_BMON_CTI_SECTION 0x1000 3306*e65e175bSOded Gabbay #define mmDMA_CH_3_USER_CTI_BASE 0x7FFE566000ull 3307*e65e175bSOded Gabbay #define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000 3308*e65e175bSOded Gabbay #define DMA_CH_3_USER_CTI_SECTION 0x1000 3309*e65e175bSOded Gabbay #define mmDMA_CH_3_BMON_0_BASE 0x7FFE567000ull 3310*e65e175bSOded Gabbay #define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000 3311*e65e175bSOded Gabbay #define DMA_CH_3_BMON_0_SECTION 0x1000 3312*e65e175bSOded Gabbay #define mmDMA_CH_3_BMON_1_BASE 0x7FFE568000ull 3313*e65e175bSOded Gabbay #define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000 3314*e65e175bSOded Gabbay #define DMA_CH_3_BMON_1_SECTION 0x19000 3315*e65e175bSOded Gabbay #define mmDMA_CH_4_CS_STM_BASE 0x7FFE581000ull 3316*e65e175bSOded Gabbay #define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000 3317*e65e175bSOded Gabbay #define DMA_CH_4_CS_STM_SECTION 0x1000 3318*e65e175bSOded Gabbay #define mmDMA_CH_4_CS_CTI_BASE 0x7FFE582000ull 3319*e65e175bSOded Gabbay #define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000 3320*e65e175bSOded Gabbay #define DMA_CH_4_CS_CTI_SECTION 0x1000 3321*e65e175bSOded Gabbay #define mmDMA_CH_4_CS_ETF_BASE 0x7FFE583000ull 3322*e65e175bSOded Gabbay #define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000 3323*e65e175bSOded Gabbay #define DMA_CH_4_CS_ETF_SECTION 0x1000 3324*e65e175bSOded Gabbay #define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE584000ull 3325*e65e175bSOded Gabbay #define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000 3326*e65e175bSOded Gabbay #define DMA_CH_4_CS_SPMU_SECTION 0x1000 3327*e65e175bSOded Gabbay #define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE585000ull 3328*e65e175bSOded Gabbay #define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000 3329*e65e175bSOded Gabbay #define DMA_CH_4_BMON_CTI_SECTION 0x1000 3330*e65e175bSOded Gabbay #define mmDMA_CH_4_USER_CTI_BASE 0x7FFE586000ull 3331*e65e175bSOded Gabbay #define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000 3332*e65e175bSOded Gabbay #define DMA_CH_4_USER_CTI_SECTION 0x1000 3333*e65e175bSOded Gabbay #define mmDMA_CH_4_BMON_0_BASE 0x7FFE587000ull 3334*e65e175bSOded Gabbay #define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000 3335*e65e175bSOded Gabbay #define DMA_CH_4_BMON_0_SECTION 0x1000 3336*e65e175bSOded Gabbay #define mmDMA_CH_4_BMON_1_BASE 0x7FFE588000ull 3337*e65e175bSOded Gabbay #define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000 3338*e65e175bSOded Gabbay #define DMA_CH_4_BMON_1_SECTION 0x19000 3339*e65e175bSOded Gabbay #define mmDMA_CH_5_CS_STM_BASE 0x7FFE5A1000ull 3340*e65e175bSOded Gabbay #define DMA_CH_5_CS_STM_MAX_OFFSET 0x1000 3341*e65e175bSOded Gabbay #define DMA_CH_5_CS_STM_SECTION 0x1000 3342*e65e175bSOded Gabbay #define mmDMA_CH_5_CS_CTI_BASE 0x7FFE5A2000ull 3343*e65e175bSOded Gabbay #define DMA_CH_5_CS_CTI_MAX_OFFSET 0x1000 3344*e65e175bSOded Gabbay #define DMA_CH_5_CS_CTI_SECTION 0x1000 3345*e65e175bSOded Gabbay #define mmDMA_CH_5_CS_ETF_BASE 0x7FFE5A3000ull 3346*e65e175bSOded Gabbay #define DMA_CH_5_CS_ETF_MAX_OFFSET 0x1000 3347*e65e175bSOded Gabbay #define DMA_CH_5_CS_ETF_SECTION 0x1000 3348*e65e175bSOded Gabbay #define mmDMA_CH_5_CS_SPMU_BASE 0x7FFE5A4000ull 3349*e65e175bSOded Gabbay #define DMA_CH_5_CS_SPMU_MAX_OFFSET 0x1000 3350*e65e175bSOded Gabbay #define DMA_CH_5_CS_SPMU_SECTION 0x1000 3351*e65e175bSOded Gabbay #define mmDMA_CH_5_BMON_CTI_BASE 0x7FFE5A5000ull 3352*e65e175bSOded Gabbay #define DMA_CH_5_BMON_CTI_MAX_OFFSET 0x1000 3353*e65e175bSOded Gabbay #define DMA_CH_5_BMON_CTI_SECTION 0x1000 3354*e65e175bSOded Gabbay #define mmDMA_CH_5_USER_CTI_BASE 0x7FFE5A6000ull 3355*e65e175bSOded Gabbay #define DMA_CH_5_USER_CTI_MAX_OFFSET 0x1000 3356*e65e175bSOded Gabbay #define DMA_CH_5_USER_CTI_SECTION 0x1000 3357*e65e175bSOded Gabbay #define mmDMA_CH_5_BMON_0_BASE 0x7FFE5A7000ull 3358*e65e175bSOded Gabbay #define DMA_CH_5_BMON_0_MAX_OFFSET 0x1000 3359*e65e175bSOded Gabbay #define DMA_CH_5_BMON_0_SECTION 0x1000 3360*e65e175bSOded Gabbay #define mmDMA_CH_5_BMON_1_BASE 0x7FFE5A8000ull 3361*e65e175bSOded Gabbay #define DMA_CH_5_BMON_1_MAX_OFFSET 0x1000 3362*e65e175bSOded Gabbay #define DMA_CH_5_BMON_1_SECTION 0x19000 3363*e65e175bSOded Gabbay #define mmDMA_CH_6_CS_STM_BASE 0x7FFE5C1000ull 3364*e65e175bSOded Gabbay #define DMA_CH_6_CS_STM_MAX_OFFSET 0x1000 3365*e65e175bSOded Gabbay #define DMA_CH_6_CS_STM_SECTION 0x1000 3366*e65e175bSOded Gabbay #define mmDMA_CH_6_CS_CTI_BASE 0x7FFE5C2000ull 3367*e65e175bSOded Gabbay #define DMA_CH_6_CS_CTI_MAX_OFFSET 0x1000 3368*e65e175bSOded Gabbay #define DMA_CH_6_CS_CTI_SECTION 0x1000 3369*e65e175bSOded Gabbay #define mmDMA_CH_6_CS_ETF_BASE 0x7FFE5C3000ull 3370*e65e175bSOded Gabbay #define DMA_CH_6_CS_ETF_MAX_OFFSET 0x1000 3371*e65e175bSOded Gabbay #define DMA_CH_6_CS_ETF_SECTION 0x1000 3372*e65e175bSOded Gabbay #define mmDMA_CH_6_CS_SPMU_BASE 0x7FFE5C4000ull 3373*e65e175bSOded Gabbay #define DMA_CH_6_CS_SPMU_MAX_OFFSET 0x1000 3374*e65e175bSOded Gabbay #define DMA_CH_6_CS_SPMU_SECTION 0x1000 3375*e65e175bSOded Gabbay #define mmDMA_CH_6_BMON_CTI_BASE 0x7FFE5C5000ull 3376*e65e175bSOded Gabbay #define DMA_CH_6_BMON_CTI_MAX_OFFSET 0x1000 3377*e65e175bSOded Gabbay #define DMA_CH_6_BMON_CTI_SECTION 0x1000 3378*e65e175bSOded Gabbay #define mmDMA_CH_6_USER_CTI_BASE 0x7FFE5C6000ull 3379*e65e175bSOded Gabbay #define DMA_CH_6_USER_CTI_MAX_OFFSET 0x1000 3380*e65e175bSOded Gabbay #define DMA_CH_6_USER_CTI_SECTION 0x1000 3381*e65e175bSOded Gabbay #define mmDMA_CH_6_BMON_0_BASE 0x7FFE5C7000ull 3382*e65e175bSOded Gabbay #define DMA_CH_6_BMON_0_MAX_OFFSET 0x1000 3383*e65e175bSOded Gabbay #define DMA_CH_6_BMON_0_SECTION 0x1000 3384*e65e175bSOded Gabbay #define mmDMA_CH_6_BMON_1_BASE 0x7FFE5C8000ull 3385*e65e175bSOded Gabbay #define DMA_CH_6_BMON_1_MAX_OFFSET 0x1000 3386*e65e175bSOded Gabbay #define DMA_CH_6_BMON_1_SECTION 0x19000 3387*e65e175bSOded Gabbay #define mmDMA_CH_7_CS_STM_BASE 0x7FFE5E1000ull 3388*e65e175bSOded Gabbay #define DMA_CH_7_CS_STM_MAX_OFFSET 0x1000 3389*e65e175bSOded Gabbay #define DMA_CH_7_CS_STM_SECTION 0x1000 3390*e65e175bSOded Gabbay #define mmDMA_CH_7_CS_CTI_BASE 0x7FFE5E2000ull 3391*e65e175bSOded Gabbay #define DMA_CH_7_CS_CTI_MAX_OFFSET 0x1000 3392*e65e175bSOded Gabbay #define DMA_CH_7_CS_CTI_SECTION 0x1000 3393*e65e175bSOded Gabbay #define mmDMA_CH_7_CS_ETF_BASE 0x7FFE5E3000ull 3394*e65e175bSOded Gabbay #define DMA_CH_7_CS_ETF_MAX_OFFSET 0x1000 3395*e65e175bSOded Gabbay #define DMA_CH_7_CS_ETF_SECTION 0x1000 3396*e65e175bSOded Gabbay #define mmDMA_CH_7_CS_SPMU_BASE 0x7FFE5E4000ull 3397*e65e175bSOded Gabbay #define DMA_CH_7_CS_SPMU_MAX_OFFSET 0x1000 3398*e65e175bSOded Gabbay #define DMA_CH_7_CS_SPMU_SECTION 0x1000 3399*e65e175bSOded Gabbay #define mmDMA_CH_7_BMON_CTI_BASE 0x7FFE5E5000ull 3400*e65e175bSOded Gabbay #define DMA_CH_7_BMON_CTI_MAX_OFFSET 0x1000 3401*e65e175bSOded Gabbay #define DMA_CH_7_BMON_CTI_SECTION 0x1000 3402*e65e175bSOded Gabbay #define mmDMA_CH_7_USER_CTI_BASE 0x7FFE5E6000ull 3403*e65e175bSOded Gabbay #define DMA_CH_7_USER_CTI_MAX_OFFSET 0x1000 3404*e65e175bSOded Gabbay #define DMA_CH_7_USER_CTI_SECTION 0x1000 3405*e65e175bSOded Gabbay #define mmDMA_CH_7_BMON_0_BASE 0x7FFE5E7000ull 3406*e65e175bSOded Gabbay #define DMA_CH_7_BMON_0_MAX_OFFSET 0x1000 3407*e65e175bSOded Gabbay #define DMA_CH_7_BMON_0_SECTION 0x1000 3408*e65e175bSOded Gabbay #define mmDMA_CH_7_BMON_1_BASE 0x7FFE5E8000ull 3409*e65e175bSOded Gabbay #define DMA_CH_7_BMON_1_MAX_OFFSET 0x1000 3410*e65e175bSOded Gabbay #define DMA_CH_7_BMON_1_SECTION 0x18000 3411*e65e175bSOded Gabbay #define mmNIC_TPC_FUNNEL_W_S_BASE 0x7FFE600000ull 3412*e65e175bSOded Gabbay #define NIC_TPC_FUNNEL_W_S_MAX_OFFSET 0x1000 3413*e65e175bSOded Gabbay #define NIC_TPC_FUNNEL_W_S_SECTION 0x80000 3414*e65e175bSOded Gabbay #define mmNIC_TPC_FUNNEL_E_S_BASE 0x7FFE680000ull 3415*e65e175bSOded Gabbay #define NIC_TPC_FUNNEL_E_S_MAX_OFFSET 0x1000 3416*e65e175bSOded Gabbay #define NIC_TPC_FUNNEL_E_S_SECTION 0x80000 3417*e65e175bSOded Gabbay #define mmNIC_TPC_FUNNEL_W_N_BASE 0x7FFE700000ull 3418*e65e175bSOded Gabbay #define NIC_TPC_FUNNEL_W_N_MAX_OFFSET 0x1000 3419*e65e175bSOded Gabbay #define NIC_TPC_FUNNEL_W_N_SECTION 0x80000 3420*e65e175bSOded Gabbay #define mmNIC_TPC_FUNNEL_E_N_BASE 0x7FFE780000ull 3421*e65e175bSOded Gabbay #define NIC_TPC_FUNNEL_E_N_MAX_OFFSET 0x1000 3422*e65e175bSOded Gabbay #define NIC_TPC_FUNNEL_E_N_SECTION 0x80000 3423*e65e175bSOded Gabbay #define mmCA53_BASE 0x7FFE800000ull 3424*e65e175bSOded Gabbay #define CA53_MAX_OFFSET 0x141000 3425*e65e175bSOded Gabbay #define CA53_SECTION 0x400000 3426*e65e175bSOded Gabbay #define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull 3427*e65e175bSOded Gabbay #define PCI_ROM_TABLE_MAX_OFFSET 0x1000 3428*e65e175bSOded Gabbay #define PCI_ROM_TABLE_SECTION 0x1000 3429*e65e175bSOded Gabbay #define mmPCIE_STM_BASE 0x7FFEC01000ull 3430*e65e175bSOded Gabbay #define PCIE_STM_MAX_OFFSET 0x1000 3431*e65e175bSOded Gabbay #define PCIE_STM_SECTION 0x1000 3432*e65e175bSOded Gabbay #define mmPCIE_ETF_BASE 0x7FFEC02000ull 3433*e65e175bSOded Gabbay #define PCIE_ETF_MAX_OFFSET 0x1000 3434*e65e175bSOded Gabbay #define PCIE_ETF_SECTION 0x1000 3435*e65e175bSOded Gabbay #define mmPCIE_CTI_0_BASE 0x7FFEC03000ull 3436*e65e175bSOded Gabbay #define PCIE_CTI_0_MAX_OFFSET 0x1000 3437*e65e175bSOded Gabbay #define PCIE_CTI_0_SECTION 0x1000 3438*e65e175bSOded Gabbay #define mmPCIE_SPMU_BASE 0x7FFEC04000ull 3439*e65e175bSOded Gabbay #define PCIE_SPMU_MAX_OFFSET 0x1000 3440*e65e175bSOded Gabbay #define PCIE_SPMU_SECTION 0x1000 3441*e65e175bSOded Gabbay #define mmPCIE_CTI_1_BASE 0x7FFEC05000ull 3442*e65e175bSOded Gabbay #define PCIE_CTI_1_MAX_OFFSET 0x1000 3443*e65e175bSOded Gabbay #define PCIE_CTI_1_SECTION 0x1000 3444*e65e175bSOded Gabbay #define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull 3445*e65e175bSOded Gabbay #define PCIE_FUNNEL_MAX_OFFSET 0x1000 3446*e65e175bSOded Gabbay #define PCIE_FUNNEL_SECTION 0x1000 3447*e65e175bSOded Gabbay #define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull 3448*e65e175bSOded Gabbay #define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000 3449*e65e175bSOded Gabbay #define PCIE_BMON_MSTR_WR_SECTION 0x1000 3450*e65e175bSOded Gabbay #define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull 3451*e65e175bSOded Gabbay #define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000 3452*e65e175bSOded Gabbay #define PCIE_BMON_MSTR_RD_SECTION 0x1000 3453*e65e175bSOded Gabbay #define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull 3454*e65e175bSOded Gabbay #define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000 3455*e65e175bSOded Gabbay #define PCIE_BMON_SLV_WR_SECTION 0x1000 3456*e65e175bSOded Gabbay #define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull 3457*e65e175bSOded Gabbay #define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000 3458*e65e175bSOded Gabbay #define PCIE_BMON_SLV_RD_SECTION 0x7000 3459*e65e175bSOded Gabbay #define mmMMU_CS_STM_BASE 0x7FFEC11000ull 3460*e65e175bSOded Gabbay #define MMU_CS_STM_MAX_OFFSET 0x1000 3461*e65e175bSOded Gabbay #define MMU_CS_STM_SECTION 0x1000 3462*e65e175bSOded Gabbay #define mmMMU_CS_CTI_BASE 0x7FFEC12000ull 3463*e65e175bSOded Gabbay #define MMU_CS_CTI_MAX_OFFSET 0x1000 3464*e65e175bSOded Gabbay #define MMU_CS_CTI_SECTION 0x1000 3465*e65e175bSOded Gabbay #define mmMMU_CS_ETF_BASE 0x7FFEC13000ull 3466*e65e175bSOded Gabbay #define MMU_CS_ETF_MAX_OFFSET 0x1000 3467*e65e175bSOded Gabbay #define MMU_CS_ETF_SECTION 0x1000 3468*e65e175bSOded Gabbay #define mmMMU_CS_SPMU_BASE 0x7FFEC14000ull 3469*e65e175bSOded Gabbay #define MMU_CS_SPMU_MAX_OFFSET 0x1000 3470*e65e175bSOded Gabbay #define MMU_CS_SPMU_SECTION 0x1000 3471*e65e175bSOded Gabbay #define mmMMU_BMON_CTI_BASE 0x7FFEC15000ull 3472*e65e175bSOded Gabbay #define MMU_BMON_CTI_MAX_OFFSET 0x1000 3473*e65e175bSOded Gabbay #define MMU_BMON_CTI_SECTION 0x1000 3474*e65e175bSOded Gabbay #define mmMMU_USER_CTI_BASE 0x7FFEC16000ull 3475*e65e175bSOded Gabbay #define MMU_USER_CTI_MAX_OFFSET 0x1000 3476*e65e175bSOded Gabbay #define MMU_USER_CTI_SECTION 0x1000 3477*e65e175bSOded Gabbay #define mmMMU_BMON_0_BASE 0x7FFEC17000ull 3478*e65e175bSOded Gabbay #define MMU_BMON_0_MAX_OFFSET 0x1000 3479*e65e175bSOded Gabbay #define MMU_BMON_0_SECTION 0x1000 3480*e65e175bSOded Gabbay #define mmMMU_BMON_1_BASE 0x7FFEC18000ull 3481*e65e175bSOded Gabbay #define MMU_BMON_1_MAX_OFFSET 0x1000 3482*e65e175bSOded Gabbay #define MMU_BMON_1_SECTION 0x28000 3483*e65e175bSOded Gabbay #define mmPSOC_CTI_BASE 0x7FFEC40000ull 3484*e65e175bSOded Gabbay #define PSOC_CTI_MAX_OFFSET 0x1000 3485*e65e175bSOded Gabbay #define PSOC_CTI_SECTION 0x1000 3486*e65e175bSOded Gabbay #define mmPSOC_STM_BASE 0x7FFEC41000ull 3487*e65e175bSOded Gabbay #define PSOC_STM_MAX_OFFSET 0x1000 3488*e65e175bSOded Gabbay #define PSOC_STM_SECTION 0x1000 3489*e65e175bSOded Gabbay #define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull 3490*e65e175bSOded Gabbay #define PSOC_FUNNEL_MAX_OFFSET 0x1000 3491*e65e175bSOded Gabbay #define PSOC_FUNNEL_SECTION 0x1000 3492*e65e175bSOded Gabbay #define mmPSOC_ETR_BASE 0x7FFEC43000ull 3493*e65e175bSOded Gabbay #define PSOC_ETR_MAX_OFFSET 0x1000 3494*e65e175bSOded Gabbay #define PSOC_ETR_SECTION 0x1000 3495*e65e175bSOded Gabbay #define mmPSOC_ETF_BASE 0x7FFEC44000ull 3496*e65e175bSOded Gabbay #define PSOC_ETF_MAX_OFFSET 0x1000 3497*e65e175bSOded Gabbay #define PSOC_ETF_SECTION 0x1000 3498*e65e175bSOded Gabbay #define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull 3499*e65e175bSOded Gabbay #define PSOC_TS_CTI_MAX_OFFSET 0x1000 3500*e65e175bSOded Gabbay #define PSOC_TS_CTI_SECTION 0xB000 3501*e65e175bSOded Gabbay #define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull 3502*e65e175bSOded Gabbay #define TOP_ROM_TABLE_MAX_OFFSET 0x1000 3503*e65e175bSOded Gabbay #define TOP_ROM_TABLE_SECTION 0x70000 3504*e65e175bSOded Gabbay #define mmNIC0_ROM_TABLE_BASE 0x7FFECC0000ull 3505*e65e175bSOded Gabbay #define NIC0_ROM_TABLE_MAX_OFFSET 0x1000 3506*e65e175bSOded Gabbay #define NIC0_ROM_TABLE_SECTION 0x1000 3507*e65e175bSOded Gabbay #define mmSTM_0_NIC0_DBG_BASE 0x7FFECC1000ull 3508*e65e175bSOded Gabbay #define STM_0_NIC0_DBG_MAX_OFFSET 0x21000 3509*e65e175bSOded Gabbay #define STM_0_NIC0_DBG_SECTION 0x1000 3510*e65e175bSOded Gabbay #define mmCTI_0_NIC0_DBG_BASE 0x7FFECC2000ull 3511*e65e175bSOded Gabbay #define CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 3512*e65e175bSOded Gabbay #define CTI_0_NIC0_DBG_SECTION 0x1000 3513*e65e175bSOded Gabbay #define mmETF_0_NIC0_DBG_BASE 0x7FFECC3000ull 3514*e65e175bSOded Gabbay #define ETF_0_NIC0_DBG_MAX_OFFSET 0x1000 3515*e65e175bSOded Gabbay #define ETF_0_NIC0_DBG_SECTION 0x1000 3516*e65e175bSOded Gabbay #define mmSPMU_0_NIC0_DBG_BASE 0x7FFECC4000ull 3517*e65e175bSOded Gabbay #define SPMU_0_NIC0_DBG_MAX_OFFSET 0x1000 3518*e65e175bSOded Gabbay #define SPMU_0_NIC0_DBG_SECTION 0x2000 3519*e65e175bSOded Gabbay #define mmUSER_CTI_0_NIC0_DBG_BASE 0x7FFECC6000ull 3520*e65e175bSOded Gabbay #define USER_CTI_0_NIC0_DBG_MAX_OFFSET 0x1000 3521*e65e175bSOded Gabbay #define USER_CTI_0_NIC0_DBG_SECTION 0xB000 3522*e65e175bSOded Gabbay #define mmSTM_1_NIC0_DBG_BASE 0x7FFECD1000ull 3523*e65e175bSOded Gabbay #define STM_1_NIC0_DBG_MAX_OFFSET 0x1000 3524*e65e175bSOded Gabbay #define STM_1_NIC0_DBG_SECTION 0x1000 3525*e65e175bSOded Gabbay #define mmCTI_1_NIC0_DBG_BASE 0x7FFECD2000ull 3526*e65e175bSOded Gabbay #define CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 3527*e65e175bSOded Gabbay #define CTI_1_NIC0_DBG_SECTION 0x1000 3528*e65e175bSOded Gabbay #define mmETF_1_NIC0_DBG_BASE 0x7FFECD3000ull 3529*e65e175bSOded Gabbay #define ETF_1_NIC0_DBG_MAX_OFFSET 0x1000 3530*e65e175bSOded Gabbay #define ETF_1_NIC0_DBG_SECTION 0x1000 3531*e65e175bSOded Gabbay #define mmSPMU_1_NIC0_DBG_BASE 0x7FFECD4000ull 3532*e65e175bSOded Gabbay #define SPMU_1_NIC0_DBG_MAX_OFFSET 0x1000 3533*e65e175bSOded Gabbay #define SPMU_1_NIC0_DBG_SECTION 0x1000 3534*e65e175bSOded Gabbay #define mmBMON_CTI_NIC0_DBG_BASE 0x7FFECD5000ull 3535*e65e175bSOded Gabbay #define BMON_CTI_NIC0_DBG_MAX_OFFSET 0x1000 3536*e65e175bSOded Gabbay #define BMON_CTI_NIC0_DBG_SECTION 0x1000 3537*e65e175bSOded Gabbay #define mmUSER_CTI_1_NIC0_DBG_BASE 0x7FFECD6000ull 3538*e65e175bSOded Gabbay #define USER_CTI_1_NIC0_DBG_MAX_OFFSET 0x1000 3539*e65e175bSOded Gabbay #define USER_CTI_1_NIC0_DBG_SECTION 0x1000 3540*e65e175bSOded Gabbay #define mmBMON0_NIC0_DBG_BASE 0x7FFECD7000ull 3541*e65e175bSOded Gabbay #define BMON0_NIC0_DBG_MAX_OFFSET 0x1000 3542*e65e175bSOded Gabbay #define BMON0_NIC0_DBG_SECTION 0x1000 3543*e65e175bSOded Gabbay #define mmBMON1_NIC0_DBG_BASE 0x7FFECD8000ull 3544*e65e175bSOded Gabbay #define BMON1_NIC0_DBG_MAX_OFFSET 0x1000 3545*e65e175bSOded Gabbay #define BMON1_NIC0_DBG_SECTION 0x1000 3546*e65e175bSOded Gabbay #define mmBMON2_NIC0_DBG_BASE 0x7FFECD9000ull 3547*e65e175bSOded Gabbay #define BMON2_NIC0_DBG_MAX_OFFSET 0x1000 3548*e65e175bSOded Gabbay #define BMON2_NIC0_DBG_SECTION 0x1000 3549*e65e175bSOded Gabbay #define mmBMON3_NIC0_DBG_BASE 0x7FFECDA000ull 3550*e65e175bSOded Gabbay #define BMON3_NIC0_DBG_MAX_OFFSET 0x1000 3551*e65e175bSOded Gabbay #define BMON3_NIC0_DBG_SECTION 0x1000 3552*e65e175bSOded Gabbay #define mmBMON4_NIC0_DBG_BASE 0x7FFECDB000ull 3553*e65e175bSOded Gabbay #define BMON4_NIC0_DBG_MAX_OFFSET 0x1000 3554*e65e175bSOded Gabbay #define BMON4_NIC0_DBG_SECTION 0x6000 3555*e65e175bSOded Gabbay #define mmFUNNEL_NIC0_DBG_BASE 0x7FFECE1000ull 3556*e65e175bSOded Gabbay #define FUNNEL_NIC0_DBG_MAX_OFFSET 0x1000 3557*e65e175bSOded Gabbay #define FUNNEL_NIC0_DBG_SECTION 0x1F000 3558*e65e175bSOded Gabbay #define mmNIC1_ROM_TABLE_BASE 0x7FFED00000ull 3559*e65e175bSOded Gabbay #define NIC1_ROM_TABLE_MAX_OFFSET 0x1000 3560*e65e175bSOded Gabbay #define NIC1_ROM_TABLE_SECTION 0x1000 3561*e65e175bSOded Gabbay #define mmSTM_0_NIC1_DBG_BASE 0x7FFED01000ull 3562*e65e175bSOded Gabbay #define STM_0_NIC1_DBG_MAX_OFFSET 0x21000 3563*e65e175bSOded Gabbay #define STM_0_NIC1_DBG_SECTION 0x1000 3564*e65e175bSOded Gabbay #define mmCTI_0_NIC1_DBG_BASE 0x7FFED02000ull 3565*e65e175bSOded Gabbay #define CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 3566*e65e175bSOded Gabbay #define CTI_0_NIC1_DBG_SECTION 0x1000 3567*e65e175bSOded Gabbay #define mmETF_0_NIC1_DBG_BASE 0x7FFED03000ull 3568*e65e175bSOded Gabbay #define ETF_0_NIC1_DBG_MAX_OFFSET 0x1000 3569*e65e175bSOded Gabbay #define ETF_0_NIC1_DBG_SECTION 0x1000 3570*e65e175bSOded Gabbay #define mmSPMU_0_NIC1_DBG_BASE 0x7FFED04000ull 3571*e65e175bSOded Gabbay #define SPMU_0_NIC1_DBG_MAX_OFFSET 0x1000 3572*e65e175bSOded Gabbay #define SPMU_0_NIC1_DBG_SECTION 0x2000 3573*e65e175bSOded Gabbay #define mmUSER_CTI_0_NIC1_DBG_BASE 0x7FFED06000ull 3574*e65e175bSOded Gabbay #define USER_CTI_0_NIC1_DBG_MAX_OFFSET 0x1000 3575*e65e175bSOded Gabbay #define USER_CTI_0_NIC1_DBG_SECTION 0xB000 3576*e65e175bSOded Gabbay #define mmSTM_1_NIC1_DBG_BASE 0x7FFED11000ull 3577*e65e175bSOded Gabbay #define STM_1_NIC1_DBG_MAX_OFFSET 0x1000 3578*e65e175bSOded Gabbay #define STM_1_NIC1_DBG_SECTION 0x1000 3579*e65e175bSOded Gabbay #define mmCTI_1_NIC1_DBG_BASE 0x7FFED12000ull 3580*e65e175bSOded Gabbay #define CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 3581*e65e175bSOded Gabbay #define CTI_1_NIC1_DBG_SECTION 0x1000 3582*e65e175bSOded Gabbay #define mmETF_1_NIC1_DBG_BASE 0x7FFED13000ull 3583*e65e175bSOded Gabbay #define ETF_1_NIC1_DBG_MAX_OFFSET 0x1000 3584*e65e175bSOded Gabbay #define ETF_1_NIC1_DBG_SECTION 0x1000 3585*e65e175bSOded Gabbay #define mmSPMU_1_NIC1_DBG_BASE 0x7FFED14000ull 3586*e65e175bSOded Gabbay #define SPMU_1_NIC1_DBG_MAX_OFFSET 0x1000 3587*e65e175bSOded Gabbay #define SPMU_1_NIC1_DBG_SECTION 0x1000 3588*e65e175bSOded Gabbay #define mmBMON_CTI_NIC1_DBG_BASE 0x7FFED15000ull 3589*e65e175bSOded Gabbay #define BMON_CTI_NIC1_DBG_MAX_OFFSET 0x1000 3590*e65e175bSOded Gabbay #define BMON_CTI_NIC1_DBG_SECTION 0x1000 3591*e65e175bSOded Gabbay #define mmUSER_CTI_1_NIC1_DBG_BASE 0x7FFED16000ull 3592*e65e175bSOded Gabbay #define USER_CTI_1_NIC1_DBG_MAX_OFFSET 0x1000 3593*e65e175bSOded Gabbay #define USER_CTI_1_NIC1_DBG_SECTION 0x1000 3594*e65e175bSOded Gabbay #define mmBMON0_NIC1_DBG_BASE 0x7FFED17000ull 3595*e65e175bSOded Gabbay #define BMON0_NIC1_DBG_MAX_OFFSET 0x1000 3596*e65e175bSOded Gabbay #define BMON0_NIC1_DBG_SECTION 0x1000 3597*e65e175bSOded Gabbay #define mmBMON1_NIC1_DBG_BASE 0x7FFED18000ull 3598*e65e175bSOded Gabbay #define BMON1_NIC1_DBG_MAX_OFFSET 0x1000 3599*e65e175bSOded Gabbay #define BMON1_NIC1_DBG_SECTION 0x1000 3600*e65e175bSOded Gabbay #define mmBMON2_NIC1_DBG_BASE 0x7FFED19000ull 3601*e65e175bSOded Gabbay #define BMON2_NIC1_DBG_MAX_OFFSET 0x1000 3602*e65e175bSOded Gabbay #define BMON2_NIC1_DBG_SECTION 0x1000 3603*e65e175bSOded Gabbay #define mmBMON3_NIC1_DBG_BASE 0x7FFED1A000ull 3604*e65e175bSOded Gabbay #define BMON3_NIC1_DBG_MAX_OFFSET 0x1000 3605*e65e175bSOded Gabbay #define BMON3_NIC1_DBG_SECTION 0x1000 3606*e65e175bSOded Gabbay #define mmBMON4_NIC1_DBG_BASE 0x7FFED1B000ull 3607*e65e175bSOded Gabbay #define BMON4_NIC1_DBG_MAX_OFFSET 0x1000 3608*e65e175bSOded Gabbay #define BMON4_NIC1_DBG_SECTION 0x6000 3609*e65e175bSOded Gabbay #define mmFUNNEL_NIC1_DBG_BASE 0x7FFED21000ull 3610*e65e175bSOded Gabbay #define FUNNEL_NIC1_DBG_MAX_OFFSET 0x1000 3611*e65e175bSOded Gabbay #define FUNNEL_NIC1_DBG_SECTION 0x1F000 3612*e65e175bSOded Gabbay #define mmNIC2_ROM_TABLE_BASE 0x7FFED40000ull 3613*e65e175bSOded Gabbay #define NIC2_ROM_TABLE_MAX_OFFSET 0x1000 3614*e65e175bSOded Gabbay #define NIC2_ROM_TABLE_SECTION 0x1000 3615*e65e175bSOded Gabbay #define mmSTM_0_NIC2_DBG_BASE 0x7FFED41000ull 3616*e65e175bSOded Gabbay #define STM_0_NIC2_DBG_MAX_OFFSET 0x21000 3617*e65e175bSOded Gabbay #define STM_0_NIC2_DBG_SECTION 0x1000 3618*e65e175bSOded Gabbay #define mmCTI_0_NIC2_DBG_BASE 0x7FFED42000ull 3619*e65e175bSOded Gabbay #define CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 3620*e65e175bSOded Gabbay #define CTI_0_NIC2_DBG_SECTION 0x1000 3621*e65e175bSOded Gabbay #define mmETF_0_NIC2_DBG_BASE 0x7FFED43000ull 3622*e65e175bSOded Gabbay #define ETF_0_NIC2_DBG_MAX_OFFSET 0x1000 3623*e65e175bSOded Gabbay #define ETF_0_NIC2_DBG_SECTION 0x1000 3624*e65e175bSOded Gabbay #define mmSPMU_0_NIC2_DBG_BASE 0x7FFED44000ull 3625*e65e175bSOded Gabbay #define SPMU_0_NIC2_DBG_MAX_OFFSET 0x1000 3626*e65e175bSOded Gabbay #define SPMU_0_NIC2_DBG_SECTION 0x2000 3627*e65e175bSOded Gabbay #define mmUSER_CTI_0_NIC2_DBG_BASE 0x7FFED46000ull 3628*e65e175bSOded Gabbay #define USER_CTI_0_NIC2_DBG_MAX_OFFSET 0x1000 3629*e65e175bSOded Gabbay #define USER_CTI_0_NIC2_DBG_SECTION 0xB000 3630*e65e175bSOded Gabbay #define mmSTM_1_NIC2_DBG_BASE 0x7FFED51000ull 3631*e65e175bSOded Gabbay #define STM_1_NIC2_DBG_MAX_OFFSET 0x1000 3632*e65e175bSOded Gabbay #define STM_1_NIC2_DBG_SECTION 0x1000 3633*e65e175bSOded Gabbay #define mmCTI_1_NIC2_DBG_BASE 0x7FFED52000ull 3634*e65e175bSOded Gabbay #define CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 3635*e65e175bSOded Gabbay #define CTI_1_NIC2_DBG_SECTION 0x1000 3636*e65e175bSOded Gabbay #define mmETF_1_NIC2_DBG_BASE 0x7FFED53000ull 3637*e65e175bSOded Gabbay #define ETF_1_NIC2_DBG_MAX_OFFSET 0x1000 3638*e65e175bSOded Gabbay #define ETF_1_NIC2_DBG_SECTION 0x1000 3639*e65e175bSOded Gabbay #define mmSPMU_1_NIC2_DBG_BASE 0x7FFED54000ull 3640*e65e175bSOded Gabbay #define SPMU_1_NIC2_DBG_MAX_OFFSET 0x1000 3641*e65e175bSOded Gabbay #define SPMU_1_NIC2_DBG_SECTION 0x1000 3642*e65e175bSOded Gabbay #define mmBMON_CTI_NIC2_DBG_BASE 0x7FFED55000ull 3643*e65e175bSOded Gabbay #define BMON_CTI_NIC2_DBG_MAX_OFFSET 0x1000 3644*e65e175bSOded Gabbay #define BMON_CTI_NIC2_DBG_SECTION 0x1000 3645*e65e175bSOded Gabbay #define mmUSER_CTI_1_NIC2_DBG_BASE 0x7FFED56000ull 3646*e65e175bSOded Gabbay #define USER_CTI_1_NIC2_DBG_MAX_OFFSET 0x1000 3647*e65e175bSOded Gabbay #define USER_CTI_1_NIC2_DBG_SECTION 0x1000 3648*e65e175bSOded Gabbay #define mmBMON0_NIC2_DBG_BASE 0x7FFED57000ull 3649*e65e175bSOded Gabbay #define BMON0_NIC2_DBG_MAX_OFFSET 0x1000 3650*e65e175bSOded Gabbay #define BMON0_NIC2_DBG_SECTION 0x1000 3651*e65e175bSOded Gabbay #define mmBMON1_NIC2_DBG_BASE 0x7FFED58000ull 3652*e65e175bSOded Gabbay #define BMON1_NIC2_DBG_MAX_OFFSET 0x1000 3653*e65e175bSOded Gabbay #define BMON1_NIC2_DBG_SECTION 0x1000 3654*e65e175bSOded Gabbay #define mmBMON2_NIC2_DBG_BASE 0x7FFED59000ull 3655*e65e175bSOded Gabbay #define BMON2_NIC2_DBG_MAX_OFFSET 0x1000 3656*e65e175bSOded Gabbay #define BMON2_NIC2_DBG_SECTION 0x1000 3657*e65e175bSOded Gabbay #define mmBMON3_NIC2_DBG_BASE 0x7FFED5A000ull 3658*e65e175bSOded Gabbay #define BMON3_NIC2_DBG_MAX_OFFSET 0x1000 3659*e65e175bSOded Gabbay #define BMON3_NIC2_DBG_SECTION 0x1000 3660*e65e175bSOded Gabbay #define mmBMON4_NIC2_DBG_BASE 0x7FFED5B000ull 3661*e65e175bSOded Gabbay #define BMON4_NIC2_DBG_MAX_OFFSET 0x1000 3662*e65e175bSOded Gabbay #define BMON4_NIC2_DBG_SECTION 0x6000 3663*e65e175bSOded Gabbay #define mmFUNNEL_NIC2_DBG_BASE 0x7FFED61000ull 3664*e65e175bSOded Gabbay #define FUNNEL_NIC2_DBG_MAX_OFFSET 0x1000 3665*e65e175bSOded Gabbay #define FUNNEL_NIC2_DBG_SECTION 0x1F000 3666*e65e175bSOded Gabbay #define mmNIC3_ROM_TABLE_BASE 0x7FFED80000ull 3667*e65e175bSOded Gabbay #define NIC3_ROM_TABLE_MAX_OFFSET 0x1000 3668*e65e175bSOded Gabbay #define NIC3_ROM_TABLE_SECTION 0x1000 3669*e65e175bSOded Gabbay #define mmSTM_0_NIC3_DBG_BASE 0x7FFED81000ull 3670*e65e175bSOded Gabbay #define STM_0_NIC3_DBG_MAX_OFFSET 0x21000 3671*e65e175bSOded Gabbay #define STM_0_NIC3_DBG_SECTION 0x1000 3672*e65e175bSOded Gabbay #define mmCTI_0_NIC3_DBG_BASE 0x7FFED82000ull 3673*e65e175bSOded Gabbay #define CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 3674*e65e175bSOded Gabbay #define CTI_0_NIC3_DBG_SECTION 0x1000 3675*e65e175bSOded Gabbay #define mmETF_0_NIC3_DBG_BASE 0x7FFED83000ull 3676*e65e175bSOded Gabbay #define ETF_0_NIC3_DBG_MAX_OFFSET 0x1000 3677*e65e175bSOded Gabbay #define ETF_0_NIC3_DBG_SECTION 0x1000 3678*e65e175bSOded Gabbay #define mmSPMU_0_NIC3_DBG_BASE 0x7FFED84000ull 3679*e65e175bSOded Gabbay #define SPMU_0_NIC3_DBG_MAX_OFFSET 0x1000 3680*e65e175bSOded Gabbay #define SPMU_0_NIC3_DBG_SECTION 0x2000 3681*e65e175bSOded Gabbay #define mmUSER_CTI_0_NIC3_DBG_BASE 0x7FFED86000ull 3682*e65e175bSOded Gabbay #define USER_CTI_0_NIC3_DBG_MAX_OFFSET 0x1000 3683*e65e175bSOded Gabbay #define USER_CTI_0_NIC3_DBG_SECTION 0xB000 3684*e65e175bSOded Gabbay #define mmSTM_1_NIC3_DBG_BASE 0x7FFED91000ull 3685*e65e175bSOded Gabbay #define STM_1_NIC3_DBG_MAX_OFFSET 0x1000 3686*e65e175bSOded Gabbay #define STM_1_NIC3_DBG_SECTION 0x1000 3687*e65e175bSOded Gabbay #define mmCTI_1_NIC3_DBG_BASE 0x7FFED92000ull 3688*e65e175bSOded Gabbay #define CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 3689*e65e175bSOded Gabbay #define CTI_1_NIC3_DBG_SECTION 0x1000 3690*e65e175bSOded Gabbay #define mmETF_1_NIC3_DBG_BASE 0x7FFED93000ull 3691*e65e175bSOded Gabbay #define ETF_1_NIC3_DBG_MAX_OFFSET 0x1000 3692*e65e175bSOded Gabbay #define ETF_1_NIC3_DBG_SECTION 0x1000 3693*e65e175bSOded Gabbay #define mmSPMU_1_NIC3_DBG_BASE 0x7FFED94000ull 3694*e65e175bSOded Gabbay #define SPMU_1_NIC3_DBG_MAX_OFFSET 0x1000 3695*e65e175bSOded Gabbay #define SPMU_1_NIC3_DBG_SECTION 0x1000 3696*e65e175bSOded Gabbay #define mmBMON_CTI_NIC3_DBG_BASE 0x7FFED95000ull 3697*e65e175bSOded Gabbay #define BMON_CTI_NIC3_DBG_MAX_OFFSET 0x1000 3698*e65e175bSOded Gabbay #define BMON_CTI_NIC3_DBG_SECTION 0x1000 3699*e65e175bSOded Gabbay #define mmUSER_CTI_1_NIC3_DBG_BASE 0x7FFED96000ull 3700*e65e175bSOded Gabbay #define USER_CTI_1_NIC3_DBG_MAX_OFFSET 0x1000 3701*e65e175bSOded Gabbay #define USER_CTI_1_NIC3_DBG_SECTION 0x1000 3702*e65e175bSOded Gabbay #define mmBMON0_NIC3_DBG_BASE 0x7FFED97000ull 3703*e65e175bSOded Gabbay #define BMON0_NIC3_DBG_MAX_OFFSET 0x1000 3704*e65e175bSOded Gabbay #define BMON0_NIC3_DBG_SECTION 0x1000 3705*e65e175bSOded Gabbay #define mmBMON1_NIC3_DBG_BASE 0x7FFED98000ull 3706*e65e175bSOded Gabbay #define BMON1_NIC3_DBG_MAX_OFFSET 0x1000 3707*e65e175bSOded Gabbay #define BMON1_NIC3_DBG_SECTION 0x1000 3708*e65e175bSOded Gabbay #define mmBMON2_NIC3_DBG_BASE 0x7FFED99000ull 3709*e65e175bSOded Gabbay #define BMON2_NIC3_DBG_MAX_OFFSET 0x1000 3710*e65e175bSOded Gabbay #define BMON2_NIC3_DBG_SECTION 0x1000 3711*e65e175bSOded Gabbay #define mmBMON3_NIC3_DBG_BASE 0x7FFED9A000ull 3712*e65e175bSOded Gabbay #define BMON3_NIC3_DBG_MAX_OFFSET 0x1000 3713*e65e175bSOded Gabbay #define BMON3_NIC3_DBG_SECTION 0x1000 3714*e65e175bSOded Gabbay #define mmBMON4_NIC3_DBG_BASE 0x7FFED9B000ull 3715*e65e175bSOded Gabbay #define BMON4_NIC3_DBG_MAX_OFFSET 0x1000 3716*e65e175bSOded Gabbay #define BMON4_NIC3_DBG_SECTION 0x6000 3717*e65e175bSOded Gabbay #define mmFUNNEL_NIC3_DBG_BASE 0x7FFEDA1000ull 3718*e65e175bSOded Gabbay #define FUNNEL_NIC3_DBG_MAX_OFFSET 0x1000 3719*e65e175bSOded Gabbay #define FUNNEL_NIC3_DBG_SECTION 0x1F000 3720*e65e175bSOded Gabbay #define mmNIC4_ROM_TABLE_BASE 0x7FFEDC0000ull 3721*e65e175bSOded Gabbay #define NIC4_ROM_TABLE_MAX_OFFSET 0x1000 3722*e65e175bSOded Gabbay #define NIC4_ROM_TABLE_SECTION 0x1000 3723*e65e175bSOded Gabbay #define mmSTM_0_NIC4_DBG_BASE 0x7FFEDC1000ull 3724*e65e175bSOded Gabbay #define STM_0_NIC4_DBG_MAX_OFFSET 0x21000 3725*e65e175bSOded Gabbay #define STM_0_NIC4_DBG_SECTION 0x1000 3726*e65e175bSOded Gabbay #define mmCTI_0_NIC4_DBG_BASE 0x7FFEDC2000ull 3727*e65e175bSOded Gabbay #define CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 3728*e65e175bSOded Gabbay #define CTI_0_NIC4_DBG_SECTION 0x1000 3729*e65e175bSOded Gabbay #define mmETF_0_NIC4_DBG_BASE 0x7FFEDC3000ull 3730*e65e175bSOded Gabbay #define ETF_0_NIC4_DBG_MAX_OFFSET 0x1000 3731*e65e175bSOded Gabbay #define ETF_0_NIC4_DBG_SECTION 0x1000 3732*e65e175bSOded Gabbay #define mmSPMU_0_NIC4_DBG_BASE 0x7FFEDC4000ull 3733*e65e175bSOded Gabbay #define SPMU_0_NIC4_DBG_MAX_OFFSET 0x1000 3734*e65e175bSOded Gabbay #define SPMU_0_NIC4_DBG_SECTION 0x2000 3735*e65e175bSOded Gabbay #define mmUSER_CTI_0_NIC4_DBG_BASE 0x7FFEDC6000ull 3736*e65e175bSOded Gabbay #define USER_CTI_0_NIC4_DBG_MAX_OFFSET 0x1000 3737*e65e175bSOded Gabbay #define USER_CTI_0_NIC4_DBG_SECTION 0xB000 3738*e65e175bSOded Gabbay #define mmSTM_1_NIC4_DBG_BASE 0x7FFEDD1000ull 3739*e65e175bSOded Gabbay #define STM_1_NIC4_DBG_MAX_OFFSET 0x1000 3740*e65e175bSOded Gabbay #define STM_1_NIC4_DBG_SECTION 0x1000 3741*e65e175bSOded Gabbay #define mmCTI_1_NIC4_DBG_BASE 0x7FFEDD2000ull 3742*e65e175bSOded Gabbay #define CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 3743*e65e175bSOded Gabbay #define CTI_1_NIC4_DBG_SECTION 0x1000 3744*e65e175bSOded Gabbay #define mmETF_1_NIC4_DBG_BASE 0x7FFEDD3000ull 3745*e65e175bSOded Gabbay #define ETF_1_NIC4_DBG_MAX_OFFSET 0x1000 3746*e65e175bSOded Gabbay #define ETF_1_NIC4_DBG_SECTION 0x1000 3747*e65e175bSOded Gabbay #define mmSPMU_1_NIC4_DBG_BASE 0x7FFEDD4000ull 3748*e65e175bSOded Gabbay #define SPMU_1_NIC4_DBG_MAX_OFFSET 0x1000 3749*e65e175bSOded Gabbay #define SPMU_1_NIC4_DBG_SECTION 0x1000 3750*e65e175bSOded Gabbay #define mmBMON_CTI_NIC4_DBG_BASE 0x7FFEDD5000ull 3751*e65e175bSOded Gabbay #define BMON_CTI_NIC4_DBG_MAX_OFFSET 0x1000 3752*e65e175bSOded Gabbay #define BMON_CTI_NIC4_DBG_SECTION 0x1000 3753*e65e175bSOded Gabbay #define mmUSER_CTI_1_NIC4_DBG_BASE 0x7FFEDD6000ull 3754*e65e175bSOded Gabbay #define USER_CTI_1_NIC4_DBG_MAX_OFFSET 0x1000 3755*e65e175bSOded Gabbay #define USER_CTI_1_NIC4_DBG_SECTION 0x1000 3756*e65e175bSOded Gabbay #define mmBMON0_NIC4_DBG_BASE 0x7FFEDD7000ull 3757*e65e175bSOded Gabbay #define BMON0_NIC4_DBG_MAX_OFFSET 0x1000 3758*e65e175bSOded Gabbay #define BMON0_NIC4_DBG_SECTION 0x1000 3759*e65e175bSOded Gabbay #define mmBMON1_NIC4_DBG_BASE 0x7FFEDD8000ull 3760*e65e175bSOded Gabbay #define BMON1_NIC4_DBG_MAX_OFFSET 0x1000 3761*e65e175bSOded Gabbay #define BMON1_NIC4_DBG_SECTION 0x1000 3762*e65e175bSOded Gabbay #define mmBMON2_NIC4_DBG_BASE 0x7FFEDD9000ull 3763*e65e175bSOded Gabbay #define BMON2_NIC4_DBG_MAX_OFFSET 0x1000 3764*e65e175bSOded Gabbay #define BMON2_NIC4_DBG_SECTION 0x1000 3765*e65e175bSOded Gabbay #define mmBMON3_NIC4_DBG_BASE 0x7FFEDDA000ull 3766*e65e175bSOded Gabbay #define BMON3_NIC4_DBG_MAX_OFFSET 0x1000 3767*e65e175bSOded Gabbay #define BMON3_NIC4_DBG_SECTION 0x1000 3768*e65e175bSOded Gabbay #define mmBMON4_NIC4_DBG_BASE 0x7FFEDDB000ull 3769*e65e175bSOded Gabbay #define BMON4_NIC4_DBG_MAX_OFFSET 0x1000 3770*e65e175bSOded Gabbay #define BMON4_NIC4_DBG_SECTION 0x6000 3771*e65e175bSOded Gabbay #define mmFUNNEL_NIC4_DBG_BASE 0x7FFEDE1000ull 3772*e65e175bSOded Gabbay #define FUNNEL_NIC4_DBG_MAX_OFFSET 0x1000 3773*e65e175bSOded Gabbay #define FUNNEL_NIC4_DBG_SECTION 0x21F000 3774*e65e175bSOded Gabbay #define mmTPC0_ROM_TABLE_BASE 0x7FFF000000ull 3775*e65e175bSOded Gabbay #define TPC0_ROM_TABLE_MAX_OFFSET 0x1000 3776*e65e175bSOded Gabbay #define TPC0_ROM_TABLE_SECTION 0x1000 3777*e65e175bSOded Gabbay #define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull 3778*e65e175bSOded Gabbay #define TPC0_EML_SPMU_MAX_OFFSET 0x1000 3779*e65e175bSOded Gabbay #define TPC0_EML_SPMU_SECTION 0x1000 3780*e65e175bSOded Gabbay #define mmTPC0_EML_ETF_BASE 0x7FFF002000ull 3781*e65e175bSOded Gabbay #define TPC0_EML_ETF_MAX_OFFSET 0x1000 3782*e65e175bSOded Gabbay #define TPC0_EML_ETF_SECTION 0x1000 3783*e65e175bSOded Gabbay #define mmTPC0_EML_STM_BASE 0x7FFF003000ull 3784*e65e175bSOded Gabbay #define TPC0_EML_STM_MAX_OFFSET 0x1000 3785*e65e175bSOded Gabbay #define TPC0_EML_STM_SECTION 0x2000 3786*e65e175bSOded Gabbay #define mmTPC0_EML_CTI_BASE 0x7FFF005000ull 3787*e65e175bSOded Gabbay #define TPC0_EML_CTI_MAX_OFFSET 0x1000 3788*e65e175bSOded Gabbay #define TPC0_EML_CTI_SECTION 0x1000 3789*e65e175bSOded Gabbay #define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull 3790*e65e175bSOded Gabbay #define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 3791*e65e175bSOded Gabbay #define TPC0_EML_FUNNEL_SECTION 0x1000 3792*e65e175bSOded Gabbay #define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull 3793*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 3794*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_0_SECTION 0x1000 3795*e65e175bSOded Gabbay #define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull 3796*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 3797*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_1_SECTION 0x1000 3798*e65e175bSOded Gabbay #define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull 3799*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 3800*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_2_SECTION 0x1000 3801*e65e175bSOded Gabbay #define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull 3802*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 3803*e65e175bSOded Gabbay #define TPC0_EML_BUSMON_3_SECTION 0x36000 3804*e65e175bSOded Gabbay #define mmTPC0_EML_CFG_BASE 0x7FFF040000ull 3805*e65e175bSOded Gabbay #define TPC0_EML_CFG_MAX_OFFSET 0x3380 3806*e65e175bSOded Gabbay #define TPC0_EML_CFG_SECTION 0x1000 3807*e65e175bSOded Gabbay #define mmTPC0_EML_TPC_CFG_BASE 0x7FFF041000ull 3808*e65e175bSOded Gabbay #define TPC0_EML_TPC_CFG_MAX_OFFSET 0xE400 3809*e65e175bSOded Gabbay #define TPC0_EML_TPC_CFG_SECTION 0x4000 3810*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041400ull 3811*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3812*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 3813*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041438ull 3814*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3815*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 3816*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041470ull 3817*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3818*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 3819*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF0414A8ull 3820*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3821*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 3822*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF0414E0ull 3823*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3824*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 3825*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041518ull 3826*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3827*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 3828*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041550ull 3829*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3830*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 3831*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041588ull 3832*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3833*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 3834*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF0415C0ull 3835*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3836*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 3837*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF0415F8ull 3838*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3839*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 3840*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041630ull 3841*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3842*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 3843*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041668ull 3844*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3845*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 3846*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF0416A0ull 3847*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3848*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 3849*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF0416D8ull 3850*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3851*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 3852*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041710ull 3853*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3854*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 3855*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041748ull 3856*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3857*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 3858*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull 3859*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 3860*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 3861*e65e175bSOded Gabbay #define mmKERNEL_TPC0_EML_TPC_CFG_BASE 0x7FFF041788ull 3862*e65e175bSOded Gabbay #define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 3863*e65e175bSOded Gabbay #define KERNEL_TPC0_EML_TPC_CFG_SECTION 0x2780 3864*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041A00ull 3865*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3866*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800 3867*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041A38ull 3868*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3869*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800 3870*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041A70ull 3871*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3872*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800 3873*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF041AA8ull 3874*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3875*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800 3876*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF041AE0ull 3877*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3878*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800 3879*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041B18ull 3880*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3881*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800 3882*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041B50ull 3883*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3884*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800 3885*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041B88ull 3886*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3887*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800 3888*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF041BC0ull 3889*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3890*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800 3891*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF041BF8ull 3892*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3893*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800 3894*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041C30ull 3895*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3896*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800 3897*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041C68ull 3898*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3899*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800 3900*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF041CA0ull 3901*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3902*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800 3903*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF041CD8ull 3904*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3905*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800 3906*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041D10ull 3907*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3908*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800 3909*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041D48ull 3910*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800 3911*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800 3912*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041D80ull 3913*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000 3914*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000 3915*e65e175bSOded Gabbay #define mmQM_TPC0_EML_TPC_CFG_BASE 0x7FFF041D88ull 3916*e65e175bSOded Gabbay #define QM_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800 3917*e65e175bSOded Gabbay #define QM_TPC0_EML_TPC_CFG_SECTION 0x2780 3918*e65e175bSOded Gabbay #define mmTPC0_EML_TPC_QM_BASE 0x7FFF042000ull 3919*e65e175bSOded Gabbay #define TPC0_EML_TPC_QM_MAX_OFFSET 0xD040 3920*e65e175bSOded Gabbay #define TPC0_EML_TPC_QM_SECTION 0x1BD000 3921*e65e175bSOded Gabbay #define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull 3922*e65e175bSOded Gabbay #define TPC0_EML_CS_MAX_OFFSET 0x1000 3923*e65e175bSOded Gabbay #define TPC0_EML_CS_SECTION 0x1000 3924*e65e175bSOded Gabbay #define mmTPC1_ROM_TABLE_BASE 0x7FFF200000ull 3925*e65e175bSOded Gabbay #define TPC1_ROM_TABLE_MAX_OFFSET 0x1000 3926*e65e175bSOded Gabbay #define TPC1_ROM_TABLE_SECTION 0x1000 3927*e65e175bSOded Gabbay #define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull 3928*e65e175bSOded Gabbay #define TPC1_EML_SPMU_MAX_OFFSET 0x1000 3929*e65e175bSOded Gabbay #define TPC1_EML_SPMU_SECTION 0x1000 3930*e65e175bSOded Gabbay #define mmTPC1_EML_ETF_BASE 0x7FFF202000ull 3931*e65e175bSOded Gabbay #define TPC1_EML_ETF_MAX_OFFSET 0x1000 3932*e65e175bSOded Gabbay #define TPC1_EML_ETF_SECTION 0x1000 3933*e65e175bSOded Gabbay #define mmTPC1_EML_STM_BASE 0x7FFF203000ull 3934*e65e175bSOded Gabbay #define TPC1_EML_STM_MAX_OFFSET 0x1000 3935*e65e175bSOded Gabbay #define TPC1_EML_STM_SECTION 0x2000 3936*e65e175bSOded Gabbay #define mmTPC1_EML_CTI_BASE 0x7FFF205000ull 3937*e65e175bSOded Gabbay #define TPC1_EML_CTI_MAX_OFFSET 0x1000 3938*e65e175bSOded Gabbay #define TPC1_EML_CTI_SECTION 0x1000 3939*e65e175bSOded Gabbay #define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull 3940*e65e175bSOded Gabbay #define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 3941*e65e175bSOded Gabbay #define TPC1_EML_FUNNEL_SECTION 0x1000 3942*e65e175bSOded Gabbay #define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull 3943*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 3944*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_0_SECTION 0x1000 3945*e65e175bSOded Gabbay #define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull 3946*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 3947*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_1_SECTION 0x1000 3948*e65e175bSOded Gabbay #define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull 3949*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 3950*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_2_SECTION 0x1000 3951*e65e175bSOded Gabbay #define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull 3952*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 3953*e65e175bSOded Gabbay #define TPC1_EML_BUSMON_3_SECTION 0x36000 3954*e65e175bSOded Gabbay #define mmTPC1_EML_CFG_BASE 0x7FFF240000ull 3955*e65e175bSOded Gabbay #define TPC1_EML_CFG_MAX_OFFSET 0x3380 3956*e65e175bSOded Gabbay #define TPC1_EML_CFG_SECTION 0x1000 3957*e65e175bSOded Gabbay #define mmTPC1_EML_TPC_CFG_BASE 0x7FFF241000ull 3958*e65e175bSOded Gabbay #define TPC1_EML_TPC_CFG_MAX_OFFSET 0xE400 3959*e65e175bSOded Gabbay #define TPC1_EML_TPC_CFG_SECTION 0x4000 3960*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241400ull 3961*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3962*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 3963*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241438ull 3964*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3965*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 3966*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241470ull 3967*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3968*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 3969*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF2414A8ull 3970*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3971*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 3972*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF2414E0ull 3973*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3974*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 3975*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241518ull 3976*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3977*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 3978*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241550ull 3979*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3980*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 3981*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241588ull 3982*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3983*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 3984*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF2415C0ull 3985*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3986*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 3987*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF2415F8ull 3988*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3989*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 3990*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241630ull 3991*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3992*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 3993*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241668ull 3994*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3995*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 3996*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF2416A0ull 3997*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 3998*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 3999*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF2416D8ull 4000*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4001*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 4002*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241710ull 4003*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4004*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 4005*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241748ull 4006*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4007*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 4008*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull 4009*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 4010*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 4011*e65e175bSOded Gabbay #define mmKERNEL_TPC1_EML_TPC_CFG_BASE 0x7FFF241788ull 4012*e65e175bSOded Gabbay #define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 4013*e65e175bSOded Gabbay #define KERNEL_TPC1_EML_TPC_CFG_SECTION 0x2780 4014*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241A00ull 4015*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4016*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800 4017*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241A38ull 4018*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4019*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800 4020*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241A70ull 4021*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4022*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800 4023*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF241AA8ull 4024*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4025*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800 4026*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF241AE0ull 4027*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4028*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800 4029*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241B18ull 4030*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4031*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800 4032*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241B50ull 4033*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4034*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800 4035*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241B88ull 4036*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4037*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800 4038*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF241BC0ull 4039*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4040*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800 4041*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF241BF8ull 4042*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4043*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800 4044*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241C30ull 4045*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4046*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800 4047*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241C68ull 4048*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4049*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800 4050*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF241CA0ull 4051*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4052*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800 4053*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF241CD8ull 4054*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4055*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800 4056*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241D10ull 4057*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4058*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800 4059*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241D48ull 4060*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800 4061*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800 4062*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241D80ull 4063*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000 4064*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000 4065*e65e175bSOded Gabbay #define mmQM_TPC1_EML_TPC_CFG_BASE 0x7FFF241D88ull 4066*e65e175bSOded Gabbay #define QM_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800 4067*e65e175bSOded Gabbay #define QM_TPC1_EML_TPC_CFG_SECTION 0x2780 4068*e65e175bSOded Gabbay #define mmTPC1_EML_TPC_QM_BASE 0x7FFF242000ull 4069*e65e175bSOded Gabbay #define TPC1_EML_TPC_QM_MAX_OFFSET 0xD040 4070*e65e175bSOded Gabbay #define TPC1_EML_TPC_QM_SECTION 0x1BD000 4071*e65e175bSOded Gabbay #define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull 4072*e65e175bSOded Gabbay #define TPC1_EML_CS_MAX_OFFSET 0x1000 4073*e65e175bSOded Gabbay #define TPC1_EML_CS_SECTION 0x1000 4074*e65e175bSOded Gabbay #define mmTPC2_ROM_TABLE_BASE 0x7FFF400000ull 4075*e65e175bSOded Gabbay #define TPC2_ROM_TABLE_MAX_OFFSET 0x1000 4076*e65e175bSOded Gabbay #define TPC2_ROM_TABLE_SECTION 0x1000 4077*e65e175bSOded Gabbay #define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull 4078*e65e175bSOded Gabbay #define TPC2_EML_SPMU_MAX_OFFSET 0x1000 4079*e65e175bSOded Gabbay #define TPC2_EML_SPMU_SECTION 0x1000 4080*e65e175bSOded Gabbay #define mmTPC2_EML_ETF_BASE 0x7FFF402000ull 4081*e65e175bSOded Gabbay #define TPC2_EML_ETF_MAX_OFFSET 0x1000 4082*e65e175bSOded Gabbay #define TPC2_EML_ETF_SECTION 0x1000 4083*e65e175bSOded Gabbay #define mmTPC2_EML_STM_BASE 0x7FFF403000ull 4084*e65e175bSOded Gabbay #define TPC2_EML_STM_MAX_OFFSET 0x1000 4085*e65e175bSOded Gabbay #define TPC2_EML_STM_SECTION 0x2000 4086*e65e175bSOded Gabbay #define mmTPC2_EML_CTI_BASE 0x7FFF405000ull 4087*e65e175bSOded Gabbay #define TPC2_EML_CTI_MAX_OFFSET 0x1000 4088*e65e175bSOded Gabbay #define TPC2_EML_CTI_SECTION 0x1000 4089*e65e175bSOded Gabbay #define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull 4090*e65e175bSOded Gabbay #define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 4091*e65e175bSOded Gabbay #define TPC2_EML_FUNNEL_SECTION 0x1000 4092*e65e175bSOded Gabbay #define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull 4093*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 4094*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_0_SECTION 0x1000 4095*e65e175bSOded Gabbay #define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull 4096*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 4097*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_1_SECTION 0x1000 4098*e65e175bSOded Gabbay #define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull 4099*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 4100*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_2_SECTION 0x1000 4101*e65e175bSOded Gabbay #define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull 4102*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 4103*e65e175bSOded Gabbay #define TPC2_EML_BUSMON_3_SECTION 0x36000 4104*e65e175bSOded Gabbay #define mmTPC2_EML_CFG_BASE 0x7FFF440000ull 4105*e65e175bSOded Gabbay #define TPC2_EML_CFG_MAX_OFFSET 0x3380 4106*e65e175bSOded Gabbay #define TPC2_EML_CFG_SECTION 0x1000 4107*e65e175bSOded Gabbay #define mmTPC2_EML_TPC_CFG_BASE 0x7FFF441000ull 4108*e65e175bSOded Gabbay #define TPC2_EML_TPC_CFG_MAX_OFFSET 0xE400 4109*e65e175bSOded Gabbay #define TPC2_EML_TPC_CFG_SECTION 0x4000 4110*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441400ull 4111*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4112*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 4113*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441438ull 4114*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4115*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 4116*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441470ull 4117*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4118*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 4119*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF4414A8ull 4120*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4121*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 4122*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF4414E0ull 4123*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4124*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 4125*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441518ull 4126*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4127*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 4128*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441550ull 4129*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4130*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 4131*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441588ull 4132*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4133*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 4134*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF4415C0ull 4135*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4136*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 4137*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF4415F8ull 4138*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4139*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 4140*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441630ull 4141*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4142*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 4143*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441668ull 4144*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4145*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 4146*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF4416A0ull 4147*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4148*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 4149*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF4416D8ull 4150*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4151*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 4152*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441710ull 4153*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4154*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 4155*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441748ull 4156*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4157*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 4158*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull 4159*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 4160*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 4161*e65e175bSOded Gabbay #define mmKERNEL_TPC2_EML_TPC_CFG_BASE 0x7FFF441788ull 4162*e65e175bSOded Gabbay #define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 4163*e65e175bSOded Gabbay #define KERNEL_TPC2_EML_TPC_CFG_SECTION 0x2780 4164*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441A00ull 4165*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4166*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800 4167*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441A38ull 4168*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4169*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800 4170*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441A70ull 4171*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4172*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800 4173*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF441AA8ull 4174*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4175*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800 4176*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF441AE0ull 4177*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4178*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800 4179*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441B18ull 4180*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4181*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800 4182*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441B50ull 4183*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4184*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800 4185*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441B88ull 4186*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4187*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800 4188*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF441BC0ull 4189*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4190*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800 4191*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF441BF8ull 4192*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4193*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800 4194*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441C30ull 4195*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4196*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800 4197*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441C68ull 4198*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4199*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800 4200*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF441CA0ull 4201*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4202*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800 4203*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF441CD8ull 4204*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4205*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800 4206*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441D10ull 4207*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4208*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800 4209*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441D48ull 4210*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800 4211*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800 4212*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441D80ull 4213*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000 4214*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000 4215*e65e175bSOded Gabbay #define mmQM_TPC2_EML_TPC_CFG_BASE 0x7FFF441D88ull 4216*e65e175bSOded Gabbay #define QM_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800 4217*e65e175bSOded Gabbay #define QM_TPC2_EML_TPC_CFG_SECTION 0x2780 4218*e65e175bSOded Gabbay #define mmTPC2_EML_TPC_QM_BASE 0x7FFF442000ull 4219*e65e175bSOded Gabbay #define TPC2_EML_TPC_QM_MAX_OFFSET 0xD040 4220*e65e175bSOded Gabbay #define TPC2_EML_TPC_QM_SECTION 0x1BD000 4221*e65e175bSOded Gabbay #define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull 4222*e65e175bSOded Gabbay #define TPC2_EML_CS_MAX_OFFSET 0x1000 4223*e65e175bSOded Gabbay #define TPC2_EML_CS_SECTION 0x1000 4224*e65e175bSOded Gabbay #define mmTPC3_ROM_TABLE_BASE 0x7FFF600000ull 4225*e65e175bSOded Gabbay #define TPC3_ROM_TABLE_MAX_OFFSET 0x1000 4226*e65e175bSOded Gabbay #define TPC3_ROM_TABLE_SECTION 0x1000 4227*e65e175bSOded Gabbay #define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull 4228*e65e175bSOded Gabbay #define TPC3_EML_SPMU_MAX_OFFSET 0x1000 4229*e65e175bSOded Gabbay #define TPC3_EML_SPMU_SECTION 0x1000 4230*e65e175bSOded Gabbay #define mmTPC3_EML_ETF_BASE 0x7FFF602000ull 4231*e65e175bSOded Gabbay #define TPC3_EML_ETF_MAX_OFFSET 0x1000 4232*e65e175bSOded Gabbay #define TPC3_EML_ETF_SECTION 0x1000 4233*e65e175bSOded Gabbay #define mmTPC3_EML_STM_BASE 0x7FFF603000ull 4234*e65e175bSOded Gabbay #define TPC3_EML_STM_MAX_OFFSET 0x1000 4235*e65e175bSOded Gabbay #define TPC3_EML_STM_SECTION 0x2000 4236*e65e175bSOded Gabbay #define mmTPC3_EML_CTI_BASE 0x7FFF605000ull 4237*e65e175bSOded Gabbay #define TPC3_EML_CTI_MAX_OFFSET 0x1000 4238*e65e175bSOded Gabbay #define TPC3_EML_CTI_SECTION 0x1000 4239*e65e175bSOded Gabbay #define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull 4240*e65e175bSOded Gabbay #define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 4241*e65e175bSOded Gabbay #define TPC3_EML_FUNNEL_SECTION 0x1000 4242*e65e175bSOded Gabbay #define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull 4243*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 4244*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_0_SECTION 0x1000 4245*e65e175bSOded Gabbay #define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull 4246*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 4247*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_1_SECTION 0x1000 4248*e65e175bSOded Gabbay #define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull 4249*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 4250*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_2_SECTION 0x1000 4251*e65e175bSOded Gabbay #define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull 4252*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 4253*e65e175bSOded Gabbay #define TPC3_EML_BUSMON_3_SECTION 0x36000 4254*e65e175bSOded Gabbay #define mmTPC3_EML_CFG_BASE 0x7FFF640000ull 4255*e65e175bSOded Gabbay #define TPC3_EML_CFG_MAX_OFFSET 0x3380 4256*e65e175bSOded Gabbay #define TPC3_EML_CFG_SECTION 0x1000 4257*e65e175bSOded Gabbay #define mmTPC3_EML_TPC_CFG_BASE 0x7FFF641000ull 4258*e65e175bSOded Gabbay #define TPC3_EML_TPC_CFG_MAX_OFFSET 0xE400 4259*e65e175bSOded Gabbay #define TPC3_EML_TPC_CFG_SECTION 0x4000 4260*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641400ull 4261*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4262*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 4263*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641438ull 4264*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4265*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 4266*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641470ull 4267*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4268*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 4269*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF6414A8ull 4270*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4271*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 4272*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF6414E0ull 4273*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4274*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 4275*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641518ull 4276*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4277*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 4278*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641550ull 4279*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4280*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 4281*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641588ull 4282*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4283*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 4284*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF6415C0ull 4285*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4286*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 4287*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF6415F8ull 4288*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4289*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 4290*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641630ull 4291*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4292*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 4293*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641668ull 4294*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4295*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 4296*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF6416A0ull 4297*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4298*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 4299*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF6416D8ull 4300*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4301*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 4302*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641710ull 4303*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4304*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 4305*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641748ull 4306*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4307*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 4308*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull 4309*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 4310*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 4311*e65e175bSOded Gabbay #define mmKERNEL_TPC3_EML_TPC_CFG_BASE 0x7FFF641788ull 4312*e65e175bSOded Gabbay #define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 4313*e65e175bSOded Gabbay #define KERNEL_TPC3_EML_TPC_CFG_SECTION 0x2780 4314*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641A00ull 4315*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4316*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800 4317*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641A38ull 4318*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4319*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800 4320*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641A70ull 4321*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4322*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800 4323*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF641AA8ull 4324*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4325*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800 4326*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF641AE0ull 4327*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4328*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800 4329*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641B18ull 4330*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4331*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800 4332*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641B50ull 4333*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4334*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800 4335*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641B88ull 4336*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4337*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800 4338*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF641BC0ull 4339*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4340*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800 4341*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF641BF8ull 4342*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4343*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800 4344*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641C30ull 4345*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4346*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800 4347*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641C68ull 4348*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4349*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800 4350*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF641CA0ull 4351*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4352*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800 4353*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF641CD8ull 4354*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4355*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800 4356*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641D10ull 4357*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4358*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800 4359*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641D48ull 4360*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800 4361*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800 4362*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641D80ull 4363*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000 4364*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000 4365*e65e175bSOded Gabbay #define mmQM_TPC3_EML_TPC_CFG_BASE 0x7FFF641D88ull 4366*e65e175bSOded Gabbay #define QM_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800 4367*e65e175bSOded Gabbay #define QM_TPC3_EML_TPC_CFG_SECTION 0x2780 4368*e65e175bSOded Gabbay #define mmTPC3_EML_TPC_QM_BASE 0x7FFF642000ull 4369*e65e175bSOded Gabbay #define TPC3_EML_TPC_QM_MAX_OFFSET 0xD040 4370*e65e175bSOded Gabbay #define TPC3_EML_TPC_QM_SECTION 0x1BD000 4371*e65e175bSOded Gabbay #define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull 4372*e65e175bSOded Gabbay #define TPC3_EML_CS_MAX_OFFSET 0x1000 4373*e65e175bSOded Gabbay #define TPC3_EML_CS_SECTION 0x1000 4374*e65e175bSOded Gabbay #define mmTPC4_ROM_TABLE_BASE 0x7FFF800000ull 4375*e65e175bSOded Gabbay #define TPC4_ROM_TABLE_MAX_OFFSET 0x1000 4376*e65e175bSOded Gabbay #define TPC4_ROM_TABLE_SECTION 0x1000 4377*e65e175bSOded Gabbay #define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull 4378*e65e175bSOded Gabbay #define TPC4_EML_SPMU_MAX_OFFSET 0x1000 4379*e65e175bSOded Gabbay #define TPC4_EML_SPMU_SECTION 0x1000 4380*e65e175bSOded Gabbay #define mmTPC4_EML_ETF_BASE 0x7FFF802000ull 4381*e65e175bSOded Gabbay #define TPC4_EML_ETF_MAX_OFFSET 0x1000 4382*e65e175bSOded Gabbay #define TPC4_EML_ETF_SECTION 0x1000 4383*e65e175bSOded Gabbay #define mmTPC4_EML_STM_BASE 0x7FFF803000ull 4384*e65e175bSOded Gabbay #define TPC4_EML_STM_MAX_OFFSET 0x1000 4385*e65e175bSOded Gabbay #define TPC4_EML_STM_SECTION 0x2000 4386*e65e175bSOded Gabbay #define mmTPC4_EML_CTI_BASE 0x7FFF805000ull 4387*e65e175bSOded Gabbay #define TPC4_EML_CTI_MAX_OFFSET 0x1000 4388*e65e175bSOded Gabbay #define TPC4_EML_CTI_SECTION 0x1000 4389*e65e175bSOded Gabbay #define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull 4390*e65e175bSOded Gabbay #define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 4391*e65e175bSOded Gabbay #define TPC4_EML_FUNNEL_SECTION 0x1000 4392*e65e175bSOded Gabbay #define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull 4393*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 4394*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_0_SECTION 0x1000 4395*e65e175bSOded Gabbay #define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull 4396*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 4397*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_1_SECTION 0x1000 4398*e65e175bSOded Gabbay #define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull 4399*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 4400*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_2_SECTION 0x1000 4401*e65e175bSOded Gabbay #define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull 4402*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 4403*e65e175bSOded Gabbay #define TPC4_EML_BUSMON_3_SECTION 0x36000 4404*e65e175bSOded Gabbay #define mmTPC4_EML_CFG_BASE 0x7FFF840000ull 4405*e65e175bSOded Gabbay #define TPC4_EML_CFG_MAX_OFFSET 0x3380 4406*e65e175bSOded Gabbay #define TPC4_EML_CFG_SECTION 0x1000 4407*e65e175bSOded Gabbay #define mmTPC4_EML_TPC_CFG_BASE 0x7FFF841000ull 4408*e65e175bSOded Gabbay #define TPC4_EML_TPC_CFG_MAX_OFFSET 0xE400 4409*e65e175bSOded Gabbay #define TPC4_EML_TPC_CFG_SECTION 0x4000 4410*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841400ull 4411*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4412*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 4413*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841438ull 4414*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4415*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 4416*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841470ull 4417*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4418*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 4419*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF8414A8ull 4420*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4421*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 4422*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF8414E0ull 4423*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4424*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 4425*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841518ull 4426*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4427*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 4428*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841550ull 4429*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4430*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 4431*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841588ull 4432*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4433*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 4434*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF8415C0ull 4435*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4436*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 4437*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF8415F8ull 4438*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4439*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 4440*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841630ull 4441*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4442*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 4443*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841668ull 4444*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4445*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 4446*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF8416A0ull 4447*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4448*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 4449*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF8416D8ull 4450*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4451*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 4452*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841710ull 4453*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4454*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 4455*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841748ull 4456*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4457*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 4458*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull 4459*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 4460*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 4461*e65e175bSOded Gabbay #define mmKERNEL_TPC4_EML_TPC_CFG_BASE 0x7FFF841788ull 4462*e65e175bSOded Gabbay #define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 4463*e65e175bSOded Gabbay #define KERNEL_TPC4_EML_TPC_CFG_SECTION 0x2780 4464*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841A00ull 4465*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4466*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800 4467*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841A38ull 4468*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4469*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800 4470*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841A70ull 4471*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4472*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800 4473*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF841AA8ull 4474*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4475*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800 4476*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF841AE0ull 4477*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4478*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800 4479*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841B18ull 4480*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4481*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800 4482*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841B50ull 4483*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4484*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800 4485*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841B88ull 4486*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4487*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800 4488*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF841BC0ull 4489*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4490*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800 4491*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF841BF8ull 4492*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4493*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800 4494*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841C30ull 4495*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4496*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800 4497*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841C68ull 4498*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4499*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800 4500*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF841CA0ull 4501*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4502*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800 4503*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF841CD8ull 4504*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4505*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800 4506*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841D10ull 4507*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4508*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800 4509*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841D48ull 4510*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800 4511*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800 4512*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841D80ull 4513*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000 4514*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000 4515*e65e175bSOded Gabbay #define mmQM_TPC4_EML_TPC_CFG_BASE 0x7FFF841D88ull 4516*e65e175bSOded Gabbay #define QM_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800 4517*e65e175bSOded Gabbay #define QM_TPC4_EML_TPC_CFG_SECTION 0x2780 4518*e65e175bSOded Gabbay #define mmTPC4_EML_TPC_QM_BASE 0x7FFF842000ull 4519*e65e175bSOded Gabbay #define TPC4_EML_TPC_QM_MAX_OFFSET 0xD040 4520*e65e175bSOded Gabbay #define TPC4_EML_TPC_QM_SECTION 0x1BD000 4521*e65e175bSOded Gabbay #define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull 4522*e65e175bSOded Gabbay #define TPC4_EML_CS_MAX_OFFSET 0x1000 4523*e65e175bSOded Gabbay #define TPC4_EML_CS_SECTION 0x1000 4524*e65e175bSOded Gabbay #define mmTPC5_ROM_TABLE_BASE 0x7FFFA00000ull 4525*e65e175bSOded Gabbay #define TPC5_ROM_TABLE_MAX_OFFSET 0x1000 4526*e65e175bSOded Gabbay #define TPC5_ROM_TABLE_SECTION 0x1000 4527*e65e175bSOded Gabbay #define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull 4528*e65e175bSOded Gabbay #define TPC5_EML_SPMU_MAX_OFFSET 0x1000 4529*e65e175bSOded Gabbay #define TPC5_EML_SPMU_SECTION 0x1000 4530*e65e175bSOded Gabbay #define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull 4531*e65e175bSOded Gabbay #define TPC5_EML_ETF_MAX_OFFSET 0x1000 4532*e65e175bSOded Gabbay #define TPC5_EML_ETF_SECTION 0x1000 4533*e65e175bSOded Gabbay #define mmTPC5_EML_STM_BASE 0x7FFFA03000ull 4534*e65e175bSOded Gabbay #define TPC5_EML_STM_MAX_OFFSET 0x1000 4535*e65e175bSOded Gabbay #define TPC5_EML_STM_SECTION 0x2000 4536*e65e175bSOded Gabbay #define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull 4537*e65e175bSOded Gabbay #define TPC5_EML_CTI_MAX_OFFSET 0x1000 4538*e65e175bSOded Gabbay #define TPC5_EML_CTI_SECTION 0x1000 4539*e65e175bSOded Gabbay #define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull 4540*e65e175bSOded Gabbay #define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 4541*e65e175bSOded Gabbay #define TPC5_EML_FUNNEL_SECTION 0x1000 4542*e65e175bSOded Gabbay #define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull 4543*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 4544*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_0_SECTION 0x1000 4545*e65e175bSOded Gabbay #define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull 4546*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 4547*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_1_SECTION 0x1000 4548*e65e175bSOded Gabbay #define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull 4549*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 4550*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_2_SECTION 0x1000 4551*e65e175bSOded Gabbay #define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull 4552*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 4553*e65e175bSOded Gabbay #define TPC5_EML_BUSMON_3_SECTION 0x36000 4554*e65e175bSOded Gabbay #define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull 4555*e65e175bSOded Gabbay #define TPC5_EML_CFG_MAX_OFFSET 0x3380 4556*e65e175bSOded Gabbay #define TPC5_EML_CFG_SECTION 0x1000 4557*e65e175bSOded Gabbay #define mmTPC5_EML_TPC_CFG_BASE 0x7FFFA41000ull 4558*e65e175bSOded Gabbay #define TPC5_EML_TPC_CFG_MAX_OFFSET 0xE400 4559*e65e175bSOded Gabbay #define TPC5_EML_TPC_CFG_SECTION 0x4000 4560*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41400ull 4561*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4562*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 4563*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41438ull 4564*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4565*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 4566*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41470ull 4567*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4568*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 4569*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA414A8ull 4570*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4571*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 4572*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA414E0ull 4573*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4574*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 4575*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41518ull 4576*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4577*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 4578*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41550ull 4579*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4580*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 4581*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41588ull 4582*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4583*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 4584*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA415C0ull 4585*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4586*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 4587*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA415F8ull 4588*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4589*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 4590*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41630ull 4591*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4592*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 4593*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41668ull 4594*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4595*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 4596*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA416A0ull 4597*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4598*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 4599*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA416D8ull 4600*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4601*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 4602*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41710ull 4603*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4604*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 4605*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41748ull 4606*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4607*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 4608*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull 4609*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 4610*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 4611*e65e175bSOded Gabbay #define mmKERNEL_TPC5_EML_TPC_CFG_BASE 0x7FFFA41788ull 4612*e65e175bSOded Gabbay #define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 4613*e65e175bSOded Gabbay #define KERNEL_TPC5_EML_TPC_CFG_SECTION 0x2780 4614*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A00ull 4615*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4616*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800 4617*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A38ull 4618*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4619*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800 4620*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A70ull 4621*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4622*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800 4623*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AA8ull 4624*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4625*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800 4626*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AE0ull 4627*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4628*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800 4629*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B18ull 4630*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4631*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800 4632*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B50ull 4633*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4634*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800 4635*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B88ull 4636*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4637*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800 4638*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BC0ull 4639*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4640*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800 4641*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BF8ull 4642*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4643*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800 4644*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C30ull 4645*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4646*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800 4647*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C68ull 4648*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4649*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800 4650*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CA0ull 4651*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4652*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800 4653*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CD8ull 4654*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4655*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800 4656*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D10ull 4657*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4658*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800 4659*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D48ull 4660*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800 4661*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800 4662*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D80ull 4663*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000 4664*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000 4665*e65e175bSOded Gabbay #define mmQM_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D88ull 4666*e65e175bSOded Gabbay #define QM_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800 4667*e65e175bSOded Gabbay #define QM_TPC5_EML_TPC_CFG_SECTION 0x2780 4668*e65e175bSOded Gabbay #define mmTPC5_EML_TPC_QM_BASE 0x7FFFA42000ull 4669*e65e175bSOded Gabbay #define TPC5_EML_TPC_QM_MAX_OFFSET 0xD040 4670*e65e175bSOded Gabbay #define TPC5_EML_TPC_QM_SECTION 0x1BD000 4671*e65e175bSOded Gabbay #define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull 4672*e65e175bSOded Gabbay #define TPC5_EML_CS_MAX_OFFSET 0x1000 4673*e65e175bSOded Gabbay #define TPC5_EML_CS_SECTION 0x1000 4674*e65e175bSOded Gabbay #define mmTPC6_ROM_TABLE_BASE 0x7FFFC00000ull 4675*e65e175bSOded Gabbay #define TPC6_ROM_TABLE_MAX_OFFSET 0x1000 4676*e65e175bSOded Gabbay #define TPC6_ROM_TABLE_SECTION 0x1000 4677*e65e175bSOded Gabbay #define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull 4678*e65e175bSOded Gabbay #define TPC6_EML_SPMU_MAX_OFFSET 0x1000 4679*e65e175bSOded Gabbay #define TPC6_EML_SPMU_SECTION 0x1000 4680*e65e175bSOded Gabbay #define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull 4681*e65e175bSOded Gabbay #define TPC6_EML_ETF_MAX_OFFSET 0x1000 4682*e65e175bSOded Gabbay #define TPC6_EML_ETF_SECTION 0x1000 4683*e65e175bSOded Gabbay #define mmTPC6_EML_STM_BASE 0x7FFFC03000ull 4684*e65e175bSOded Gabbay #define TPC6_EML_STM_MAX_OFFSET 0x1000 4685*e65e175bSOded Gabbay #define TPC6_EML_STM_SECTION 0x2000 4686*e65e175bSOded Gabbay #define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull 4687*e65e175bSOded Gabbay #define TPC6_EML_CTI_MAX_OFFSET 0x1000 4688*e65e175bSOded Gabbay #define TPC6_EML_CTI_SECTION 0x1000 4689*e65e175bSOded Gabbay #define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull 4690*e65e175bSOded Gabbay #define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 4691*e65e175bSOded Gabbay #define TPC6_EML_FUNNEL_SECTION 0x1000 4692*e65e175bSOded Gabbay #define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull 4693*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 4694*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_0_SECTION 0x1000 4695*e65e175bSOded Gabbay #define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull 4696*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 4697*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_1_SECTION 0x1000 4698*e65e175bSOded Gabbay #define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull 4699*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 4700*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_2_SECTION 0x1000 4701*e65e175bSOded Gabbay #define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull 4702*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 4703*e65e175bSOded Gabbay #define TPC6_EML_BUSMON_3_SECTION 0x36000 4704*e65e175bSOded Gabbay #define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull 4705*e65e175bSOded Gabbay #define TPC6_EML_CFG_MAX_OFFSET 0x3380 4706*e65e175bSOded Gabbay #define TPC6_EML_CFG_SECTION 0x1000 4707*e65e175bSOded Gabbay #define mmTPC6_EML_TPC_CFG_BASE 0x7FFFC41000ull 4708*e65e175bSOded Gabbay #define TPC6_EML_TPC_CFG_MAX_OFFSET 0xE400 4709*e65e175bSOded Gabbay #define TPC6_EML_TPC_CFG_SECTION 0x4000 4710*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41400ull 4711*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4712*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 4713*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41438ull 4714*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4715*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 4716*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41470ull 4717*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4718*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 4719*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC414A8ull 4720*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4721*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 4722*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC414E0ull 4723*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4724*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 4725*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41518ull 4726*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4727*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 4728*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41550ull 4729*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4730*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 4731*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41588ull 4732*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4733*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 4734*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC415C0ull 4735*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4736*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 4737*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC415F8ull 4738*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4739*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 4740*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41630ull 4741*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4742*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 4743*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41668ull 4744*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4745*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 4746*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC416A0ull 4747*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4748*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 4749*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC416D8ull 4750*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4751*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 4752*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41710ull 4753*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4754*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 4755*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41748ull 4756*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4757*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 4758*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull 4759*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 4760*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 4761*e65e175bSOded Gabbay #define mmKERNEL_TPC6_EML_TPC_CFG_BASE 0x7FFFC41788ull 4762*e65e175bSOded Gabbay #define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 4763*e65e175bSOded Gabbay #define KERNEL_TPC6_EML_TPC_CFG_SECTION 0x2780 4764*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A00ull 4765*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4766*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800 4767*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A38ull 4768*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4769*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800 4770*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A70ull 4771*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4772*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800 4773*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AA8ull 4774*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4775*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800 4776*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AE0ull 4777*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4778*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800 4779*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B18ull 4780*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4781*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800 4782*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B50ull 4783*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4784*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800 4785*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B88ull 4786*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4787*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800 4788*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BC0ull 4789*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4790*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800 4791*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BF8ull 4792*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4793*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800 4794*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C30ull 4795*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4796*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800 4797*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C68ull 4798*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4799*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800 4800*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CA0ull 4801*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4802*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800 4803*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CD8ull 4804*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4805*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800 4806*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D10ull 4807*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4808*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800 4809*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D48ull 4810*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800 4811*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800 4812*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D80ull 4813*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000 4814*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000 4815*e65e175bSOded Gabbay #define mmQM_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D88ull 4816*e65e175bSOded Gabbay #define QM_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800 4817*e65e175bSOded Gabbay #define QM_TPC6_EML_TPC_CFG_SECTION 0x2780 4818*e65e175bSOded Gabbay #define mmTPC6_EML_TPC_QM_BASE 0x7FFFC42000ull 4819*e65e175bSOded Gabbay #define TPC6_EML_TPC_QM_MAX_OFFSET 0xD040 4820*e65e175bSOded Gabbay #define TPC6_EML_TPC_QM_SECTION 0x1BD000 4821*e65e175bSOded Gabbay #define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull 4822*e65e175bSOded Gabbay #define TPC6_EML_CS_MAX_OFFSET 0x1000 4823*e65e175bSOded Gabbay #define TPC6_EML_CS_SECTION 0x1000 4824*e65e175bSOded Gabbay #define mmTPC7_ROM_TABLE_BASE 0x7FFFE00000ull 4825*e65e175bSOded Gabbay #define TPC7_ROM_TABLE_MAX_OFFSET 0x1000 4826*e65e175bSOded Gabbay #define TPC7_ROM_TABLE_SECTION 0x1000 4827*e65e175bSOded Gabbay #define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull 4828*e65e175bSOded Gabbay #define TPC7_EML_SPMU_MAX_OFFSET 0x1000 4829*e65e175bSOded Gabbay #define TPC7_EML_SPMU_SECTION 0x1000 4830*e65e175bSOded Gabbay #define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull 4831*e65e175bSOded Gabbay #define TPC7_EML_ETF_MAX_OFFSET 0x1000 4832*e65e175bSOded Gabbay #define TPC7_EML_ETF_SECTION 0x1000 4833*e65e175bSOded Gabbay #define mmTPC7_EML_STM_BASE 0x7FFFE03000ull 4834*e65e175bSOded Gabbay #define TPC7_EML_STM_MAX_OFFSET 0x1000 4835*e65e175bSOded Gabbay #define TPC7_EML_STM_SECTION 0x2000 4836*e65e175bSOded Gabbay #define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull 4837*e65e175bSOded Gabbay #define TPC7_EML_CTI_MAX_OFFSET 0x1000 4838*e65e175bSOded Gabbay #define TPC7_EML_CTI_SECTION 0x1000 4839*e65e175bSOded Gabbay #define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull 4840*e65e175bSOded Gabbay #define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000 4841*e65e175bSOded Gabbay #define TPC7_EML_FUNNEL_SECTION 0x1000 4842*e65e175bSOded Gabbay #define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull 4843*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000 4844*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_0_SECTION 0x1000 4845*e65e175bSOded Gabbay #define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull 4846*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000 4847*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_1_SECTION 0x1000 4848*e65e175bSOded Gabbay #define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull 4849*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000 4850*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_2_SECTION 0x1000 4851*e65e175bSOded Gabbay #define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull 4852*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000 4853*e65e175bSOded Gabbay #define TPC7_EML_BUSMON_3_SECTION 0x36000 4854*e65e175bSOded Gabbay #define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull 4855*e65e175bSOded Gabbay #define TPC7_EML_CFG_MAX_OFFSET 0x3380 4856*e65e175bSOded Gabbay #define TPC7_EML_CFG_SECTION 0x1000 4857*e65e175bSOded Gabbay #define mmTPC7_EML_TPC_CFG_BASE 0x7FFFE41000ull 4858*e65e175bSOded Gabbay #define TPC7_EML_TPC_CFG_MAX_OFFSET 0xE400 4859*e65e175bSOded Gabbay #define TPC7_EML_TPC_CFG_SECTION 0x4000 4860*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41400ull 4861*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4862*e65e175bSOded Gabbay #define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 4863*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41438ull 4864*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4865*e65e175bSOded Gabbay #define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 4866*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41470ull 4867*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4868*e65e175bSOded Gabbay #define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 4869*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE414A8ull 4870*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4871*e65e175bSOded Gabbay #define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 4872*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE414E0ull 4873*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4874*e65e175bSOded Gabbay #define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 4875*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41518ull 4876*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4877*e65e175bSOded Gabbay #define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 4878*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41550ull 4879*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4880*e65e175bSOded Gabbay #define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 4881*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41588ull 4882*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4883*e65e175bSOded Gabbay #define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 4884*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE415C0ull 4885*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4886*e65e175bSOded Gabbay #define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 4887*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE415F8ull 4888*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4889*e65e175bSOded Gabbay #define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 4890*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41630ull 4891*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4892*e65e175bSOded Gabbay #define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 4893*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41668ull 4894*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4895*e65e175bSOded Gabbay #define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 4896*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE416A0ull 4897*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4898*e65e175bSOded Gabbay #define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 4899*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE416D8ull 4900*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4901*e65e175bSOded Gabbay #define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 4902*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41710ull 4903*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4904*e65e175bSOded Gabbay #define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 4905*e65e175bSOded Gabbay #define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41748ull 4906*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4907*e65e175bSOded Gabbay #define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 4908*e65e175bSOded Gabbay #define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull 4909*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 4910*e65e175bSOded Gabbay #define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 4911*e65e175bSOded Gabbay #define mmKERNEL_TPC7_EML_TPC_CFG_BASE 0x7FFFE41788ull 4912*e65e175bSOded Gabbay #define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 4913*e65e175bSOded Gabbay #define KERNEL_TPC7_EML_TPC_CFG_SECTION 0x2780 4914*e65e175bSOded Gabbay #define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A00ull 4915*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4916*e65e175bSOded Gabbay #define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800 4917*e65e175bSOded Gabbay #define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A38ull 4918*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4919*e65e175bSOded Gabbay #define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800 4920*e65e175bSOded Gabbay #define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A70ull 4921*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4922*e65e175bSOded Gabbay #define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800 4923*e65e175bSOded Gabbay #define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AA8ull 4924*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4925*e65e175bSOded Gabbay #define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800 4926*e65e175bSOded Gabbay #define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AE0ull 4927*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4928*e65e175bSOded Gabbay #define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800 4929*e65e175bSOded Gabbay #define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B18ull 4930*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4931*e65e175bSOded Gabbay #define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800 4932*e65e175bSOded Gabbay #define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B50ull 4933*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4934*e65e175bSOded Gabbay #define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800 4935*e65e175bSOded Gabbay #define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B88ull 4936*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4937*e65e175bSOded Gabbay #define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800 4938*e65e175bSOded Gabbay #define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BC0ull 4939*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4940*e65e175bSOded Gabbay #define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800 4941*e65e175bSOded Gabbay #define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BF8ull 4942*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4943*e65e175bSOded Gabbay #define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800 4944*e65e175bSOded Gabbay #define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C30ull 4945*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4946*e65e175bSOded Gabbay #define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800 4947*e65e175bSOded Gabbay #define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C68ull 4948*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4949*e65e175bSOded Gabbay #define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800 4950*e65e175bSOded Gabbay #define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CA0ull 4951*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4952*e65e175bSOded Gabbay #define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800 4953*e65e175bSOded Gabbay #define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CD8ull 4954*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4955*e65e175bSOded Gabbay #define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800 4956*e65e175bSOded Gabbay #define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D10ull 4957*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4958*e65e175bSOded Gabbay #define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800 4959*e65e175bSOded Gabbay #define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D48ull 4960*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800 4961*e65e175bSOded Gabbay #define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800 4962*e65e175bSOded Gabbay #define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D80ull 4963*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000 4964*e65e175bSOded Gabbay #define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000 4965*e65e175bSOded Gabbay #define mmQM_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D88ull 4966*e65e175bSOded Gabbay #define QM_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800 4967*e65e175bSOded Gabbay #define QM_TPC7_EML_TPC_CFG_SECTION 0x2780 4968*e65e175bSOded Gabbay #define mmTPC7_EML_TPC_QM_BASE 0x7FFFE42000ull 4969*e65e175bSOded Gabbay #define TPC7_EML_TPC_QM_MAX_OFFSET 0xD040 4970*e65e175bSOded Gabbay #define TPC7_EML_TPC_QM_SECTION 0x1BD000 4971*e65e175bSOded Gabbay #define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull 4972*e65e175bSOded Gabbay #define TPC7_EML_CS_MAX_OFFSET 0x1000 4973*e65e175bSOded Gabbay 4974*e65e175bSOded Gabbay #endif /* GAUDI_BLOCKS_H_ */ 4975