xref: /linux/drivers/net/wireless/rsi/rsi_hal.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1 /*
2  * Copyright (c) 2017 Redpine Signals Inc.
3  *
4  * Permission to use, copy, modify, and/or distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  */
16 
17 #ifndef __RSI_HAL_H__
18 #define __RSI_HAL_H__
19 
20 /* Device Operating modes */
21 #define DEV_OPMODE_WIFI_ALONE		1
22 #define DEV_OPMODE_BT_ALONE		4
23 #define DEV_OPMODE_BT_LE_ALONE		8
24 #define DEV_OPMODE_BT_DUAL		12
25 #define DEV_OPMODE_STA_BT		5
26 #define DEV_OPMODE_STA_BT_LE		9
27 #define DEV_OPMODE_STA_BT_DUAL		13
28 #define DEV_OPMODE_AP_BT		6
29 #define DEV_OPMODE_AP_BT_DUAL		14
30 
31 #define DEV_OPMODE_PARAM_DESC		\
32 	__stringify(DEV_OPMODE_WIFI_ALONE)	"[Wi-Fi alone], "	\
33 	__stringify(DEV_OPMODE_BT_ALONE)	"[BT classic alone], "	\
34 	__stringify(DEV_OPMODE_BT_LE_ALONE)	"[BT LE alone], "	\
35 	__stringify(DEV_OPMODE_BT_DUAL)		"[BT classic + BT LE alone], " \
36 	__stringify(DEV_OPMODE_STA_BT)		"[Wi-Fi STA + BT classic], " \
37 	__stringify(DEV_OPMODE_STA_BT_LE)	"[Wi-Fi STA + BT LE], "	\
38 	__stringify(DEV_OPMODE_STA_BT_DUAL)	"[Wi-Fi STA + BT classic + BT LE], " \
39 	__stringify(DEV_OPMODE_AP_BT)		"[Wi-Fi AP + BT classic], "	\
40 	__stringify(DEV_OPMODE_AP_BT_DUAL)	"[Wi-Fi AP + BT classic + BT LE]"
41 
42 #define FLASH_WRITE_CHUNK_SIZE		(4 * 1024)
43 #define FLASH_SECTOR_SIZE		(4 * 1024)
44 
45 #define FLASH_SIZE_ADDR			0x04000016
46 #define PING_BUFFER_ADDRESS		0x19000
47 #define PONG_BUFFER_ADDRESS		0x1a000
48 #define SWBL_REGIN			0x41050034
49 #define SWBL_REGOUT			0x4105003c
50 #define PING_WRITE			0x1
51 #define PONG_WRITE			0x2
52 
53 #define BL_CMD_TIMEOUT			2000
54 #define BL_BURN_TIMEOUT			(50 * 1000)
55 
56 #define REGIN_VALID			0xA
57 #define REGIN_INPUT			0xA0
58 #define REGOUT_VALID			0xAB
59 #define REGOUT_INVALID			(~0xAB)
60 #define CMD_PASS			0xAA
61 #define CMD_FAIL			0xCC
62 
63 #define LOAD_HOSTED_FW			'A'
64 #define BURN_HOSTED_FW			'B'
65 #define PING_VALID			'I'
66 #define PONG_VALID			'O'
67 #define PING_AVAIL			'I'
68 #define PONG_AVAIL			'O'
69 #define EOF_REACHED			'E'
70 #define CHECK_CRC			'K'
71 #define POLLING_MODE			'P'
72 #define AUTO_READ_MODE			'R'
73 #define JUMP_TO_ZERO_PC			'J'
74 #define FW_LOADING_SUCCESSFUL		'S'
75 #define LOADING_INITIATED		'1'
76 
77 #define RSI_ULP_RESET_REG		0x161
78 #define RSI_WATCH_DOG_TIMER_1		0x16c
79 #define RSI_WATCH_DOG_TIMER_2		0x16d
80 #define RSI_WATCH_DOG_DELAY_TIMER_1		0x16e
81 #define RSI_WATCH_DOG_DELAY_TIMER_2		0x16f
82 #define RSI_WATCH_DOG_TIMER_ENABLE		0x170
83 
84 /* Watchdog timer addresses for 9116 */
85 #define NWP_AHB_BASE_ADDR		0x41300000
86 #define NWP_WWD_INTERRUPT_TIMER		(NWP_AHB_BASE_ADDR + 0x300)
87 #define NWP_WWD_SYSTEM_RESET_TIMER	(NWP_AHB_BASE_ADDR + 0x304)
88 #define NWP_WWD_WINDOW_TIMER		(NWP_AHB_BASE_ADDR + 0x308)
89 #define NWP_WWD_TIMER_SETTINGS		(NWP_AHB_BASE_ADDR + 0x30C)
90 #define NWP_WWD_MODE_AND_RSTART		(NWP_AHB_BASE_ADDR + 0x310)
91 #define NWP_WWD_RESET_BYPASS		(NWP_AHB_BASE_ADDR + 0x314)
92 #define NWP_FSM_INTR_MASK_REG		(NWP_AHB_BASE_ADDR + 0x104)
93 
94 /* Watchdog timer values */
95 #define NWP_WWD_INT_TIMER_CLKS		5
96 #define NWP_WWD_SYS_RESET_TIMER_CLKS	4
97 #define NWP_WWD_TIMER_DISABLE		0xAA0001
98 
99 #define RSI_ULP_WRITE_0			00
100 #define RSI_ULP_WRITE_2			02
101 #define RSI_ULP_WRITE_50		50
102 
103 #define RSI_RESTART_WDT			BIT(11)
104 #define RSI_BYPASS_ULP_ON_WDT		BIT(1)
105 
106 #define RSI_ULP_TIMER_ENABLE		((0xaa000) | RSI_RESTART_WDT |	\
107 					 RSI_BYPASS_ULP_ON_WDT)
108 #define RSI_RF_SPI_PROG_REG_BASE_ADDR	0x40080000
109 
110 #define RSI_GSPI_CTRL_REG0		(RSI_RF_SPI_PROG_REG_BASE_ADDR)
111 #define RSI_GSPI_CTRL_REG1		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x2)
112 #define RSI_GSPI_DATA_REG0		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x4)
113 #define RSI_GSPI_DATA_REG1		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x6)
114 #define RSI_GSPI_DATA_REG2		(RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x8)
115 
116 #define RSI_GSPI_CTRL_REG0_VALUE		0x340
117 
118 #define RSI_GSPI_DMA_MODE			BIT(13)
119 
120 #define RSI_GSPI_2_ULP			BIT(12)
121 #define RSI_GSPI_TRIG			BIT(7)
122 #define RSI_GSPI_READ			BIT(6)
123 #define RSI_GSPI_RF_SPI_ACTIVE		BIT(8)
124 
125 /* Boot loader commands */
126 #define SEND_RPS_FILE			'2'
127 
128 #define FW_IMAGE_MIN_ADDRESS		(68 * 1024)
129 #define MAX_FLASH_FILE_SIZE		(400 * 1024) //400K
130 #define FLASH_START_ADDRESS		16
131 
132 #define COMMON_HAL_CARD_READY_IND	0x0
133 
134 #define COMMAN_HAL_WAIT_FOR_CARD_READY	1
135 
136 #define RSI_DEV_OPMODE_WIFI_ALONE	1
137 #define RSI_DEV_COEX_MODE_WIFI_ALONE	1
138 
139 #define BBP_INFO_40MHZ 0x6
140 
141 #define FW_FLASH_OFFSET			0x820
142 #define LMAC_VER_OFFSET_9113		(FW_FLASH_OFFSET + 0x200)
143 #define LMAC_VER_OFFSET_9116		0x22C2
144 #define MAX_DWORD_ALIGN_BYTES		64
145 #define RSI_COMMON_REG_SIZE		2
146 #define RSI_9116_REG_SIZE		4
147 #define FW_ALIGN_SIZE			4
148 #define RSI_9116_FW_MAGIC_WORD		0x5aa5
149 
150 #define MEM_ACCESS_CTRL_FROM_HOST	0x41300000
151 #define RAM_384K_ACCESS_FROM_TA		(BIT(2) | BIT(3) | BIT(4) | BIT(5) | \
152 					 BIT(20) | BIT(21) | BIT(22) | \
153 					 BIT(23) | BIT(24) | BIT(25))
154 
155 struct bl_header {
156 	__le32 flags;
157 	__le32 image_no;
158 	__le32 check_sum;
159 	__le32 flash_start_address;
160 	__le32 flash_len;
161 } __packed;
162 
163 struct ta_metadata {
164 	char *name;
165 	unsigned int address;
166 };
167 
168 #define RSI_BL_CTRL_LEN_MASK			0xFFFFFF
169 #define RSI_BL_CTRL_SPI_32BIT_MODE		BIT(27)
170 #define RSI_BL_CTRL_REL_TA_SOFTRESET		BIT(28)
171 #define RSI_BL_CTRL_START_FROM_ROM_PC		BIT(29)
172 #define RSI_BL_CTRL_SPI_8BIT_MODE		BIT(30)
173 #define RSI_BL_CTRL_LAST_ENTRY			BIT(31)
174 struct bootload_entry {
175 	__le32 control;
176 	__le32 dst_addr;
177 } __packed;
178 
179 struct bootload_ds {
180 	__le16 fixed_pattern;
181 	__le16 offset;
182 	__le32 reserved;
183 	struct bootload_entry bl_entry[7];
184 } __packed;
185 
186 struct rsi_mgmt_desc {
187 	__le16 len_qno;
188 	u8 frame_type;
189 	u8 misc_flags;
190 	u8 xtend_desc_size;
191 	u8 header_len;
192 	__le16 frame_info;
193 	__le16 rate_info;
194 	__le16 bbp_info;
195 	__le16 seq_ctrl;
196 	u8 reserved2;
197 	u8 sta_id;
198 } __packed;
199 
200 struct rsi_data_desc {
201 	__le16 len_qno;
202 	u8 cfm_frame_type;
203 	u8 misc_flags;
204 	u8 xtend_desc_size;
205 	u8 header_len;
206 	__le16 frame_info;
207 	__le16 rate_info;
208 	__le16 bbp_info;
209 	__le16 mac_flags;
210 	u8 qid_tid;
211 	u8 sta_id;
212 } __packed;
213 
214 struct rsi_bt_desc {
215 	__le16 len_qno;
216 	__le16 reserved1;
217 	__le32 reserved2;
218 	__le32 reserved3;
219 	__le16 reserved4;
220 	__le16 bt_pkt_type;
221 } __packed;
222 
223 int rsi_hal_device_init(struct rsi_hw *adapter);
224 int rsi_prepare_mgmt_desc(struct rsi_common *common, struct sk_buff *skb);
225 int rsi_prepare_data_desc(struct rsi_common *common, struct sk_buff *skb);
226 int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb);
227 int rsi_send_pkt_to_bus(struct rsi_common *common, struct sk_buff *skb);
228 int rsi_send_bt_pkt(struct rsi_common *common, struct sk_buff *skb);
229 
230 #endif
231