28 		[1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf),  in mt7603_set_tmac_template()
36 	for (i = 0; i < ARRAY_SIZE(desc); i++)  in mt7603_set_tmac_template()
50 	int reserved_count = 0;  in mt7603_dma_sched_init()
65 	mt76_wr(dev, MT_HIGH_PRIORITY_1, 0x55555553);  in mt7603_dma_sched_init()
66 	mt76_wr(dev, MT_HIGH_PRIORITY_2, 0x78555555);  in mt7603_dma_sched_init()
68 	mt76_wr(dev, MT_QUEUE_PRIORITY_1, 0x2b1a096e);  in mt7603_dma_sched_init()
69 	mt76_wr(dev, MT_QUEUE_PRIORITY_2, 0x785f4d3c);  in mt7603_dma_sched_init()
71 	mt76_wr(dev, MT_PRIORITY_MASK, 0xffffffff);  in mt7603_dma_sched_init()
76 	for (i = 0; i <= 4; i++)  in mt7603_dma_sched_init()
90 		reserved_count = 0;  in mt7603_dma_sched_init()
95 		mt76_wr(dev, MT_GROUP_THRESH(0),  in mt7603_dma_sched_init()
98 		mt76_wr(dev, MT_BMAP_0, 0x0080ff5f);  in mt7603_dma_sched_init()
100 		mt76_wr(dev, MT_BMAP_1, 0x00000020);  in mt7603_dma_sched_init()
102 		mt76_wr(dev, MT_GROUP_THRESH(0), page_count);  in mt7603_dma_sched_init()
103 		mt76_wr(dev, MT_BMAP_0, 0xffff);  in mt7603_dma_sched_init()
106 	mt76_wr(dev, MT_SCH_4, 0);  in mt7603_dma_sched_init()
108 	for (i = 0; i <= 15; i++)  in mt7603_dma_sched_init()
109 		mt76_wr(dev, MT_TXTIME_THRESH(i), 0xfffff);  in mt7603_dma_sched_init()
129 	dev->agc0 = mt76_rr(dev, MT_AGC(0));  in mt7603_phy_init()
141 		(MT_AGG_SIZE_LIMIT(0) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |  in mt7603_mac_init()
147 		(MT_AGG_SIZE_LIMIT(4) << 0 * MT_AGG_BA_SIZE_LIMIT_SHIFT) |  in mt7603_mac_init()
153 		FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |  in mt7603_mac_init()
159 		FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) |  in mt7603_mac_init()
165 		FIELD_PREP(MT_AGG_CONTROL_BAR_RATE, 0x4b) |  in mt7603_mac_init()
166 		FIELD_PREP(MT_AGG_CONTROL_CFEND_RATE, 0x69) |  in mt7603_mac_init()
176 	mt76_rmw(dev, MT_DMA_VCFR0, BIT(0), BIT(13));  in mt7603_mac_init()
177 	mt76_rmw(dev, MT_DMA_TMCFR0, BIT(0) | BIT(1), BIT(13));  in mt7603_mac_init()
182 	mt76_rmw(dev, MT_WF_RMAC_MAXMINLEN, 0xffffff, 0x19000);  in mt7603_mac_init()
184 	mt76_wr(dev, MT_WF_RFCR1, 0);  in mt7603_mac_init()
190 			 MT_TMAC_TCR_TXOP_BURST_STOP | BIT(1) | BIT(0));  in mt7603_mac_init()
213 	mt76_wr(dev, MT_DMA_RCFR0, 0xc0000000);  in mt7603_mac_init()
228 	for (i = 0; i < MT7603_WTBL_SIZE; i++)  in mt7603_mac_init()
241 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) |  in mt7603_mac_init()
251 		FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), MT7603_RATE_RETRY - 1) |  in mt7603_mac_init()
272 	for (i = 0; i <= 4; i++)  in mt7603_mac_init()
282 	mt76_wr(dev, MT_INT_SOURCE_CSR, ~0);  in mt7603_init_hardware()
285 	if (ret < 0)  in mt7603_init_hardware()
292 	mt76_wr(dev, MT_WPDMA_GLO_CFG, 0x52000850);  in mt7603_init_hardware()
297 	for (i = 0; i < MT7603_WTBL_SIZE; i++) {  in mt7603_init_hardware()
300 		mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);  in mt7603_init_hardware()
312 	return 0;  in mt7603_init_hardware()
348 	val = FIELD_PREP(MT_LED_STATUS_DURATION, 0xffff) |  in mt7603_led_set_config()
377 	return 0;  in mt7603_led_set_blink()
387 		mt7603_led_set_config(mphy, 0, 0xff);  in mt7603_led_set_brightness()
389 		mt7603_led_set_config(mphy, 0xff, 0);  in mt7603_led_set_brightness()
394 	if (addr < 0x100000)  in __mt7603_reg_addr()
442 		return 0;  in mt7603_txpower_signed()
444 	val &= GENMASK(5, 0);  in mt7603_txpower_signed()
465 	if (ext_pa && is_mt7603(dev) && ext_pa_pwr != 0 && ext_pa_pwr != 0xff)  in mt7603_init_txpower()
469 		target_power = -(target_power & GENMASK(5, 0));  in mt7603_init_txpower()
471 	max_offset = 0;  in mt7603_init_txpower()
472 	for (i = 0; i < 14; i++) {  in mt7603_init_txpower()
488 	for (i = 0; i < sband->n_channels; i++) {  in mt7603_init_txpower()
561 	return 0;  in mt7603_register_device()