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/linux/include/linux/
H A Dkernelcapi.h19 #define CAPI_NOERROR 0x0000
21 #define CAPI_TOOMANYAPPLS 0x1001
22 #define CAPI_LOGBLKSIZETOSMALL 0x1002
23 #define CAPI_BUFFEXECEEDS64K 0x1003
24 #define CAPI_MSGBUFSIZETOOSMALL 0x1004
25 #define CAPI_ANZLOGCONNNOTSUPPORTED 0x1005
26 #define CAPI_REGRESERVED 0x1006
27 #define CAPI_REGBUSY 0x1007
28 #define CAPI_REGOSRESOURCEERR 0x1008
29 #define CAPI_REGNOTINSTALLED 0x1009
[all …]
H A DmISDNif.h43 * <16 bit 0 >
58 #define MISDN_CMDMASK 0xff00
59 #define MISDN_LAYERMASK 0x00ff
62 #define OPEN_CHANNEL 0x0100
63 #define CLOSE_CHANNEL 0x0200
64 #define CONTROL_CHANNEL 0x0300
65 #define CHECK_DATA 0x0400
68 #define PH_ACTIVATE_REQ 0x0101
69 #define PH_DEACTIVATE_REQ 0x0201
70 #define PH_DATA_REQ 0x2001
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dbrcm,bcm74110-mbox.yaml58 reg = <0xa552000 0x1104>;
59 interrupts = <GIC_SPI 0x67 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 0x66 IRQ_TYPE_LEVEL_HIGH>;
61 #mbox-cells = <0x2>;
62 brcm,rx = <0x7>;
63 brcm,tx = <0x6>;
/linux/sound/mips/
H A Dhal2.h15 #define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */
16 #define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */
17 #define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */
18 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
19 #define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
23 #define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */
24 #define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */
25 #define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */
26 #define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
37 #define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */
[all …]
/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux/sound/soc/kirkwood/
H A Dkirkwood.h13 #define KIRKWOOD_RECORD_WIN 0
17 #define KIRKWOOD_AUDIO_WIN_BASE_REG(win) (0xA00 + ((win)<<3))
18 #define KIRKWOOD_AUDIO_WIN_CTRL_REG(win) (0xA04 + ((win)<<3))
21 #define KIRKWOOD_RECCTL 0x1000
31 #define KIRKWOOD_RECCTL_MONO_CHAN_LEFT (0<<3)
32 #define KIRKWOOD_RECCTL_SIZE_MASK (7<<0)
33 #define KIRKWOOD_RECCTL_SIZE_16 (7<<0)
34 #define KIRKWOOD_RECCTL_SIZE_16_C (3<<0)
35 #define KIRKWOOD_RECCTL_SIZE_20 (2<<0)
36 #define KIRKWOOD_RECCTL_SIZE_24 (1<<0)
[all …]
/linux/arch/arm/mach-s5pv210/
H A Dregs-clock.h12 #define S3C_ADDR_BASE 0xF6000000
14 #define S3C_VA_SYS S3C_ADDR(0x00100000)
18 #define S5P_APLL_LOCK S5P_CLKREG(0x00)
19 #define S5P_MPLL_LOCK S5P_CLKREG(0x08)
20 #define S5P_EPLL_LOCK S5P_CLKREG(0x10)
21 #define S5P_VPLL_LOCK S5P_CLKREG(0x20)
23 #define S5P_APLL_CON S5P_CLKREG(0x100)
24 #define S5P_MPLL_CON S5P_CLKREG(0x108)
25 #define S5P_EPLL_CON S5P_CLKREG(0x110)
26 #define S5P_EPLL_CON1 S5P_CLKREG(0x114)
[all …]
/linux/drivers/net/dsa/xrs700x/
H A Dxrs700x_reg.h4 #define XRS_DEVICE_ID_BASE 0x0
5 #define XRS_GPIO_BASE 0x10000
6 #define XRS_PORT_OFFSET 0x10000
7 #define XRS_PORT_BASE(x) (0x200000 + XRS_PORT_OFFSET * (x))
8 #define XRS_RTC_BASE 0x280000
9 #define XRS_TS_OFFSET 0x8000
10 #define XRS_TS_BASE(x) (0x290000 + XRS_TS_OFFSET * (x))
11 #define XRS_SWITCH_CONF_BASE 0x300000
14 #define XRS_DEV_ID0 (XRS_DEVICE_ID_BASE + 0)
21 #define XRS_CONFIG0 (XRS_GPIO_BASE + 0x1000)
[all …]
/linux/drivers/ata/
H A Dpata_sil680.c52 return 0xA0 + (ap->port_no << 4) + r; in sil680_selreg()
68 return 0xA0 + (ap->port_no << 4) + r + (adev->devno << 1); in sil680_seldev()
83 int addr = sil680_selreg(ap, 0); in sil680_cable_detect()
106 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 in sil680_set_piomode()
109 0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1 in sil680_set_piomode()
112 int tfaddr = sil680_selreg(ap, 0x02); in sil680_set_piomode()
113 int addr = sil680_seldev(ap, adev, 0x04); in sil680_set_piomode()
114 int addr_mask = 0x80 + 4 * ap->port_no; in sil680_set_piomode()
133 reg &= ~0x0200; /* Clear IORDY */ in sil680_set_piomode()
137 reg |= 0x0200; /* Enable IORDY */ in sil680_set_piomode()
[all …]
H A Dpata_pdc2027x.c37 PDC_UDMA_100 = 0,
43 PDC_SYS_CTL = 0x1100,
44 PDC_ATA_CTL = 0x1104,
45 PDC_GLOBAL_CTL = 0x1108,
46 PDC_CTCR0 = 0x110C,
47 PDC_CTCR1 = 0x1110,
48 PDC_BYTE_COUNT = 0x1120,
49 PDC_PLL_CTL = 0x1202,
75 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
76 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h23 #define SPEED_0 0xffff
30 #define MEDIA_TYPE_AUTO_SENSOR 0
33 #define REG_PM_CTRLSTAT 0x44
35 #define REG_PCIE_CAP_LIST 0x58
37 #define REG_VPD_CAP 0x6C
38 #define VPD_CAP_ID_MASK 0xFF
39 #define VPD_CAP_ID_SHIFT 0
40 #define VPD_CAP_NEXT_PTR_MASK 0xFF
42 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
44 #define VPD_CAP_VPD_FLAG 0x80000000
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g-ice.dts18 reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
28 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
128 <&pca9536 0 GPIO_ACTIVE_HIGH>;
129 linux,axis = <0>; /* ABS_X */
136 pinctrl-0 = <&user_leds>;
223 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
224 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
230 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
231 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
232 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
[all …]
H A Dkeystone-k2g-evm.dts17 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
27 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
72 #clock-cells = <0>;
76 sound0: sound@0 {
88 simple-audio-card,dai-link@0 {
94 clocks = <&k2g_clks 0x6 1>;
110 clocks = <&k2g_clks 0x6 1>;
125 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
126 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
132 K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
[all …]
/linux/arch/mips/bcm47xx/
H A Dboard.c41 { {0}, NULL},
68 { {0}, NULL},
76 { {0}, NULL},
91 { {0}, NULL},
101 { {0}, NULL},
116 { {0}, NULL},
122 /* like WRT160N v3.0 */
124 /* like WRT310N v2.0 */
127 /* like WRT160N v3.0 */
134 /* like WRT610N v2.0 */
[all …]
/linux/drivers/clk/stm32/
H A Dstm32mp25_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_regs.h9 #define MT_ASIC_VERSION 0x0000
11 #define MT76XX_REV_E3 0x22
12 #define MT76XX_REV_E4 0x33
14 #define MT_CMB_CTRL 0x0020
18 #define MT_EFUSE_CTRL 0x0024
19 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
27 #define MT_EFUSE_DATA_BASE 0x0028
30 #define MT_COEXCFG0 0x0040
31 #define MT_COEXCFG0_COEX_EN BIT(0)
33 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Dpci.h10 #define MDIO_PG0_G1 0
14 #define RAC_CTRL_PPR 0x00
15 #define RAC_ANA03 0x03
17 #define RAC_ANA09 0x09
19 #define RAC_ANA0A 0x0A
21 #define RAC_ANA0B 0x0B
23 #define RAC_ANA0C 0x0C
25 #define RAC_ANA0D 0x0D
28 #define RAC_ANA10 0x10
30 #define ADDR_SEL_VAL 0x3C
[all …]
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
22 pixel_order 0x0006 8
23 - e GRBG 0
27 MIPI_CCS_version 0x0007 8
28 - e v1_0 0x10
29 - e v1_1 0x11
31 - f minor 0 3
32 data_pedestal 0x0008 16
[all …]
/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h19 #define SMIAPP_REG_U16_MODEL_ID CCI_REG16(0x0000)
20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
25 #define SMIAPP_REG_U16_DATA_PEDESTAL CCI_REG16(0x0008)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
[all …]
/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c29 #define S5P_APLL_LOCK S5P_CLKREG(0x00)
30 #define S5P_APLL_CON S5P_CLKREG(0x100)
31 #define S5P_CLK_SRC0 S5P_CLKREG(0x200)
32 #define S5P_CLK_SRC2 S5P_CLKREG(0x208)
33 #define S5P_CLK_DIV0 S5P_CLKREG(0x300)
34 #define S5P_CLK_DIV2 S5P_CLKREG(0x308)
35 #define S5P_CLK_DIV6 S5P_CLKREG(0x318)
36 #define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000)
37 #define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004)
38 #define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]
/linux/drivers/net/ethernet/atheros/alx/
H A Dreg.h38 #define ALX_DEV_ID_AR8161 0x1091
39 #define ALX_DEV_ID_E2200 0xe091
40 #define ALX_DEV_ID_E2400 0xe0a1
41 #define ALX_DEV_ID_E2500 0xe0b1
42 #define ALX_DEV_ID_AR8162 0x1090
43 #define ALX_DEV_ID_AR8171 0x10A1
44 #define ALX_DEV_ID_AR8172 0x10A0
47 * bit(0): with xD support
52 #define ALX_REV_A0 0
57 #define ALX_DEV_CTRL 0x0060
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.h10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
[all …]
/linux/drivers/video/fbdev/
H A Dgxt4500.c19 #define PCI_DEVICE_ID_IBM_GXT4500P 0x21c
20 #define PCI_DEVICE_ID_IBM_GXT6500P 0x21b
21 #define PCI_DEVICE_ID_IBM_GXT4000P 0x16e
22 #define PCI_DEVICE_ID_IBM_GXT6000P 0x170
27 #define CFG_ENDIAN0 0x40
30 #define STATUS 0x1000
31 #define CTRL_REG0 0x1004
32 #define CR0_HALT_DMA 0x4
33 #define CR0_RASTER_RESET 0x8
34 #define CR0_GEOM_RESET 0x10
[all …]

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