37 	PDC_UDMA_100		= 0,
43 	PDC_SYS_CTL		= 0x1100,
44 	PDC_ATA_CTL		= 0x1104,
45 	PDC_GLOBAL_CTL		= 0x1108,
46 	PDC_CTCR0		= 0x110C,
47 	PDC_CTCR1		= 0x1110,
48 	PDC_BYTE_COUNT		= 0x1120,
49 	PDC_PLL_CTL		= 0x1202,
75 	{ 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
76 	{ 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
77 	{ 0x23, 0x26, 0x64 }, /* PIO mode 2 */
78 	{ 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
79 	{ 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
85 	{ 0xdf, 0x5f }, /* MDMA mode 0 */
86 	{ 0x6b, 0x27 }, /* MDMA mode 1 */
87 	{ 0x69, 0x25 }, /* MDMA mode 2 */
93 	{ 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
94 	{ 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
95 	{ 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
96 	{ 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
97 	{ 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
98 	{ 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
99 	{ 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
176 	return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;  in port_mmio()
187 	u8 adj = (adev->devno) ? 0x08 : 0x00;  in dev_mmio()
224 	return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;  in pdc2027x_port_enabled()
259 	if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)  in pdc2027x_mode_filter()
301 	ctcr0 &= 0xffff0000;  in pdc2027x_set_piomode()
307 	ctcr1 &= 0x00ffffff;  in pdc2027x_set_piomode()
332 		unsigned int udma_mode = dma_mode & 0x07;  in pdc2027x_set_dmamode()
347 		ctcr1 &= 0xff000000;  in pdc2027x_set_dmamode()
358 		unsigned int mdma_mode = dma_mode & 0x07;  in pdc2027x_set_dmamode()
363 		ctcr0 &= 0x0000ffff;  in pdc2027x_set_dmamode()
391 	if (rc < 0)  in pdc2027x_set_mode()
410 	return 0;  in pdc2027x_set_mode()
420  *	RETURNS: 0 when ATAPI DMA can be used
435 	switch (scsicmd[0]) {  in pdc2027x_check_atapi_dma()
442 	case 0xad: /* READ_DVD_STRUCTURE */  in pdc2027x_check_atapi_dma()
443 	case 0xbe: /* READ_CD */  in pdc2027x_check_atapi_dma()
445 		rc = 0;  in pdc2027x_check_atapi_dma()
467 	bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;  in pdc_read_counter()
468 	bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;  in pdc_read_counter()
471 	bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;  in pdc_read_counter()
472 	bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;  in pdc_read_counter()
530 		/* Using NO = 0x01, R = 0x0D */  in pdc_adjust_pll()
531 		R = 0x0d;  in pdc_adjust_pll()
533 		/* Using NO = 0x01, R = 0x08 */  in pdc_adjust_pll()
534 		R = 0x08;  in pdc_adjust_pll()
536 		/* Using NO = 0x01, R = 0x06 */  in pdc_adjust_pll()
537 		R = 0x06;  in pdc_adjust_pll()
539 		R = 0x00;  in pdc_adjust_pll()
548 	if (unlikely(F < 0 || F > 127)) {  in pdc_adjust_pll()
594 	iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);  in pdc_detect_pll_input_clock()
611 	iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);  in pdc_detect_pll_input_clock()
617 	pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *  in pdc_detect_pll_input_clock()
659 	port->error_addr	= base + 0x05;  in pdc_ata_setup_port()
660 	port->nsect_addr	= base + 0x0a;  in pdc_ata_setup_port()
661 	port->lbal_addr		= base + 0x0f;  in pdc_ata_setup_port()
662 	port->lbam_addr		= base + 0x10;  in pdc_ata_setup_port()
663 	port->lbah_addr		= base + 0x15;  in pdc_ata_setup_port()
664 	port->device_addr	= base + 0x1a;  in pdc_ata_setup_port()
666 	port->status_addr	= base + 0x1f;  in pdc_ata_setup_port()
668 	port->ctl_addr		= base + 0x81a;  in pdc_ata_setup_port()
684 	static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };  in pdc2027x_init_one()
685 	static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };  in pdc2027x_init_one()
716 	for (i = 0; i < 2; i++) {  in pdc2027x_init_one()
756 	return 0;  in pdc2027x_reinit_one()