52 	return 0xA0 + (ap->port_no << 4) + r;  in sil680_selreg()
68 	return 0xA0 + (ap->port_no << 4) + r + (adev->devno << 1);  in sil680_seldev()
83 	int addr = sil680_selreg(ap, 0);  in sil680_cable_detect()
106 		0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1  in sil680_set_piomode()
109 		0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1  in sil680_set_piomode()
112 	int tfaddr = sil680_selreg(ap, 0x02);  in sil680_set_piomode()
113 	int addr = sil680_seldev(ap, adev, 0x04);  in sil680_set_piomode()
114 	int addr_mask = 0x80 + 4 * ap->port_no;  in sil680_set_piomode()
133 	reg &= ~0x0200;			/* Clear IORDY */  in sil680_set_piomode()
137 		reg |= 0x0200;		/* Enable IORDY */  in sil680_set_piomode()
158 		{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF },	/* 100MHz */  in sil680_set_dmamode()
159 		{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 },	/* 133Mhz */  in sil680_set_dmamode()
161 	static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };  in sil680_set_dmamode()
164 	int ma = sil680_seldev(ap, adev, 0x08);  in sil680_set_dmamode()
165 	int ua = sil680_seldev(ap, adev, 0x0C);  in sil680_set_dmamode()
166 	int addr_mask = 0x80 + 4 * ap->port_no;  in sil680_set_dmamode()
171 	pci_read_config_byte(pdev, 0x8A, &scsc);  in sil680_set_dmamode()
177 	ultra &= ~0x3F;  in sil680_set_dmamode()
178 	mode &= ~(0x03 << port_shift);  in sil680_set_dmamode()
181 	scsc = (scsc & 0x30) ? 1 : 0;  in sil680_set_dmamode()
184 		multi = 0x10C1;  in sil680_set_dmamode()
186 		mode |= (0x03 << port_shift);  in sil680_set_dmamode()
189 		mode |= (0x02 << port_shift);  in sil680_set_dmamode()
223 	return val & 0x08;  in sil680_sff_irq_check()
252 	u8 tmpbyte	= 0;  in sil680_init_chip()
258 	pci_write_config_byte(pdev, 0x80, 0x00);  in sil680_init_chip()
259 	pci_write_config_byte(pdev, 0x84, 0x00);  in sil680_init_chip()
261 	pci_read_config_byte(pdev, 0x8A, &tmpbyte);  in sil680_init_chip()
264 		tmpbyte & 1, tmpbyte & 0x30);  in sil680_init_chip()
266 	*try_mmio = 0;  in sil680_init_chip()
272 	switch (tmpbyte & 0x30) {  in sil680_init_chip()
273 	case 0x00:  in sil680_init_chip()
275 		pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);  in sil680_init_chip()
277 	case 0x30:  in sil680_init_chip()
280 		pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);  in sil680_init_chip()
282 	case 0x10:  in sil680_init_chip()
285 	case 0x20:  in sil680_init_chip()
290 	pci_read_config_byte(pdev,   0x8A, &tmpbyte);  in sil680_init_chip()
292 		tmpbyte & 1, tmpbyte & 0x30);  in sil680_init_chip()
294 	pci_write_config_byte(pdev,  0xA1, 0x72);  in sil680_init_chip()
295 	pci_write_config_word(pdev,  0xA2, 0x328A);  in sil680_init_chip()
296 	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);  in sil680_init_chip()
297 	pci_write_config_dword(pdev, 0xA8, 0x43924392);  in sil680_init_chip()
298 	pci_write_config_dword(pdev, 0xAC, 0x40094009);  in sil680_init_chip()
299 	pci_write_config_byte(pdev,  0xB1, 0x72);  in sil680_init_chip()
300 	pci_write_config_word(pdev,  0xB2, 0x328A);  in sil680_init_chip()
301 	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);  in sil680_init_chip()
302 	pci_write_config_dword(pdev, 0xB8, 0x43924392);  in sil680_init_chip()
303 	pci_write_config_dword(pdev, 0xBC, 0x40094009);  in sil680_init_chip()
305 	switch (tmpbyte & 0x30) {  in sil680_init_chip()
306 	case 0x00:  in sil680_init_chip()
309 	case 0x10:  in sil680_init_chip()
312 	case 0x20:  in sil680_init_chip()
316 	case 0x30:  in sil680_init_chip()
319 	return tmpbyte & 0x30;  in sil680_init_chip()
350 		case 0:  in sil680_init_one()
351 			ppi[0] = &info_slow;  in sil680_init_one()
353 		case 0x30:  in sil680_init_one()
381 	host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;  in sil680_init_one()
382 	host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;  in sil680_init_one()
383 	host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;  in sil680_init_one()
384 	host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;  in sil680_init_one()
385 	ata_sff_std_ports(&host->ports[0]->ioaddr);  in sil680_init_one()
386 	host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;  in sil680_init_one()
387 	host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;  in sil680_init_one()
388 	host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;  in sil680_init_one()
389 	host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;  in sil680_init_one()
397 	return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);  in sil680_init_one()
411 	return 0;  in sil680_reinit_one()