Lines Matching +full:0 +full:x1104
15 #define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */
16 #define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */
17 #define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */
18 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
19 #define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
23 #define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */
24 #define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */
25 #define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */
26 #define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
37 #define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */
43 #define H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */
61 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
62 #define H2_IAR_PARAM 0x000C /* Parameter Select */
63 #define H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */
87 #define H2I_RELAY_C 0x9100
88 #define H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */
92 #define H2I_DMA_PORT_EN 0x9104
93 #define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */
94 #define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */
95 #define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */
96 #define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */
97 #define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */
99 #define H2I_DMA_END 0x9108 /* global dma endian select */
100 #define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */
101 #define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */
102 #define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */
103 #define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */
104 #define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */
105 /* 0=b_end 1=l_end */
107 #define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
109 #define H2I_SYNTH_C 0x1104 /* Synth DMA control */
111 #define H2I_AESRX_C 0x1204 /* AES RX dma control */
113 #define H2I_C_TS_EN 0x20 /* Timestamp enable */
114 #define H2I_C_TS_FRMT 0x40 /* Timestamp format */
115 #define H2I_C_NAUDIO 0x80 /* Sign extend */
119 #define H2I_AESTX_C 0x1304 /* AES TX DMA control */
121 #define H2I_AESTX_C_CLKID_M 0x18
123 #define H2I_AESTX_C_DATAT_M 0x300
127 #define H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */
128 #define H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */
129 #define H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */
130 #define H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */
134 #define H2I_C1_DMA_SHIFT 0 /* DMA channel */
135 #define H2I_C1_DMA_M 0x7
137 #define H2I_C1_CLKID_M 0x18
139 #define H2I_C1_DATAT_M 0x300
143 #define H2I_C2_R_GAIN_SHIFT 0 /* right a/d input gain */
144 #define H2I_C2_R_GAIN_M 0xf
146 #define H2I_C2_L_GAIN_M 0xf0
147 #define H2I_C2_R_SEL 0x100 /* right input select */
148 #define H2I_C2_L_SEL 0x200 /* left input select */
149 #define H2I_C2_MUTE 0x400 /* mute */
150 #define H2I_C2_DO1 0x00010000 /* digital output port bit 0 */
151 #define H2I_C2_DO2 0x00020000 /* digital output port bit 1 */
153 #define H2I_C2_R_ATT_M 0x007c0000 /* attenuation */
155 #define H2I_C2_L_ATT_M 0x0f800000 /* attenuation */
157 #define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */
161 #define H2I_BRES1_C1 0x2104
162 #define H2I_BRES2_C1 0x2204
163 #define H2I_BRES3_C1 0x2304
165 #define H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
166 #define H2I_BRES_C1_M 0x03
170 #define H2I_BRES1_C2 0x2108
171 #define H2I_BRES2_C2 0x2208
172 #define H2I_BRES3_C2 0x2308
174 #define H2I_BRES_C2_INC_SHIFT 0 /* increment value */
175 #define H2I_BRES_C2_INC_M 0xffff
177 #define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
181 #define H2I_UTIME 0x3104
182 #define H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */
183 #define H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */
184 #define H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */
185 #define H2I_UTIME_2_LD 0xffff /* seconds, LSB's */
186 #define H2I_UTIME_3_LD 0xffff /* seconds, MSB's */
190 u32 isr; /* 0x10 Status Register */
192 u32 rev; /* 0x20 Revision Register */
194 u32 iar; /* 0x30 Indirect Address Register */
196 u32 idr0; /* 0x40 Indirect Data Register 0 */
198 u32 idr1; /* 0x50 Indirect Data Register 1 */
200 u32 idr2; /* 0x60 Indirect Data Register 2 */
202 u32 idr3; /* 0x70 Indirect Data Register 3 */