1049633fcSKrzysztof Kozlowski /* SPDX-License-Identifier: GPL-2.0 */ 29740bdd9SKukjin Kim /* 39740bdd9SKukjin Kim * Copyright (c) 2010 Samsung Electronics Co., Ltd. 49740bdd9SKukjin Kim * http://www.samsung.com/ 59740bdd9SKukjin Kim * 69740bdd9SKukjin Kim * S5PV210 - Clock register definitions 79740bdd9SKukjin Kim */ 89740bdd9SKukjin Kim 99740bdd9SKukjin Kim #ifndef __ASM_ARCH_REGS_CLOCK_H 109740bdd9SKukjin Kim #define __ASM_ARCH_REGS_CLOCK_H __FILE__ 119740bdd9SKukjin Kim 12*423c62bfSArnd Bergmann #define S3C_ADDR_BASE 0xF6000000 13*423c62bfSArnd Bergmann #define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) 14*423c62bfSArnd Bergmann #define S3C_VA_SYS S3C_ADDR(0x00100000) 159740bdd9SKukjin Kim 169740bdd9SKukjin Kim #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 179740bdd9SKukjin Kim 189740bdd9SKukjin Kim #define S5P_APLL_LOCK S5P_CLKREG(0x00) 199740bdd9SKukjin Kim #define S5P_MPLL_LOCK S5P_CLKREG(0x08) 209740bdd9SKukjin Kim #define S5P_EPLL_LOCK S5P_CLKREG(0x10) 219740bdd9SKukjin Kim #define S5P_VPLL_LOCK S5P_CLKREG(0x20) 229740bdd9SKukjin Kim 239740bdd9SKukjin Kim #define S5P_APLL_CON S5P_CLKREG(0x100) 249740bdd9SKukjin Kim #define S5P_MPLL_CON S5P_CLKREG(0x108) 259740bdd9SKukjin Kim #define S5P_EPLL_CON S5P_CLKREG(0x110) 269740bdd9SKukjin Kim #define S5P_EPLL_CON1 S5P_CLKREG(0x114) 279740bdd9SKukjin Kim #define S5P_VPLL_CON S5P_CLKREG(0x120) 289740bdd9SKukjin Kim 299740bdd9SKukjin Kim #define S5P_CLK_SRC0 S5P_CLKREG(0x200) 309740bdd9SKukjin Kim #define S5P_CLK_SRC1 S5P_CLKREG(0x204) 319740bdd9SKukjin Kim #define S5P_CLK_SRC2 S5P_CLKREG(0x208) 329740bdd9SKukjin Kim #define S5P_CLK_SRC3 S5P_CLKREG(0x20C) 339740bdd9SKukjin Kim #define S5P_CLK_SRC4 S5P_CLKREG(0x210) 349740bdd9SKukjin Kim #define S5P_CLK_SRC5 S5P_CLKREG(0x214) 359740bdd9SKukjin Kim #define S5P_CLK_SRC6 S5P_CLKREG(0x218) 369740bdd9SKukjin Kim 379740bdd9SKukjin Kim #define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280) 389740bdd9SKukjin Kim #define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284) 399740bdd9SKukjin Kim 409740bdd9SKukjin Kim #define S5P_CLK_DIV0 S5P_CLKREG(0x300) 419740bdd9SKukjin Kim #define S5P_CLK_DIV1 S5P_CLKREG(0x304) 429740bdd9SKukjin Kim #define S5P_CLK_DIV2 S5P_CLKREG(0x308) 439740bdd9SKukjin Kim #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) 449740bdd9SKukjin Kim #define S5P_CLK_DIV4 S5P_CLKREG(0x310) 459740bdd9SKukjin Kim #define S5P_CLK_DIV5 S5P_CLKREG(0x314) 469740bdd9SKukjin Kim #define S5P_CLK_DIV6 S5P_CLKREG(0x318) 479740bdd9SKukjin Kim #define S5P_CLK_DIV7 S5P_CLKREG(0x31C) 489740bdd9SKukjin Kim 499740bdd9SKukjin Kim #define S5P_CLKGATE_MAIN0 S5P_CLKREG(0x400) 509740bdd9SKukjin Kim #define S5P_CLKGATE_MAIN1 S5P_CLKREG(0x404) 519740bdd9SKukjin Kim #define S5P_CLKGATE_MAIN2 S5P_CLKREG(0x408) 529740bdd9SKukjin Kim 539740bdd9SKukjin Kim #define S5P_CLKGATE_PERI0 S5P_CLKREG(0x420) 549740bdd9SKukjin Kim #define S5P_CLKGATE_PERI1 S5P_CLKREG(0x424) 559740bdd9SKukjin Kim 569740bdd9SKukjin Kim #define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x440) 579740bdd9SKukjin Kim #define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x444) 589740bdd9SKukjin Kim #define S5P_CLKGATE_IP0 S5P_CLKREG(0x460) 599740bdd9SKukjin Kim #define S5P_CLKGATE_IP1 S5P_CLKREG(0x464) 609740bdd9SKukjin Kim #define S5P_CLKGATE_IP2 S5P_CLKREG(0x468) 619740bdd9SKukjin Kim #define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) 629740bdd9SKukjin Kim #define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) 639740bdd9SKukjin Kim 649740bdd9SKukjin Kim #define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) 659740bdd9SKukjin Kim #define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) 669740bdd9SKukjin Kim #define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) 679740bdd9SKukjin Kim #define S5P_CLK_OUT S5P_CLKREG(0x500) 689740bdd9SKukjin Kim 699740bdd9SKukjin Kim /* DIV/MUX STATUS */ 709740bdd9SKukjin Kim #define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000) 719740bdd9SKukjin Kim #define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004) 729740bdd9SKukjin Kim #define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100) 739740bdd9SKukjin Kim #define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104) 749740bdd9SKukjin Kim 759740bdd9SKukjin Kim /* CLKSRC0 */ 769740bdd9SKukjin Kim #define S5P_CLKSRC0_MUX200_SHIFT (16) 779740bdd9SKukjin Kim #define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) 789740bdd9SKukjin Kim #define S5P_CLKSRC0_MUX166_MASK (0x1<<20) 799740bdd9SKukjin Kim #define S5P_CLKSRC0_MUX133_MASK (0x1<<24) 809740bdd9SKukjin Kim 819740bdd9SKukjin Kim /* CLKSRC2 */ 829740bdd9SKukjin Kim #define S5P_CLKSRC2_G3D_SHIFT (0) 839740bdd9SKukjin Kim #define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT) 849740bdd9SKukjin Kim #define S5P_CLKSRC2_MFC_SHIFT (4) 859740bdd9SKukjin Kim #define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT) 869740bdd9SKukjin Kim 879740bdd9SKukjin Kim /* CLKSRC6*/ 889740bdd9SKukjin Kim #define S5P_CLKSRC6_ONEDRAM_SHIFT (24) 899740bdd9SKukjin Kim #define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT) 909740bdd9SKukjin Kim 919740bdd9SKukjin Kim /* CLKDIV0 */ 929740bdd9SKukjin Kim #define S5P_CLKDIV0_APLL_SHIFT (0) 939740bdd9SKukjin Kim #define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) 949740bdd9SKukjin Kim #define S5P_CLKDIV0_A2M_SHIFT (4) 959740bdd9SKukjin Kim #define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) 969740bdd9SKukjin Kim #define S5P_CLKDIV0_HCLK200_SHIFT (8) 979740bdd9SKukjin Kim #define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT) 989740bdd9SKukjin Kim #define S5P_CLKDIV0_PCLK100_SHIFT (12) 999740bdd9SKukjin Kim #define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT) 1009740bdd9SKukjin Kim #define S5P_CLKDIV0_HCLK166_SHIFT (16) 1019740bdd9SKukjin Kim #define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT) 1029740bdd9SKukjin Kim #define S5P_CLKDIV0_PCLK83_SHIFT (20) 1039740bdd9SKukjin Kim #define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT) 1049740bdd9SKukjin Kim #define S5P_CLKDIV0_HCLK133_SHIFT (24) 1059740bdd9SKukjin Kim #define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT) 1069740bdd9SKukjin Kim #define S5P_CLKDIV0_PCLK66_SHIFT (28) 1079740bdd9SKukjin Kim #define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) 1089740bdd9SKukjin Kim 1099740bdd9SKukjin Kim /* CLKDIV2 */ 1109740bdd9SKukjin Kim #define S5P_CLKDIV2_G3D_SHIFT (0) 1119740bdd9SKukjin Kim #define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT) 1129740bdd9SKukjin Kim #define S5P_CLKDIV2_MFC_SHIFT (4) 1139740bdd9SKukjin Kim #define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT) 1149740bdd9SKukjin Kim 1159740bdd9SKukjin Kim /* CLKDIV6 */ 1169740bdd9SKukjin Kim #define S5P_CLKDIV6_ONEDRAM_SHIFT (28) 1179740bdd9SKukjin Kim #define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT) 1189740bdd9SKukjin Kim 1199740bdd9SKukjin Kim #define S5P_SWRESET S5P_CLKREG(0x2000) 1209740bdd9SKukjin Kim 1219740bdd9SKukjin Kim #define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) 1229740bdd9SKukjin Kim 1239740bdd9SKukjin Kim /* Registers related to power management */ 1249740bdd9SKukjin Kim #define S5P_PWR_CFG S5P_CLKREG(0xC000) 1259740bdd9SKukjin Kim #define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) 1269740bdd9SKukjin Kim #define S5P_WAKEUP_MASK S5P_CLKREG(0xC008) 1279740bdd9SKukjin Kim #define S5P_PWR_MODE S5P_CLKREG(0xC00C) 1289740bdd9SKukjin Kim #define S5P_NORMAL_CFG S5P_CLKREG(0xC010) 1299740bdd9SKukjin Kim #define S5P_IDLE_CFG S5P_CLKREG(0xC020) 1309740bdd9SKukjin Kim #define S5P_STOP_CFG S5P_CLKREG(0xC030) 1319740bdd9SKukjin Kim #define S5P_STOP_MEM_CFG S5P_CLKREG(0xC034) 1329740bdd9SKukjin Kim #define S5P_SLEEP_CFG S5P_CLKREG(0xC040) 1339740bdd9SKukjin Kim 1349740bdd9SKukjin Kim #define S5P_OSC_FREQ S5P_CLKREG(0xC100) 1359740bdd9SKukjin Kim #define S5P_OSC_STABLE S5P_CLKREG(0xC104) 1369740bdd9SKukjin Kim #define S5P_PWR_STABLE S5P_CLKREG(0xC108) 1379740bdd9SKukjin Kim #define S5P_MTC_STABLE S5P_CLKREG(0xC110) 1389740bdd9SKukjin Kim #define S5P_CLAMP_STABLE S5P_CLKREG(0xC114) 1399740bdd9SKukjin Kim 1409740bdd9SKukjin Kim #define S5P_WAKEUP_STAT S5P_CLKREG(0xC200) 1419740bdd9SKukjin Kim #define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204) 1429740bdd9SKukjin Kim 1439740bdd9SKukjin Kim #define S5P_OTHERS S5P_CLKREG(0xE000) 1449740bdd9SKukjin Kim #define S5P_OM_STAT S5P_CLKREG(0xE100) 1459740bdd9SKukjin Kim #define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804) 1469740bdd9SKukjin Kim #define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) 1479740bdd9SKukjin Kim #define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810) 1489740bdd9SKukjin Kim 1499740bdd9SKukjin Kim #define S5P_INFORM0 S5P_CLKREG(0xF000) 1509740bdd9SKukjin Kim #define S5P_INFORM1 S5P_CLKREG(0xF004) 1519740bdd9SKukjin Kim #define S5P_INFORM2 S5P_CLKREG(0xF008) 1529740bdd9SKukjin Kim #define S5P_INFORM3 S5P_CLKREG(0xF00C) 1539740bdd9SKukjin Kim #define S5P_INFORM4 S5P_CLKREG(0xF010) 1549740bdd9SKukjin Kim #define S5P_INFORM5 S5P_CLKREG(0xF014) 1559740bdd9SKukjin Kim #define S5P_INFORM6 S5P_CLKREG(0xF018) 1569740bdd9SKukjin Kim #define S5P_INFORM7 S5P_CLKREG(0xF01C) 1579740bdd9SKukjin Kim 1589740bdd9SKukjin Kim #define S5P_RST_STAT S5P_CLKREG(0xA000) 1599740bdd9SKukjin Kim #define S5P_OSC_CON S5P_CLKREG(0x8000) 1609740bdd9SKukjin Kim #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) 1619740bdd9SKukjin Kim #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) 1629740bdd9SKukjin Kim #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) 1639740bdd9SKukjin Kim 1649740bdd9SKukjin Kim #define S5P_IDLE_CFG_TL_MASK (3 << 30) 1659740bdd9SKukjin Kim #define S5P_IDLE_CFG_TM_MASK (3 << 28) 1669740bdd9SKukjin Kim #define S5P_IDLE_CFG_TL_ON (2 << 30) 1679740bdd9SKukjin Kim #define S5P_IDLE_CFG_TM_ON (2 << 28) 1689740bdd9SKukjin Kim #define S5P_IDLE_CFG_DIDLE (1 << 0) 1699740bdd9SKukjin Kim 1709740bdd9SKukjin Kim #define S5P_CFG_WFI_CLEAN (~(3 << 8)) 1719740bdd9SKukjin Kim #define S5P_CFG_WFI_IDLE (1 << 8) 1729740bdd9SKukjin Kim #define S5P_CFG_WFI_STOP (2 << 8) 1739740bdd9SKukjin Kim #define S5P_CFG_WFI_SLEEP (3 << 8) 1749740bdd9SKukjin Kim 1759740bdd9SKukjin Kim #define S5P_OTHER_SYS_INT 24 1769740bdd9SKukjin Kim #define S5P_OTHER_STA_TYPE 23 1779740bdd9SKukjin Kim #define S5P_OTHER_SYSC_INTOFF (1 << 0) 1789740bdd9SKukjin Kim #define STA_TYPE_EXPON 0 1799740bdd9SKukjin Kim #define STA_TYPE_SFR 1 1809740bdd9SKukjin Kim 1819740bdd9SKukjin Kim #define S5P_PWR_STA_EXP_SCALE 0 1829740bdd9SKukjin Kim #define S5P_PWR_STA_CNT 4 1839740bdd9SKukjin Kim 1849740bdd9SKukjin Kim #define S5P_PWR_STABLE_COUNT 85500 1859740bdd9SKukjin Kim 1869740bdd9SKukjin Kim #define S5P_SLEEP_CFG_OSC_EN (1 << 0) 1879740bdd9SKukjin Kim #define S5P_SLEEP_CFG_USBOSC_EN (1 << 1) 1889740bdd9SKukjin Kim 1899740bdd9SKukjin Kim /* OTHERS Resgister */ 1909740bdd9SKukjin Kim #define S5P_OTHERS_USB_SIG_MASK (1 << 16) 1919740bdd9SKukjin Kim 1929740bdd9SKukjin Kim /* S5P_DAC_CONTROL */ 1939740bdd9SKukjin Kim #define S5P_DAC_ENABLE (1) 1949740bdd9SKukjin Kim #define S5P_DAC_DISABLE (0) 1959740bdd9SKukjin Kim 1969740bdd9SKukjin Kim #endif /* __ASM_ARCH_REGS_CLOCK_H */ 197