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/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-espi-0.dtsi2 * QorIQ eSPI device tree stub [ controller @ offset 0x110000 ]
37 #size-cells = <0>;
39 reg = <0x110000 0x1000>;
40 interrupts = <53 0x2 0 0>;
H A Db4860si-post.dtsi37 /* controller at 0x200000 */
64 dcsr-epu@0 {
79 reg = <0x13000 0x1000>;
96 reg = <0x108000 0x1000 0x109000 0x1000>;
101 reg = <0x110000 0x1000 0x111000 0x1000>;
106 reg = <0x118000 0x1000 0x119000 0x1000>;
113 reg = <0x38000 0x4000>, <0x100e000 0x1000>;
114 interrupts = <133 2 0 0>;
118 reg = <0x3c000 0x4000>, <0x100f000 0x1000>;
119 interrupts = <135 2 0 0>;
[all …]
/linux/arch/mips/boot/dts/loongson/
H A Dloongson1c.dtsi12 reg = <0x1fe78030 0x8>;
21 reg = <0x420 0x8>;
26 reg = <0x10a0 0x18>;
35 reg = <0x10c8 0x4>;
43 reg = <0x10cc 0x4>;
51 reg = <0x1160 0x4>;
62 reg = <0x110000 0x10000>;
75 reg = <0x120000 0x100>;
77 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
83 reg = <0x128000 0x100>;
[all …]
H A Dloongson1b.dtsi57 reg = <0x1fe78030 0x8>;
66 reg = <0x420 0x8>;
71 reg = <0x1160 0x4>;
82 reg = <0x100000 0x100>;
84 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
90 reg = <0x108000 0x100>;
98 reg = <0x110000 0x10000>;
111 reg = <0x120000 0x10000>;
126 reg = <0x1c030 0x10>;
134 reg = <0x1c060 0xc>;
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-platform-regs.h11 * locates in one single space starts from 0 but in different sctions with
12 * different addresses, the subsystem offsets are defined to 0 as the
13 * register definition will have the address offset to 0.
15 #define IPU6_UNIFIED_OFFSET 0
17 #define IPU6_ISYS_IOMMU0_OFFSET 0x2e0000
18 #define IPU6_ISYS_IOMMU1_OFFSET 0x2e0500
19 #define IPU6_ISYS_IOMMUI_OFFSET 0x2e0a00
21 #define IPU6_PSYS_IOMMU0_OFFSET 0x1b0000
22 #define IPU6_PSYS_IOMMU1_OFFSET 0x1b0700
23 #define IPU6_PSYS_IOMMU1R_OFFSET 0x1b0e00
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dgt215.c45 if (ret < 0) in gt215_devinit_pll_set()
51 nvkm_wr32(device, info.reg + 0, 0x50000610); in gt215_devinit_pll_set()
52 nvkm_mask(device, info.reg + 4, 0x003fffff, in gt215_devinit_pll_set()
69 u32 r001540 = nvkm_rd32(device, 0x001540); in gt215_devinit_disable()
70 u32 r00154c = nvkm_rd32(device, 0x00154c); in gt215_devinit_disable()
72 if (!(r001540 & 0x40000000)) { in gt215_devinit_disable()
73 nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0); in gt215_devinit_disable()
74 nvkm_subdev_disable(device, NVKM_ENGINE_MSPPP, 0); in gt215_devinit_disable()
77 if (!(r00154c & 0x00000004)) in gt215_devinit_disable()
78 nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0); in gt215_devinit_disable()
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-3720-gl-mv1000.dts23 memory@0 {
25 reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
35 gpios-states = <0>;
36 states = <1800000 0x1
37 3300000 0x0>;
81 flash@0 {
82 reg = <0>;
91 partition@0 {
93 reg = <0 0xf0000>;
98 reg = <0xf0000 0x8000>;
[all …]
/linux/sound/pci/emu10k1/
H A Dp16v.c8 * Output fixed at S32_LE, 2 channel to hw:0,0
44 * Removed #if 0 ... #endif
50 * setting HD Capture channel to 0 captures from CDROM digital input.
92 #define SET_CHANNEL 0 /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */
93 #define PCM_FRONT_CHANNEL 0
97 #define CONTROL_FRONT_CHANNEL 0
129 .fifo_size = 0,
149 .fifo_size = 0,
[all...]
/linux/fs/unicode/
H A Dmkutf8data.c50 int verbose = 0;
63 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
98 return 0; in age_valid()
100 return 0; in age_valid()
102 return 0; in age_valid()
119 * if offlen == 0 (non-branching node)
124 * if offlen != 0 (branching node)
133 #define BITNUM 0x07
134 #define NEXTBYTE 0x08
135 #define OFFLEN 0x30
[all …]
/linux/include/soc/fsl/qe/
H A Dimmap_qe.h26 u8 res0[0x04];
28 u8 res1[0x70];
44 u8 res0[0x4];
47 u8 res1[0x4];
49 u8 res2[0x20];
51 u8 res3[0x1C];
59 u8 res0[0xA];
61 u8 res1[0x2];
66 u8 res2[0x8];
70 u8 res3[0x2];
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/linux/drivers/staging/sm750fb/
H A Dsm750_accel.h5 #define HW_ROP2_COPY 0xc
6 #define HW_ROP2_XOR 0x6
8 /* notes: below address are the offset value from de_base_address (0x100000)*/
11 #define DE_BASE_ADDR_TYPE1 0x100000
13 #define DE_BASE_ADDR_TYPE2 0x8000
15 #define DE_BASE_ADDR_TYPE3 0
18 #define DE_PORT_ADDR_TYPE1 0x110000
20 #define DE_PORT_ADDR_TYPE2 0x100000
22 #define DE_PORT_ADDR_TYPE3 0x100000
24 #define DE_SOURCE 0x0
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
[all …]
H A Djuno-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
34 #clock-cells = <0>;
55 gpios = <&iofpga_gpio0 0 0x4>;
62 gpios = <&iofpga_gpio0 1 0x4>;
69 gpios = <&iofpga_gpio0 2 0x4>;
76 gpios = <&iofpga_gpio0 3 0x4>;
83 gpios = <&iofpga_gpio0 4 0x4>;
90 gpios = <&iofpga_gpio0 5 0x4>;
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dusb_mcu.c14 #define MCU_FW_URB_MAX_PAYLOAD 0x3900
17 #define MT76U_MCU_ILM_OFFSET 0x80000
18 #define MT76U_MCU_DLM_OFFSET 0x110000
19 #define MT76U_MCU_ROM_PATCH_OFFSET 0x90000
25 0x12, 0, NULL, 0); in mt76x2u_mcu_load_ivb()
32 0x6f, 0xfc, 0x08, 0x01, in mt76x2u_mcu_enable_patch()
33 0x20, 0x04, 0x00, 0x00, in mt76x2u_mcu_enable_patch()
34 0x00, 0x09, 0x00, in mt76x2u_mcu_enable_patch()
40 0x12, 0, usb->data, sizeof(data)); in mt76x2u_mcu_enable_patch()
47 0x6f, 0xfc, 0x05, 0x01, in mt76x2u_mcu_reset_wmt()
[all …]
/linux/arch/m68k/include/asm/
H A Dm523xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
H A Dm528xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 0 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
H A Dm527xsim.h24 #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */
25 #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */
27 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
28 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
29 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
30 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
31 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
32 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
33 #define MCFINTC_IRLR 0x18 /* */
34 #define MCFINTC_IACKL 0x19 /* */
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
41 d-cache-size = <0x8000>; // L1, 32 KB
42 i-cache-size = <0x8000>; // L1, 32 KB
48 cache-size = <0x40000>; // L2, 256 KB
98 hysteresis = <0>;
104 hysteresis = <0>;
110 hysteresis = <0>;
133 #clock-cells = <0>;
[all …]
/linux/sound/hda/codecs/
H A Dca0132_regs.h12 #define DSP_CHIP_OFFSET 0x100000
13 #define DSP_DBGCNTL_MODULE_OFFSET 0xE30
17 #define DSP_DBGCNTL_EXEC_LOBIT 0x0
18 #define DSP_DBGCNTL_EXEC_HIBIT 0x3
19 #define DSP_DBGCNTL_EXEC_MASK 0xF
21 #define DSP_DBGCNTL_SS_LOBIT 0x4
22 #define DSP_DBGCNTL_SS_HIBIT 0x7
23 #define DSP_DBGCNTL_SS_MASK 0xF0
25 #define DSP_DBGCNTL_STATE_LOBIT 0xA
26 #define DSP_DBGCNTL_STATE_HIBIT 0xD
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
/linux/drivers/tty/vt/
H A Dgen_ucs_width_table.py21 0x200B, # ZERO WIDTH SPACE
22 0x200C, # ZERO WIDTH NON-JOINER
23 0x200D, # ZERO WIDTH JOINER
24 0x2060, # WORD JOINER
25 0xFEFF # ZERO WIDTH NO-BREAK SPACE (BOM)
34 (0x1F3FB, 0x1F3FF), # Emoji modifiers (skin tones)
37 (0xFE00, 0xFE0F), # Variation Selectors 1-16
42 (0x2640, 0x2640), # Female sign
43 (0x2642, 0x2642), # Male sign
44 (0x26A7, 0x26A7), # Transgender symbol
[all …]
/linux/include/linux/
H A Dsm501-regs.h11 #define SM501_SYS_CONFIG (0x000000)
14 #define SM501_SYSTEM_CONTROL (0x000000)
16 #define SM501_SYSCTRL_PANEL_TRISTATE (1<<0)
21 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
35 #define SM501_MISC_CONTROL (0x000004)
37 #define SM501_MISC_BUS_SH (0x0)
38 #define SM501_MISC_BUS_PCI (0x1)
39 #define SM501_MISC_BUS_XSCALE (0x2)
40 #define SM501_MISC_BUS_NEC (0x6)
41 #define SM501_MISC_BUS_MASK (0x7)
[all …]
/linux/sound/pci/ctxfi/
H A Dct20k1reg.h10 #define DSPXRAM_START 0x000000
11 #define DSPXRAM_END 0x013FFC
12 #define DSPAXRAM_START 0x020000
13 #define DSPAXRAM_END 0x023FFC
14 #define DSPYRAM_START 0x040000
15 #define DSPYRAM_END 0x04FFFC
16 #define DSPAYRAM_START 0x020000
17 #define DSPAYRAM_END 0x063FFC
18 #define DSPMICRO_START 0x080000
19 #define DSPMICRO_END 0x0B3FFC
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m-rs1.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #clock-cells = <0>;
57 gpios = <&v2m_led_gpios 0 0>;
63 gpios = <&v2m_led_gpios 1 0>;
69 gpios = <&v2m_led_gpios 2 0>;
75 gpios = <&v2m_led_gpios 3 0>;
81 gpios = <&v2m_led_gpios 4 0>;
87 gpios = <&v2m_led_gpios 5 0>;
93 gpios = <&v2m_led_gpios 6 0>;
[all …]

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