1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com> 4 */ 5 6/dts-v1/; 7#include "loongson1.dtsi" 8 9/ { 10 cpu_opp_table: opp-table { 11 compatible = "operating-points-v2"; 12 opp-shared; 13 14 opp-44000000 { 15 opp-hz = /bits/ 64 <44000000>; 16 }; 17 opp-47142000 { 18 opp-hz = /bits/ 64 <47142000>; 19 }; 20 opp-50769000 { 21 opp-hz = /bits/ 64 <50769000>; 22 }; 23 opp-55000000 { 24 opp-hz = /bits/ 64 <55000000>; 25 }; 26 opp-60000000 { 27 opp-hz = /bits/ 64 <60000000>; 28 }; 29 opp-66000000 { 30 opp-hz = /bits/ 64 <66000000>; 31 }; 32 opp-73333000 { 33 opp-hz = /bits/ 64 <73333000>; 34 }; 35 opp-82500000 { 36 opp-hz = /bits/ 64 <82500000>; 37 }; 38 opp-94285000 { 39 opp-hz = /bits/ 64 <94285000>; 40 }; 41 opp-110000000 { 42 opp-hz = /bits/ 64 <110000000>; 43 }; 44 opp-132000000 { 45 opp-hz = /bits/ 64 <132000000>; 46 }; 47 opp-165000000 { 48 opp-hz = /bits/ 64 <165000000>; 49 }; 50 opp-220000000 { 51 opp-hz = /bits/ 64 <220000000>; 52 }; 53 }; 54 55 clkc: clock-controller@1fe78030 { 56 compatible = "loongson,ls1b-clk"; 57 reg = <0x1fe78030 0x8>; 58 clocks = <&xtal>; 59 #clock-cells = <1>; 60 }; 61}; 62 63&soc { 64 syscon: syscon@420 { 65 compatible = "loongson,ls1b-syscon", "syscon"; 66 reg = <0x420 0x8>; 67 }; 68 69 dma: dma-controller@1160 { 70 compatible = "loongson,ls1b-apbdma"; 71 reg = <0x1160 0x4>; 72 interrupt-parent = <&intc0>; 73 interrupts = <13 IRQ_TYPE_EDGE_RISING>, 74 <14 IRQ_TYPE_EDGE_RISING>, 75 <15 IRQ_TYPE_EDGE_RISING>; 76 interrupt-names = "ch0", "ch1", "ch2"; 77 #dma-cells = <1>; 78 }; 79 80 ehci: usb@100000 { 81 compatible = "generic-ehci"; 82 reg = <0x100000 0x100>; 83 interrupt-parent = <&intc1>; 84 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 85 status = "disabled"; 86 }; 87 88 ohci: usb@108000 { 89 compatible = "generic-ohci"; 90 reg = <0x108000 0x100>; 91 interrupt-parent = <&intc1>; 92 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 93 status = "disabled"; 94 }; 95 96 gmac0: ethernet@110000 { 97 compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a"; 98 reg = <0x110000 0x10000>; 99 clocks = <&clkc LS1X_CLKID_AHB>; 100 clock-names = "stmmaceth"; 101 interrupt-parent = <&intc1>; 102 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 103 interrupt-names = "macirq"; 104 loongson,ls1-syscon = <&syscon>; 105 snps,pbl = <1>; 106 status = "disabled"; 107 }; 108 109 gmac1: ethernet@120000 { 110 compatible = "loongson,ls1b-gmac", "snps,dwmac-3.50a"; 111 reg = <0x120000 0x10000>; 112 clocks = <&clkc LS1X_CLKID_AHB>; 113 clock-names = "stmmaceth"; 114 interrupt-parent = <&intc1>; 115 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-names = "macirq"; 117 loongson,ls1-syscon = <&syscon>; 118 snps,pbl = <1>; 119 status = "disabled"; 120 }; 121}; 122 123&apb { 124 clocksource: timer@1c030 { 125 compatible = "loongson,ls1b-pwmtimer"; 126 reg = <0x1c030 0x10>; 127 clocks = <&clkc LS1X_CLKID_APB>; 128 interrupt-parent = <&intc0>; 129 interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; 130 }; 131 132 watchdog: watchdog@1c060 { 133 compatible = "loongson,ls1b-wdt"; 134 reg = <0x1c060 0xc>; 135 clocks = <&clkc LS1X_CLKID_APB>; 136 status = "disabled"; 137 }; 138 139 rtc: rtc@24000 { 140 compatible = "loongson,ls1b-rtc"; 141 reg = <0x24000 0x78>; 142 interrupt-parent = <&intc0>; 143 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 144 status = "disabled"; 145 }; 146 147 ac97: audio-controller@34000 { 148 compatible = "loongson,ls1b-ac97"; 149 reg = <0x34000 0x60>, <0x32420 0x4>, <0x34c4c 0x4>; 150 reg-names = "ac97", "audio-tx", "audio-rx"; 151 dmas = <&dma 1>, <&dma 2>; 152 dma-names = "tx", "rx"; 153 #sound-dai-cells = <0>; 154 status = "disabled"; 155 }; 156 157 nand: nand-controller@38000 { 158 compatible = "loongson,ls1b-nand-controller"; 159 reg = <0x38000 0x24>, <0x38040 0x4>; 160 reg-names = "nand", "nand-dma"; 161 dmas = <&dma 0>; 162 dma-names = "rxtx"; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 status = "disabled"; 166 167 nand@0 { 168 reg = <0>; 169 label = "ls1x-nand"; 170 nand-use-soft-ecc-engine; 171 nand-ecc-algo = "hamming"; 172 }; 173 }; 174}; 175 176&cpu0 { 177 operating-points-v2 = <&cpu_opp_table>; 178}; 179 180&gpio0 { 181 ngpios = <31>; 182}; 183 184&gpio1 { 185 ngpios = <30>; 186}; 187 188&uart1 { 189 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 190}; 191 192&uart2 { 193 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 194}; 195 196&uart3 { 197 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 198}; 199