1*b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 249148020SSam Ravnborg /****************************************************************************/ 349148020SSam Ravnborg 449148020SSam Ravnborg /* 549148020SSam Ravnborg * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. 649148020SSam Ravnborg * 749148020SSam Ravnborg * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) 849148020SSam Ravnborg */ 949148020SSam Ravnborg 1049148020SSam Ravnborg /****************************************************************************/ 1149148020SSam Ravnborg #ifndef m527xsim_h 1249148020SSam Ravnborg #define m527xsim_h 1349148020SSam Ravnborg /****************************************************************************/ 1449148020SSam Ravnborg 157fc82b65SGreg Ungerer #define CPU_NAME "COLDFIRE(m527x)" 16733f31b7SGreg Ungerer #define CPU_INSTR_PER_JIFFY 3 17ce3de78aSGreg Ungerer #define MCF_BUSCLK (MCF_CLK / 2) 187fc82b65SGreg Ungerer 19a12cf0a8SGreg Ungerer #include <asm/m52xxacr.h> 2049148020SSam Ravnborg 2149148020SSam Ravnborg /* 2249148020SSam Ravnborg * Define the 5270/5271 SIM register set addresses. 2349148020SSam Ravnborg */ 24254eef74SGreg Ungerer #define MCFICM_INTC0 (MCF_IPSBAR + 0x0c00) /* Base for Interrupt Ctrl 0 */ 25254eef74SGreg Ungerer #define MCFICM_INTC1 (MCF_IPSBAR + 0x0d00) /* Base for Interrupt Ctrl 1 */ 26254eef74SGreg Ungerer 2749148020SSam Ravnborg #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 2849148020SSam Ravnborg #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ 2949148020SSam Ravnborg #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ 3049148020SSam Ravnborg #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 3149148020SSam Ravnborg #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 3249148020SSam Ravnborg #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 3349148020SSam Ravnborg #define MCFINTC_IRLR 0x18 /* */ 3449148020SSam Ravnborg #define MCFINTC_IACKL 0x19 /* */ 3549148020SSam Ravnborg #define MCFINTC_ICR0 0x40 /* Base ICR register */ 3649148020SSam Ravnborg 3749148020SSam Ravnborg #define MCFINT_VECBASE 64 /* Vector base number */ 3849148020SSam Ravnborg #define MCFINT_UART0 13 /* Interrupt number for UART0 */ 3949148020SSam Ravnborg #define MCFINT_UART1 14 /* Interrupt number for UART1 */ 4049148020SSam Ravnborg #define MCFINT_UART2 15 /* Interrupt number for UART2 */ 412d24b532SSteven King #define MCFINT_I2C0 17 /* Interrupt number for I2C */ 4291d60417SSteven King #define MCFINT_QSPI 18 /* Interrupt number for QSPI */ 43308bfc12SGreg Ungerer #define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */ 44308bfc12SGreg Ungerer #define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */ 45308bfc12SGreg Ungerer #define MCFINT_FECENTC0 29 /* Interrupt number for FEC0 */ 4649148020SSam Ravnborg #define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ 4749148020SSam Ravnborg 48308bfc12SGreg Ungerer #define MCFINT2_VECBASE 128 /* Vector base number 2 */ 49308bfc12SGreg Ungerer #define MCFINT2_FECRX1 23 /* Interrupt number for FEC1 */ 50308bfc12SGreg Ungerer #define MCFINT2_FECTX1 27 /* Interrupt number for FEC1 */ 51308bfc12SGreg Ungerer #define MCFINT2_FECENTC1 29 /* Interrupt number for FEC1 */ 52308bfc12SGreg Ungerer 5320e681fdSGreg Ungerer #define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0) 5420e681fdSGreg Ungerer #define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1) 5520e681fdSGreg Ungerer #define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2) 5620e681fdSGreg Ungerer 57308bfc12SGreg Ungerer #define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0) 58308bfc12SGreg Ungerer #define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0) 59308bfc12SGreg Ungerer #define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0) 60308bfc12SGreg Ungerer #define MCF_IRQ_FECRX1 (MCFINT2_VECBASE + MCFINT2_FECRX1) 61308bfc12SGreg Ungerer #define MCF_IRQ_FECTX1 (MCFINT2_VECBASE + MCFINT2_FECTX1) 62308bfc12SGreg Ungerer #define MCF_IRQ_FECENTC1 (MCFINT2_VECBASE + MCFINT2_FECENTC1) 63308bfc12SGreg Ungerer 646c84a60eSGreg Ungerer #define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI) 65bdee4e26SSteven King #define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1) 662d24b532SSteven King #define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0) 676c84a60eSGreg Ungerer 6849148020SSam Ravnborg /* 6949148020SSam Ravnborg * SDRAM configuration registers. 7049148020SSam Ravnborg */ 7149148020SSam Ravnborg #ifdef CONFIG_M5271 726a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_IPSBAR + 0x40) /* Control */ 736a92e198SGreg Ungerer #define MCFSIM_DACR0 (MCF_IPSBAR + 0x48) /* Base address 0 */ 746a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_IPSBAR + 0x4c) /* Address mask 0 */ 756a92e198SGreg Ungerer #define MCFSIM_DACR1 (MCF_IPSBAR + 0x50) /* Base address 1 */ 766a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_IPSBAR + 0x54) /* Address mask 1 */ 7749148020SSam Ravnborg #endif 7849148020SSam Ravnborg #ifdef CONFIG_M5275 796a92e198SGreg Ungerer #define MCFSIM_DMR (MCF_IPSBAR + 0x40) /* Mode */ 806a92e198SGreg Ungerer #define MCFSIM_DCR (MCF_IPSBAR + 0x44) /* Control */ 816a92e198SGreg Ungerer #define MCFSIM_DCFG1 (MCF_IPSBAR + 0x48) /* Configuration 1 */ 826a92e198SGreg Ungerer #define MCFSIM_DCFG2 (MCF_IPSBAR + 0x4c) /* Configuration 2 */ 836a92e198SGreg Ungerer #define MCFSIM_DBAR0 (MCF_IPSBAR + 0x50) /* Base address 0 */ 846a92e198SGreg Ungerer #define MCFSIM_DMR0 (MCF_IPSBAR + 0x54) /* Address mask 0 */ 856a92e198SGreg Ungerer #define MCFSIM_DBAR1 (MCF_IPSBAR + 0x58) /* Base address 1 */ 866a92e198SGreg Ungerer #define MCFSIM_DMR1 (MCF_IPSBAR + 0x5c) /* Address mask 1 */ 8749148020SSam Ravnborg #endif 8849148020SSam Ravnborg 8957015421SGreg Ungerer /* 90babc08b7SGreg Ungerer * DMA unit base addresses. 91babc08b7SGreg Ungerer */ 92babc08b7SGreg Ungerer #define MCFDMA_BASE0 (MCF_IPSBAR + 0x100) 93babc08b7SGreg Ungerer #define MCFDMA_BASE1 (MCF_IPSBAR + 0x140) 94babc08b7SGreg Ungerer #define MCFDMA_BASE2 (MCF_IPSBAR + 0x180) 95babc08b7SGreg Ungerer #define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0) 96babc08b7SGreg Ungerer 97babc08b7SGreg Ungerer /* 9857015421SGreg Ungerer * UART module. 9957015421SGreg Ungerer */ 10020e681fdSGreg Ungerer #define MCFUART_BASE0 (MCF_IPSBAR + 0x200) 10120e681fdSGreg Ungerer #define MCFUART_BASE1 (MCF_IPSBAR + 0x240) 10220e681fdSGreg Ungerer #define MCFUART_BASE2 (MCF_IPSBAR + 0x280) 1039a6b0c73SGreg Ungerer 1049a6b0c73SGreg Ungerer /* 1059a6b0c73SGreg Ungerer * FEC ethernet module. 1069a6b0c73SGreg Ungerer */ 1079a6b0c73SGreg Ungerer #define MCFFEC_BASE0 (MCF_IPSBAR + 0x1000) 1089a6b0c73SGreg Ungerer #define MCFFEC_SIZE0 0x800 109a630ec1bSGreg Ungerer #ifdef CONFIG_M5275 1109a6b0c73SGreg Ungerer #define MCFFEC_BASE1 (MCF_IPSBAR + 0x1800) 1119a6b0c73SGreg Ungerer #define MCFFEC_SIZE1 0x800 112a630ec1bSGreg Ungerer #endif 113f1554da3Ssfking@fdwdc.com 1146c84a60eSGreg Ungerer /* 1156c84a60eSGreg Ungerer * QSPI module. 1166c84a60eSGreg Ungerer */ 1176c84a60eSGreg Ungerer #define MCFQSPI_BASE (MCF_IPSBAR + 0x340) 1186c84a60eSGreg Ungerer #define MCFQSPI_SIZE 0x40 1196c84a60eSGreg Ungerer 1206c84a60eSGreg Ungerer #ifdef CONFIG_M5271 1216c84a60eSGreg Ungerer #define MCFQSPI_CS0 91 1226c84a60eSGreg Ungerer #define MCFQSPI_CS1 92 1236c84a60eSGreg Ungerer #define MCFQSPI_CS2 99 1246c84a60eSGreg Ungerer #define MCFQSPI_CS3 103 1256c84a60eSGreg Ungerer #endif 1266c84a60eSGreg Ungerer #ifdef CONFIG_M5275 1276c84a60eSGreg Ungerer #define MCFQSPI_CS0 59 1286c84a60eSGreg Ungerer #define MCFQSPI_CS1 60 1296c84a60eSGreg Ungerer #define MCFQSPI_CS2 61 1306c84a60eSGreg Ungerer #define MCFQSPI_CS3 62 1316c84a60eSGreg Ungerer #endif 1326c84a60eSGreg Ungerer 1336c84a60eSGreg Ungerer /* 1346c84a60eSGreg Ungerer * GPIO module. 1356c84a60eSGreg Ungerer */ 136f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5271 137f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000) 138f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001) 139f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002) 140f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003) 141f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004) 142f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005) 143f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006) 144f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007) 145f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008) 146f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009) 147f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A) 148f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B) 149f1554da3Ssfking@fdwdc.com 150f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010) 151f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011) 152f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012) 153f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013) 154f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014) 155f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015) 156f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016) 157f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017) 158f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018) 159f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019) 160f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A) 161f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B) 162f1554da3Ssfking@fdwdc.com 163f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020) 164f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021) 165f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022) 166f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023) 167f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024) 168f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025) 169f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026) 170f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027) 171f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028) 172f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029) 173f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A) 174f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B) 175f1554da3Ssfking@fdwdc.com 176f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030) 177f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031) 178f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032) 179f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033) 180f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034) 181f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035) 182f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036) 183f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037) 184f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038) 185f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039) 186f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A) 187f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B) 188f1554da3Ssfking@fdwdc.com 189f1554da3Ssfking@fdwdc.com /* 190f1554da3Ssfking@fdwdc.com * Generic GPIO support 191f1554da3Ssfking@fdwdc.com */ 192f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_ADDR 193f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR 194f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR 195f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR 196f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR 197f1554da3Ssfking@fdwdc.com 198f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 100 199f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 200f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 20191d60417SSteven King 202f821e349SGreg Ungerer /* 203f821e349SGreg Ungerer * Port Pin Assignment registers. 204f821e349SGreg Ungerer */ 205f821e349SGreg Ungerer #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100040) 206f821e349SGreg Ungerer #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100042) 207f821e349SGreg Ungerer #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100044) 208f821e349SGreg Ungerer #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100045) 209f821e349SGreg Ungerer #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100046) 210f821e349SGreg Ungerer #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100047) 211f821e349SGreg Ungerer #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x100048) 21291d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10004A) 21391d60417SSteven King #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10004C) 214f821e349SGreg Ungerer 215f821e349SGreg Ungerer #define UART0_ENABLE_MASK 0x000f 216f821e349SGreg Ungerer #define UART1_ENABLE_MASK 0x0ff0 217f821e349SGreg Ungerer #define UART2_ENABLE_MASK 0x3000 218f821e349SGreg Ungerer #endif /* CONFIG_M5271 */ 219f1554da3Ssfking@fdwdc.com 220f1554da3Ssfking@fdwdc.com #ifdef CONFIG_M5275 221f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004) 222f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005) 223f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008) 224f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A) 225f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B) 226f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C) 227f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D) 228f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E) 229f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F) 230f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010) 231f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011) 232f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012) 233f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013) 234f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014) 235f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015) 236f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016) 237f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017) 238f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018) 239f1554da3Ssfking@fdwdc.com 240f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020) 241f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021) 242f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024) 243f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026) 244f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027) 245f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028) 246f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029) 247f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A) 248f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B) 249f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C) 250f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D) 251f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E) 252f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F) 253f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030) 254f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031) 255f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032) 256f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033) 257f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034) 258f1554da3Ssfking@fdwdc.com 259f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C) 260f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D) 261f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040) 262f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042) 263f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043) 264f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044) 265f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045) 266f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046) 267f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047) 268f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048) 269f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049) 270f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A) 271f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B) 272f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C) 273f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D) 274f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E) 275f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F) 276f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050) 277f1554da3Ssfking@fdwdc.com 278f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058) 279f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059) 280f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C) 281f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E) 282f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F) 283f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060) 284f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061) 285f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062) 286f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063) 287f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064) 288f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065) 289f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066) 290f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067) 291f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068) 292f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069) 293f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A) 294f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B) 295f1554da3Ssfking@fdwdc.com #define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C) 296f1554da3Ssfking@fdwdc.com 297f1554da3Ssfking@fdwdc.com 298f1554da3Ssfking@fdwdc.com /* 299f1554da3Ssfking@fdwdc.com * Generic GPIO support 300f1554da3Ssfking@fdwdc.com */ 301f1554da3Ssfking@fdwdc.com #define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL 302f1554da3Ssfking@fdwdc.com #define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL 303f1554da3Ssfking@fdwdc.com #define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL 304f1554da3Ssfking@fdwdc.com #define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL 305f1554da3Ssfking@fdwdc.com #define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL 306f1554da3Ssfking@fdwdc.com 307f1554da3Ssfking@fdwdc.com #define MCFGPIO_PIN_MAX 148 308f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_MAX 8 309f1554da3Ssfking@fdwdc.com #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE 31091d60417SSteven King 311f821e349SGreg Ungerer /* 312f821e349SGreg Ungerer * Port Pin Assignment registers. 313f821e349SGreg Ungerer */ 314f821e349SGreg Ungerer #define MCFGPIO_PAR_AD (MCF_IPSBAR + 0x100070) 315f821e349SGreg Ungerer #define MCFGPIO_PAR_CS (MCF_IPSBAR + 0x100071) 316f821e349SGreg Ungerer #define MCFGPIO_PAR_BUSCTL (MCF_IPSBAR + 0x100072) 317f821e349SGreg Ungerer #define MCFGPIO_PAR_USB (MCF_IPSBAR + 0x100076) 318f821e349SGreg Ungerer #define MCFGPIO_PAR_FEC0HL (MCF_IPSBAR + 0x100078) 319f821e349SGreg Ungerer #define MCFGPIO_PAR_FEC1HL (MCF_IPSBAR + 0x100079) 320f821e349SGreg Ungerer #define MCFGPIO_PAR_TIMER (MCF_IPSBAR + 0x10007A) 321f821e349SGreg Ungerer #define MCFGPIO_PAR_UART (MCF_IPSBAR + 0x10007C) 32291d60417SSteven King #define MCFGPIO_PAR_QSPI (MCF_IPSBAR + 0x10007E) 323f821e349SGreg Ungerer #define MCFGPIO_PAR_SDRAM (MCF_IPSBAR + 0x100080) 324f821e349SGreg Ungerer #define MCFGPIO_PAR_FECI2C (MCF_IPSBAR + 0x100082) 325f821e349SGreg Ungerer #define MCFGPIO_PAR_BS (MCF_IPSBAR + 0x100084) 326f821e349SGreg Ungerer 327f821e349SGreg Ungerer #define UART0_ENABLE_MASK 0x000f 328f821e349SGreg Ungerer #define UART1_ENABLE_MASK 0x00f0 329f821e349SGreg Ungerer #define UART2_ENABLE_MASK 0x3f00 330f821e349SGreg Ungerer #endif /* CONFIG_M5275 */ 331f1554da3Ssfking@fdwdc.com 332f1554da3Ssfking@fdwdc.com /* 333f317c71aSGreg Ungerer * PIT timer base addresses. 334f317c71aSGreg Ungerer */ 335f317c71aSGreg Ungerer #define MCFPIT_BASE1 (MCF_IPSBAR + 0x150000) 336f317c71aSGreg Ungerer #define MCFPIT_BASE2 (MCF_IPSBAR + 0x160000) 337f317c71aSGreg Ungerer #define MCFPIT_BASE3 (MCF_IPSBAR + 0x170000) 338f317c71aSGreg Ungerer #define MCFPIT_BASE4 (MCF_IPSBAR + 0x180000) 339f317c71aSGreg Ungerer 340f317c71aSGreg Ungerer /* 341f1554da3Ssfking@fdwdc.com * EPort 342f1554da3Ssfking@fdwdc.com */ 34357b48143SGreg Ungerer #define MCFEPORT_EPPAR (MCF_IPSBAR + 0x130000) 344f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002) 34557b48143SGreg Ungerer #define MCFEPORT_EPIER (MCF_IPSBAR + 0x130003) 346f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004) 347f1554da3Ssfking@fdwdc.com #define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005) 34857b48143SGreg Ungerer #define MCFEPORT_EPFR (MCF_IPSBAR + 0x130006) 349f1554da3Ssfking@fdwdc.com 35049148020SSam Ravnborg /* 35125985edcSLucas De Marchi * Reset Control Unit (relative to IPSBAR). 3524c0b008dSGreg Ungerer */ 3530b2a2139SGreg Ungerer #define MCF_RCR (MCF_IPSBAR + 0x110000) 3540b2a2139SGreg Ungerer #define MCF_RSR (MCF_IPSBAR + 0x110001) 3554c0b008dSGreg Ungerer 3564c0b008dSGreg Ungerer #define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 3574c0b008dSGreg Ungerer #define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 3584c0b008dSGreg Ungerer 3592d24b532SSteven King /* 3602d24b532SSteven King * I2C module. 3612d24b532SSteven King */ 3622d24b532SSteven King #define MCFI2C_BASE0 (MCF_IPSBAR + 0x300) 3632d24b532SSteven King #define MCFI2C_SIZE0 0x40 3642d24b532SSteven King 36549148020SSam Ravnborg /****************************************************************************/ 36649148020SSam Ravnborg #endif /* m527xsim_h */ 367