1*cf4b382aSKeguang Zhang// SPDX-License-Identifier: GPL-2.0 2*cf4b382aSKeguang Zhang/* 3*cf4b382aSKeguang Zhang * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com> 4*cf4b382aSKeguang Zhang */ 5*cf4b382aSKeguang Zhang 6*cf4b382aSKeguang Zhang/dts-v1/; 7*cf4b382aSKeguang Zhang#include "loongson1.dtsi" 8*cf4b382aSKeguang Zhang 9*cf4b382aSKeguang Zhang/ { 10*cf4b382aSKeguang Zhang clkc: clock-controller@1fe78030 { 11*cf4b382aSKeguang Zhang compatible = "loongson,ls1c-clk"; 12*cf4b382aSKeguang Zhang reg = <0x1fe78030 0x8>; 13*cf4b382aSKeguang Zhang clocks = <&xtal>; 14*cf4b382aSKeguang Zhang #clock-cells = <1>; 15*cf4b382aSKeguang Zhang }; 16*cf4b382aSKeguang Zhang}; 17*cf4b382aSKeguang Zhang 18*cf4b382aSKeguang Zhang&soc { 19*cf4b382aSKeguang Zhang syscon: syscon@420 { 20*cf4b382aSKeguang Zhang compatible = "loongson,ls1c-syscon", "syscon"; 21*cf4b382aSKeguang Zhang reg = <0x420 0x8>; 22*cf4b382aSKeguang Zhang }; 23*cf4b382aSKeguang Zhang 24*cf4b382aSKeguang Zhang intc4: interrupt-controller@10a0 { 25*cf4b382aSKeguang Zhang compatible = "loongson,ls1x-intc"; 26*cf4b382aSKeguang Zhang reg = <0x10a0 0x18>; 27*cf4b382aSKeguang Zhang interrupt-controller; 28*cf4b382aSKeguang Zhang interrupt-parent = <&cpu_intc>; 29*cf4b382aSKeguang Zhang interrupts = <6>; 30*cf4b382aSKeguang Zhang #interrupt-cells = <2>; 31*cf4b382aSKeguang Zhang }; 32*cf4b382aSKeguang Zhang 33*cf4b382aSKeguang Zhang gpio2: gpio@10c8 { 34*cf4b382aSKeguang Zhang compatible = "loongson,ls1x-gpio"; 35*cf4b382aSKeguang Zhang reg = <0x10c8 0x4>; 36*cf4b382aSKeguang Zhang gpio-controller; 37*cf4b382aSKeguang Zhang ngpios = <32>; 38*cf4b382aSKeguang Zhang #gpio-cells = <2>; 39*cf4b382aSKeguang Zhang }; 40*cf4b382aSKeguang Zhang 41*cf4b382aSKeguang Zhang gpio3: gpio@10cc { 42*cf4b382aSKeguang Zhang compatible = "loongson,ls1x-gpio"; 43*cf4b382aSKeguang Zhang reg = <0x10cc 0x4>; 44*cf4b382aSKeguang Zhang gpio-controller; 45*cf4b382aSKeguang Zhang ngpios = <32>; 46*cf4b382aSKeguang Zhang #gpio-cells = <2>; 47*cf4b382aSKeguang Zhang }; 48*cf4b382aSKeguang Zhang 49*cf4b382aSKeguang Zhang dma: dma-controller@1160 { 50*cf4b382aSKeguang Zhang compatible = "loongson,ls1c-apbdma", "loongson,ls1b-apbdma"; 51*cf4b382aSKeguang Zhang reg = <0x1160 0x4>; 52*cf4b382aSKeguang Zhang interrupt-parent = <&intc0>; 53*cf4b382aSKeguang Zhang interrupts = <13 IRQ_TYPE_EDGE_RISING>, 54*cf4b382aSKeguang Zhang <14 IRQ_TYPE_EDGE_RISING>, 55*cf4b382aSKeguang Zhang <15 IRQ_TYPE_EDGE_RISING>; 56*cf4b382aSKeguang Zhang interrupt-names = "ch0", "ch1", "ch2"; 57*cf4b382aSKeguang Zhang #dma-cells = <1>; 58*cf4b382aSKeguang Zhang }; 59*cf4b382aSKeguang Zhang 60*cf4b382aSKeguang Zhang emac: ethernet@110000 { 61*cf4b382aSKeguang Zhang compatible = "loongson,ls1c-emac", "snps,dwmac-3.50a"; 62*cf4b382aSKeguang Zhang reg = <0x110000 0x10000>; 63*cf4b382aSKeguang Zhang clocks = <&clkc LS1X_CLKID_AHB>; 64*cf4b382aSKeguang Zhang clock-names = "stmmaceth"; 65*cf4b382aSKeguang Zhang interrupt-parent = <&intc1>; 66*cf4b382aSKeguang Zhang interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 67*cf4b382aSKeguang Zhang interrupt-names = "macirq"; 68*cf4b382aSKeguang Zhang loongson,ls1-syscon = <&syscon>; 69*cf4b382aSKeguang Zhang snps,pbl = <1>; 70*cf4b382aSKeguang Zhang status = "disabled"; 71*cf4b382aSKeguang Zhang }; 72*cf4b382aSKeguang Zhang 73*cf4b382aSKeguang Zhang ehci: usb@120000 { 74*cf4b382aSKeguang Zhang compatible = "generic-ehci"; 75*cf4b382aSKeguang Zhang reg = <0x120000 0x100>; 76*cf4b382aSKeguang Zhang interrupt-parent = <&intc1>; 77*cf4b382aSKeguang Zhang interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 78*cf4b382aSKeguang Zhang status = "disabled"; 79*cf4b382aSKeguang Zhang }; 80*cf4b382aSKeguang Zhang 81*cf4b382aSKeguang Zhang ohci: usb@128000 { 82*cf4b382aSKeguang Zhang compatible = "generic-ohci"; 83*cf4b382aSKeguang Zhang reg = <0x128000 0x100>; 84*cf4b382aSKeguang Zhang interrupt-parent = <&intc1>; 85*cf4b382aSKeguang Zhang interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 86*cf4b382aSKeguang Zhang status = "disabled"; 87*cf4b382aSKeguang Zhang }; 88*cf4b382aSKeguang Zhang}; 89*cf4b382aSKeguang Zhang 90*cf4b382aSKeguang Zhang&apb { 91*cf4b382aSKeguang Zhang watchdog: watchdog@1c060 { 92*cf4b382aSKeguang Zhang compatible = "loongson,ls1c-wdt"; 93*cf4b382aSKeguang Zhang reg = <0x1c060 0xc>; 94*cf4b382aSKeguang Zhang clocks = <&clkc LS1X_CLKID_APB>; 95*cf4b382aSKeguang Zhang status = "disabled"; 96*cf4b382aSKeguang Zhang }; 97*cf4b382aSKeguang Zhang 98*cf4b382aSKeguang Zhang rtc: rtc@24000 { 99*cf4b382aSKeguang Zhang compatible = "loongson,ls1c-rtc"; 100*cf4b382aSKeguang Zhang reg = <0x24000 0x78>; 101*cf4b382aSKeguang Zhang status = "disabled"; 102*cf4b382aSKeguang Zhang }; 103*cf4b382aSKeguang Zhang 104*cf4b382aSKeguang Zhang nand: nand-controller@38000 { 105*cf4b382aSKeguang Zhang compatible = "loongson,ls1c-nand-controller"; 106*cf4b382aSKeguang Zhang reg = <0x38000 0x24>, <0x38040 0x4>; 107*cf4b382aSKeguang Zhang reg-names = "nand", "nand-dma"; 108*cf4b382aSKeguang Zhang dmas = <&dma 0>; 109*cf4b382aSKeguang Zhang dma-names = "rxtx"; 110*cf4b382aSKeguang Zhang #address-cells = <1>; 111*cf4b382aSKeguang Zhang #size-cells = <0>; 112*cf4b382aSKeguang Zhang status = "disabled"; 113*cf4b382aSKeguang Zhang 114*cf4b382aSKeguang Zhang nand@0 { 115*cf4b382aSKeguang Zhang reg = <0>; 116*cf4b382aSKeguang Zhang label = "ls1x-nand"; 117*cf4b382aSKeguang Zhang nand-use-soft-ecc-engine; 118*cf4b382aSKeguang Zhang nand-ecc-algo = "hamming"; 119*cf4b382aSKeguang Zhang }; 120*cf4b382aSKeguang Zhang }; 121*cf4b382aSKeguang Zhang}; 122*cf4b382aSKeguang Zhang 123*cf4b382aSKeguang Zhang&gpio0 { 124*cf4b382aSKeguang Zhang ngpios = <32>; 125*cf4b382aSKeguang Zhang}; 126*cf4b382aSKeguang Zhang 127*cf4b382aSKeguang Zhang&gpio1 { 128*cf4b382aSKeguang Zhang ngpios = <32>; 129*cf4b382aSKeguang Zhang}; 130*cf4b382aSKeguang Zhang 131*cf4b382aSKeguang Zhang&uart1 { 132*cf4b382aSKeguang Zhang interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 133*cf4b382aSKeguang Zhang}; 134*cf4b382aSKeguang Zhang 135*cf4b382aSKeguang Zhang&uart2 { 136*cf4b382aSKeguang Zhang interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 137*cf4b382aSKeguang Zhang}; 138*cf4b382aSKeguang Zhang 139*cf4b382aSKeguang Zhang&uart3 { 140*cf4b382aSKeguang Zhang interrupts = <29 IRQ_TYPE_LEVEL_HIGH>; 141*cf4b382aSKeguang Zhang}; 142