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/freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/vdev_disk/
H A Dpage_alignment.c65 * physical (order-0) page boundary, as the kernel expects to be able in vdev_disk_check_alignment_cb()
104 return (0); in vdev_disk_check_alignment_cb()
125 512, 0x1000, {
126 { 0x0, 0x1000 },
130 512, 0x400, {
131 { 0x0, 0x1000 },
135 512, 0x400, {
136 { 0x0c00, 0x0400 },
140 512, 0x400, {
141 { 0x0200, 0x0e00 },
[all …]
/freebsd/sys/powerpc/include/
H A Dtrap.h39 #define EXC_RSVD 0x0000 /* Reserved */
40 #define EXC_RST 0x0100 /* Reset; all but IBM4xx */
41 #define EXC_MCHK 0x0200 /* Machine Check */
42 #define EXC_DSI 0x0300 /* Data Storage Interrupt */
43 #define EXC_DSE 0x0380 /* Data Segment Interrupt */
44 #define EXC_ISI 0x0400 /* Instruction Storage Interrupt */
45 #define EXC_ISE 0x0480 /* Instruction Segment Interrupt */
46 #define EXC_EXI 0x0500 /* External Interrupt */
47 #define EXC_ALI 0x0600 /* Alignment Interrupt */
48 #define EXC_PGM 0x0700 /* Program Interrupt */
[all …]
/freebsd/sys/dev/bhnd/bhndb/
H A Dbhndb_pcireg.h36 * - PCI (cid=0x804, revision <= 12)
40 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
41 * [0x1000+0x0800] fixed SPROM shadow
42 * [0x1800+0x0E00] fixed pci core device registers
43 * [0x1E00+0x0200] fixed pci core siba config registers
47 * - PCI (cid=0x804, revision >= 13)
48 * - PCIE (cid=0x820) with ChipCommon (revision <= 31)
52 * [0x0000+0x1000] dynamic mapped backplane address space (window 0).
53 * [0x1000+0x1000] fixed SPROM shadow
54 * [0x2000+0x1000] fixed pci/pcie core registers
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSymbolCOFF.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
21 mutable uint16_t Type = 0;
24 SF_ClassMask = 0x00FF,
25 SF_ClassShift = 0,
27 SF_SafeSEH = 0x0100,
28 SF_WeakExternalCharacteristicsMask = 0x0E00,
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Drcar-gen4-pci-ep.yaml100 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
101 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
102 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
103 <0 0xfe000000 0 0x400000>;
H A Drcar-gen4-pci-host.yaml98 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
99 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
100 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
101 <0 0xfe000000 0 0x400000>;
117 bus-range = <0x00 0xff>;
119 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
120 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
121 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
123 interrupt-map-mask = <0 0 0 7>;
124 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Dgate.txt31 - #clock-cells : from common clock binding; shall be set to 0
45 #clock-cells = <0>;
48 reg = <0x0a00>;
53 #clock-cells = <0>;
56 reg = <0x0a00>;
61 #clock-cells = <0>;
64 reg = <0x0e00>;
65 ti,bit-shift = <0>;
69 #clock-cells = <0>;
72 reg = <0x059c>;
[all …]
/freebsd/sys/powerpc/mpc85xx/
H A Dpci_mpc85xx.c77 #define REG_CFG_ADDR 0x0000
78 #define CONFIG_ACCESS_ENABLE 0x80000000
80 #define REG_CFG_DATA 0x0004
81 #define REG_INT_ACK 0x0008
83 #define REG_PEX_IP_BLK_REV1 0x0bf8
84 #define IP_MJ_M 0x0000ff00
86 #define IP_MN_M 0x000000ff
87 #define IP_MN_S 0
89 #define REG_POTAR(n) (0x0c00 + 0x20 * (n))
90 #define REG_POTEAR(n) (0x0c04 + 0x20 * (n))
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr8a779f0.dtsi17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
[all …]
H A Dr8a779g0.dtsi20 #clock-cells = <0>;
21 clock-frequency = <0>;
27 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
88 a76_0: cpu@0 {
90 reg = <0>;
102 reg = <0x100>;
114 reg = <0x10000>;
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c38 * alt-0 - rubbish SDHCI (0x7e202000) aka sdhost
39 * alt-3 - advanced SDHCI (0x7e300000) aka sdhci/mmc/sdio
44 * brcm,pins = <0x30 0x31 0x32 0x33 0x34 0x35>;
45 * brcm,function = <0x7>;
46 * brcm,pull = <0x0 0x2 0x2 0x2 0x2 0x2>;
47 * phandle = <0x17>;
50 * brcm,pins = <0x22 0x23 0x24 0x25 0x26 0x27>;
51 * brcm,function = <0x4>;
52 * brcm,pull = <0x0 0x2 0x2 0x2 0x2 0x2>;
53 * phandle = <0x18>;
[all …]
/freebsd/sys/x86/iommu/
H A Damd_reg.h38 #define AMDIOMMU_DEVTAB_BASE 0x0000
39 #define AMDIOMMU_CMDBUF_BASE 0x0008
40 #define AMDIOMMU_EVNTLOG_BASE 0x0010
41 #define AMDIOMMU_CTRL 0x0018
42 #define AMDIOMMU_EXCL_BASE 0x0020
43 #define AMDIOMMU_EXCL_RANGE 0x0028
44 #define AMDIOMMU_EFR 0x0030
45 #define AMDIOMMU_PPRLOG_BASE 0x0038
46 #define AMDIOMMU_HWEV_UPPER 0x0040
47 #define AMDIOMMU_HWEV_LOWER 0x0048
[all …]
/freebsd/sys/dev/cesa/
H A Dcesa.h81 #define CESA_MAX_PACKET_SIZE (CESA_SRAM_SIZE - CESA_DATA(0))
114 } while (0)
121 } while (0)
274 #define CESA_CSHD_MAC (0 << 0)
275 #define CESA_CSHD_ENC (1 << 0)
276 #define CESA_CSHD_MAC_AND_ENC (2 << 0)
277 #define CESA_CSHD_ENC_AND_MAC (3 << 0)
278 #define CESA_CSHD_OP_MASK (3 << 0)
297 #define CESA_CSH_AES_KLEN_128 (0 << 24)
307 #define CESA_ICR 0x0E20
[all …]
/freebsd/sys/dev/bhnd/siba/
H A Dsibareg.h47 #define SIBA_ENUM_SIZE 0x00100000 /**< size of the enumeration space */
64 * [0x0000-0x0dff] core registers
65 * [0x0e00-0x0eff] SIBA_R1 registers (sonics >= 2.3)
66 * [0x0f00-0x0fff] SIBA_R0 registers
69 #define SIBA_CFG0_OFFSET 0xf00 /**< first configuration block */
70 #define SIBA_CFG1_OFFSET 0xe00 /**< second configuration block (sonics >= 2.3) */
71 #define SIBA_CFG_SIZE 0x100 /**< cfg register block size */
83 #define SIBA_CFG0_IPSFLAG 0x08 /**< initiator port ocp slave flag */
84 #define SIBA_CFG0_TPSFLAG 0x18 /**< target port ocp slave flag */
85 #define SIBA_CFG0_TMERRLOGA 0x48 /**< sonics >= 2.3 */
[all …]
/freebsd/sys/arm64/include/
H A Dcmn600_reg.h34 #define CMN600_COMMON_PMU_EVENT_SEL 0x2000 /* rw */
36 #define CMN600_COMMON_PMU_EVENT_SEL_OCC_MASK (0x7UL << 32)
68 #define POR_CFGM_NODE_INFO 0x0000 /* ro */
69 #define POR_CFGM_NODE_INFO_LOGICAL_ID_MASK 0xffff00000000UL
71 #define POR_CFGM_NODE_INFO_NODE_ID_MASK 0xffff0000
73 #define POR_CFGM_NODE_INFO_NODE_TYPE_MASK 0xffff
74 #define POR_CFGM_NODE_INFO_NODE_TYPE_SHIFT 0
76 #define NODE_ID_SUB_MASK 0x3
77 #define NODE_ID_SUB_SHIFT 0
78 #define NODE_ID_PORT_MASK 0x4
[all …]
/freebsd/sys/arm64/arm64/
H A Dgic_v3_reg.h40 #define GIC_PRIORITY_MAX (0x00UL)
42 #define GIC_PRIORITY_MIN (0xFCUL)
53 #define GICD_CTLR_G1 (1 << 0)
64 #define GICD_TYPER_IDBITS(n) ((((n) >> 19) & 0x1F) + 1)
69 #define GICD_STATUSR 0x0010
71 #define GICD_SETSPI_NSR 0x0040
72 #define GICD_CLRSPI_NSR 0x0048
73 #define GICD_SETSPI_SR 0x0050
74 #define GICD_CLRSPI_SR 0x0058
75 #define GICD_SPI_INTID_MASK 0x3ff
[all …]
/freebsd/sys/dev/mii/
H A Dciphyreg.h44 #define CIPHY_MII_BMCR 0x00
45 #define CIPHY_BMCR_RESET 0x8000
46 #define CIPHY_BMCR_LOOP 0x4000
47 #define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
48 #define CIPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
49 #define CIPHY_BMCR_PDOWN 0x0800 /* Power down */
50 #define CIPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
51 #define CIPHY_BMCR_FDX 0x0100 /* Duplex mode */
52 #define CIPHY_BMCR_CTEST 0x0080 /* Collision test enable */
53 #define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
[all …]
/freebsd/sys/contrib/ncsw/Peripherals/BM/
H A Dbman_low.c58 #define REG_RCR_PI_CINH 0x0000
59 #define REG_RCR_CI_CINH 0x0004
60 #define REG_RCR_ITR 0x0008
61 #define REG_CFG 0x0100
62 #define REG_SCN(n) (0x0200 + ((n) << 2))
63 #define REG_ISR 0x0e00
64 #define REG_IER 0x0e04
65 #define REG_ISDR 0x0e08
66 #define REG_IIR 0x0e0c
69 #define CL_CR 0x0000
[all …]
/freebsd/sys/dev/usb/controller/
H A Ddwc_otgreg.h32 #define DOTG_GOTGCTL 0x0000
33 #define DOTG_GOTGINT 0x0004
34 #define DOTG_GAHBCFG 0x0008
35 #define DOTG_GUSBCFG 0x000C
36 #define DOTG_GRSTCTL 0x0010
37 #define DOTG_GINTSTS 0x0014
38 #define DOTG_GINTMSK 0x0018
39 #define DOTG_GRXSTSRD 0x001C
40 #define DOTG_GRXSTSRH 0x001C
41 #define DOTG_GRXSTSPD 0x0020
[all …]
/freebsd/sys/dev/pci/
H A Dpcireg.h53 #define PCIE_ARI_SLOTMAX 0
59 #define PCI_RID_FUNC_SHIFT 0
74 #define PCIE_ARI_RID2SLOT(rid) (0)
83 #define PCIR_DEVVENDOR 0x00
84 #define PCIR_VENDOR 0x00
85 #define PCIR_DEVICE 0x02
86 #define PCIR_COMMAND 0x04
87 #define PCIM_CMD_PORTEN 0x0001
88 #define PCIM_CMD_MEMEN 0x0002
89 #define PCIM_CMD_BUSMASTEREN 0x0004
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dapple6 0 search/1/t FiLeStArTfIlEsTaRt binscii (apple ][) text
7 0 string \x0aGL Binary II (apple ][) data
8 0 string \x76\xff Squeezed (apple ][) data
9 0 string NuFile NuFile archive (apple ][) data
10 0 string N\xf5F\xe9l\xe5 NuFile archive (apple ][) data
11 0 belong 0x00051600 AppleSingle encoded Macintosh file
12 0 belong 0x00051607 AppleDouble encoded Macintosh file
18 0 string A2R
20 >>0 use applesauce
22 >>0 use applesauce
[all …]
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_plx.c108 #define PLX_NT0_BASE 0x3E000
109 #define PLX_NT1_BASE 0x3C000
111 #define PLX_NTX_LINK_OFFSET 0x01000
115 (PLX_NTX_BASE(sc) + ((sc)->link ? PLX_NTX_LINK_OFFSET : 0))
117 (PLX_NTX_BASE(sc) + ((sc)->link ? 0 : PLX_NTX_LINK_OFFSET))
142 #define PLX_PORT_CONTROL(sc) (PLX_STATION_PORT_BASE(sc) + 0x208)
153 case 0x87a010b5: in ntb_plx_probe()
156 case 0x87a110b5: in ntb_plx_probe()
159 case 0x87b010b5: in ntb_plx_probe()
162 case 0x87b110b5: in ntb_plx_probe()
[all …]
/freebsd/sys/contrib/dev/rtw88/
H A Ddebug.c84 return 0; in rtw_debugfs_close()
122 seq_printf(m, "reg 0x%03x: 0x%02x\n", addr, val); in rtw_debugfs_get_read_reg()
126 seq_printf(m, "reg 0x%03x: 0x%04x\n", addr, val); in rtw_debugfs_get_read_reg()
130 seq_printf(m, "reg 0x%03x: 0x%08x\n", addr, val); in rtw_debugfs_get_read_reg()
133 return 0; in rtw_debugfs_get_read_reg()
151 seq_printf(m, "rf_read path:%d addr:0x%08x mask:0x%08x val=0x%08x\n", in rtw_debugfs_get_rf_read()
154 return 0; in rtw_debugfs_get_rf_read()
166 return 0; in rtw_debugfs_get_fix_rate()
170 return 0; in rtw_debugfs_get_fix_rate()
179 memset(tmp, 0, size); in rtw_debugfs_copy_from_user()
[all …]
/freebsd/sys/contrib/ncsw/Peripherals/QM/
H A Dqman_low.h54 #define REG_EQCR_PI_CINH 0x0000
55 #define REG_EQCR_CI_CINH 0x0004
56 #define REG_EQCR_ITR 0x0008
57 #define REG_DQRR_PI_CINH 0x0040
58 #define REG_DQRR_CI_CINH 0x0044
59 #define REG_DQRR_ITR 0x0048
60 #define REG_DQRR_DCAP 0x0050
61 #define REG_DQRR_SDQCR 0x0054
62 #define REG_DQRR_VDQCR 0x0058
63 #define REG_DQRR_PDQCR 0x005c
[all …]
/freebsd/sys/dev/sk/
H A Dif_skreg.h54 #define SK_GENESIS 0x0A
55 #define SK_YUKON 0xB0
56 #define SK_YUKON_LITE 0xB1
57 #define SK_YUKON_LP 0xB2
58 #define SK_YUKON_FAMILY(x) ((x) & 0xB0)
61 #define SK_YUKON_LITE_REV_A0 0x0 /* invented, see test in skc_attach. */
62 #define SK_YUKON_LITE_REV_A1 0x3
63 #define SK_YUKON_LITE_REV_A3 0x7
68 #define VENDORID_SK 0x1148
73 #define VENDORID_MARVELL 0x11AB
[all …]

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